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| REJ09B0199-0200 The revision list can be viewed directly by clicking the title page. The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to the relevant text. 32 H8SX/1582 Hardware Manual Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1500 Series H8SX/1582 R5F61582 Rev.2.00 Revision Date: Mar. 15, 2006 Rev. 2.00 Mar. 15, 2006 page ii of xxxviii Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party. 2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any thirdparty's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor home page (http://www.renesas.com). 4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein. Rev. 2.00 Mar. 15, 2006 page iii of xxxviii General Precautions on Handling of Product 1. Treatment of NC Pins Note: Do not connect anything to the NC pins. The NC (not connected) pins are either not connected to any of the internal circuitry or are used as test pins or to reduce noise. If something is connected to the NC pins, the operation of the LSI is not guaranteed. 2. Treatment of Unused Input Pins Note: Fix all unused input pins to high or low level. Generally, the input pins of CMOS products are high-impedance input pins. If unused pins are in their open states, intermediate levels are induced by noise in the vicinity, a passthrough current flows internally, and a malfunction may occur. 3. Processing before Initialization Note: When power is first supplied, the product's state is undefined. The states of internal circuits are undefined until full power is supplied throughout the chip and a low level is input on the reset pin. During the period where the states are undefined, the register settings and the output state of each pin are also undefined. Design your system so that it does not malfunction because of processing while it is in this undefined state. For those products which have a reset function, reset the LSI immediately after the power supply has been turned on. 4. Prohibition of Access to Undefined or Reserved Addresses Note: Access to undefined or reserved addresses is prohibited. The undefined or reserved addresses may be used to expand functions, or test registers may have been be allocated to these addresses. Do not access these registers; the system's operation is not guaranteed if they are accessed. Rev. 2.00 Mar. 15, 2006 page iv of xxxviii Configuration of This Manual This manual comprises the following items: 1. 2. 3. 4. 5. 6. General Precautions on Handling of Product Configuration of This Manual Preface Contents Overview Description of Functional Modules * CPU and System-Control Modules * On-Chip Peripheral Modules The configuration of the functional description of each module differs according to the module. However, the generic style includes the following items: i) Feature ii) Input/Output Pin iii) Register Description iv) Operation v) Usage Note When designing an application system that includes this LSI, take notes into account. Each section includes notes in relation to the descriptions given, and usage notes are given, as required, as the final part of each section. 7. List of Registers 8. Electrical Characteristics 9. Appendix 10. Main Revisions and Additions in this Edition (only for revised versions) The list of revisions is a summary of points that have been revised or added to earlier versions. This does not include all of the revised contents. For details, see the actual locations in this manual. 11. Index Rev. 2.00 Mar. 15, 2006 page v of xxxviii Preface The H8SX/1582 is a single-chip microcomputer made up of the high-speed internal 32-bit H8SX CPU as its core, and the peripheral functions required to configure a system. The H8SX CPU is upward compatible with the H8/300, H8/300H, and H8S CPUs. Target Users: This manual was written for users who will be using the H8SX/1582 in the design of application systems. Target users are expected to understand the fundamentals of electrical circuits, logical circuits, and microcomputers. Objective: This manual was written to explain the hardware functions and electrical characteristics of the H8SX/1582 to the target users. Refer to the H8SX Family Software Manual for a detailed description of the instruction set. Notes on reading this manual: In order to understand the overall functions of the chip Read the manual according to the contents. This manual can be roughly categorized into parts on the CPU, system control functions, and peripheral functions. In order to understand the details of the CPU's functions Read the H8SX Family Software Manual. In order to understand the details of a register when its name is known Read the index that is the final part of the manual to find the page number of the entry on the register. The addresses, bits, and initial values of the registers are summarized in section 20, List of Registers. Examples: Register name: The following notation is used for cases when the same or a similar function, e.g. 16-bit timer pulse unit or serial communication interface, is implemented on more than one channel: XXX_N (XXX is the register name and N is the channel number) Bit order: The MSB is on the left and the LSB is on the right. Number notation: Binary is B'xxxx, hexadecimal is H'xxxx, decimal is xxxx. Signal notation: An overbar is added to a low-active signal: xxxx Related Manuals: The latest versions of all related manuals are available from our web site. Please ensure you have the latest versions of all documents you require. http://www.renesas.com/ Rev. 2.00 Mar. 15, 2006 page vi of xxxviii H8SX/1582 manuals: Document Title H8SX/1582 Hardware Manual H8/SX Family Software Manual Document No. This manual REJ09B0102 Rev. 2.00 Mar. 15, 2006 page vii of xxxviii Rev. 2.00 Mar. 15, 2006 page viii of xxxviii Contents Section 1 Overview................................................................................................1 1.1 1.2 1.3 Features.................................................................................................................................. 1 Block Diagram ....................................................................................................................... 2 Pin Assignments..................................................................................................................... 3 1.3.1 Pin Assignments ....................................................................................................... 3 1.3.2 Pin Configuration in Each Operating Mode.............................................................. 4 1.3.3 Pin Functions ............................................................................................................ 8 Section 2 CPU......................................................................................................17 2.1 2.2 Features................................................................................................................................ 17 CPU Operating Modes......................................................................................................... 19 2.2.1 Normal Mode.......................................................................................................... 19 2.2.2 Middle Mode .......................................................................................................... 21 2.2.3 Advanced Mode...................................................................................................... 22 2.2.4 Maximum Mode ..................................................................................................... 23 Instruction Fetch .................................................................................................................. 25 Address Space...................................................................................................................... 25 Registers............................................................................................................................... 26 2.5.1 General Registers.................................................................................................... 27 2.5.2 Program Counter (PC) ............................................................................................ 28 2.5.3 Condition-Code Register (CCR)............................................................................. 28 2.5.4 Extended Control Register (EXR) .......................................................................... 30 2.5.5 Vector Base Register (VBR)................................................................................... 30 2.5.6 Short Address Base Register (SBR)........................................................................ 30 2.5.7 Multiply-Accumulate Register (MAC)................................................................... 31 2.5.8 Initial Values of CPU Registers .............................................................................. 31 Data Formats........................................................................................................................ 31 2.6.1 General Register Data Formats ............................................................................... 31 2.6.2 Memory Data Formats ............................................................................................ 33 Instruction Set ...................................................................................................................... 34 2.7.1 Instructions and Addressing Modes........................................................................ 36 2.7.2 Table of Instructions Classified by Function .......................................................... 40 2.7.3 Basic Instruction Formats ....................................................................................... 51 Addressing Modes and Effective Address Calculation........................................................ 52 2.8.1 Register Direct--Rn ............................................................................................... 53 2.8.2 Register Indirect--@ERn ....................................................................................... 53 2.8.3 Register Indirect with Displacement --@(d:2, ERn), @(d:16, ERn), or @(d:32, ERn)...................................................................................................... 53 2.3 2.4 2.5 2.6 2.7 2.8 Rev. 2.00 Mar. 15, 2006 page ix of xxxviii 2.9 Index Register Indirect with Displacement--@(d:16,RnL.B), @(d:32,RnL.B), @(d:16,Rn.W), @(d:32,Rn.W), @(d:16,ERn.L), or @(d:32,ERn.L)..................... 54 2.8.5 Register Indirect with Post-Increment, Pre-Decrement, Pre-Increment, or Post-Decrement--@ERn+, @-ERn, @+ERn, or @ERn- ................................ 54 2.8.6 Absolute Address--@aa:8, @aa:16, @aa:24, or @aa:32....................................... 55 2.8.7 Immediate--#xx ..................................................................................................... 56 2.8.8 Program-Counter Relative--@(d:8, PC) or @(d:16, PC) ...................................... 57 2.8.9 Program-Counter Relative with Index Register--@(RnL.B, PC), @(Rn.W, PC), or @(ERn.L, PC) .................................................................................................... 57 2.8.10 Memory Indirect--@@aa:8 ............................................................................... 57 2.8.11 Extended Memory Indirect--@@vec:7 ............................................................. 58 2.8.12 Effective Address Calculation ............................................................................ 58 2.8.13 MOVA Instruction.............................................................................................. 60 Processing States.................................................................................................................. 61 2.8.4 Section 3 MCU Operating Modes ....................................................................... 63 3.1 3.2 Operating Mode Selection ................................................................................................... 63 Register Descriptions........................................................................................................... 63 3.2.1 Mode Control Register (MDCR) ............................................................................ 64 3.2.2 System Control Register (SYSCR)......................................................................... 65 Operating Mode Descriptions .............................................................................................. 67 3.3.1 Mode 1.................................................................................................................... 67 3.3.2 Mode 2.................................................................................................................... 67 3.3.3 Mode 3.................................................................................................................... 67 Address Map ........................................................................................................................ 68 3.4.1 Address Map........................................................................................................... 68 3.3 3.4 Section 4 Exception Handling ............................................................................. 69 4.1 4.2 4.3 Exception Handling Types and Priority............................................................................... 69 Exception Sources and Exception Handling Vector Table .................................................. 70 Reset .................................................................................................................................... 72 4.3.1 Reset Exception Handling ...................................................................................... 72 4.3.2 Interrupts after Reset............................................................................................... 73 4.3.3 On-Chip Peripheral Functions after Reset Release................................................. 73 Traces................................................................................................................................... 74 Address Error....................................................................................................................... 74 4.5.1 Address Error Source.............................................................................................. 74 4.5.2 Address Error Exception Handling......................................................................... 76 Interrupts.............................................................................................................................. 77 4.6.1 Interrupt Sources..................................................................................................... 77 4.6.2 Interrupt Exception Handling ................................................................................. 77 Instruction Exception Handling ........................................................................................... 78 4.7.1 Trap Instruction ...................................................................................................... 78 4.4 4.5 4.6 4.7 Rev. 2.00 Mar. 15, 2006 page x of xxxviii 4.8 4.9 4.7.2 Exception Handling by General Illegal Instruction................................................. 79 Stack Status after Exception Handling................................................................................. 80 Usage Note........................................................................................................................... 80 Section 5 Interrupt Controller ..............................................................................83 5.1 5.2 5.3 Features................................................................................................................................ 83 Input/Output Pins ................................................................................................................. 85 Register Descriptions ........................................................................................................... 85 5.3.1 Interrupt Control Register (INTCR) ....................................................................... 86 5.3.2 CPU Priority Control Register (CPUPCR) ............................................................. 87 5.3.3 Interrupt Priority Registers A to G, I, K to O, Q, and R (IPRA to IPRG, IPRI, IPRK to IPRO, IPRQ, and IPRR) ....................................... 89 5.3.4 IRQ Enable Register (IER) ..................................................................................... 91 5.3.5 IRQ Sense Control Registers H and L (ISCRH and ISCRL) .................................. 93 5.3.6 IRQ Status Register (ISR)....................................................................................... 98 5.3.7 Software Standby Release IRQ Enable Register (SSIER) ...................................... 99 Interrupt Sources................................................................................................................ 100 5.4.1 External Interrupts ................................................................................................ 100 5.4.2 Internal Interrupts ................................................................................................. 101 Interrupt Exception Handling Vector Table....................................................................... 102 Interrupt Control Modes and Interrupt Operation .............................................................. 109 5.6.1 Interrupt Control Mode 0 ...................................................................................... 109 5.6.2 Interrupt Control Mode 2 ...................................................................................... 111 5.6.3 Interrupt Exception Handling Sequence ............................................................... 113 5.6.4 Interrupt Response Times ..................................................................................... 114 5.6.5 DTC and DMAC Activation by Interrupt ............................................................. 115 CPU Priority Control Function Over DTC and DMAC..................................................... 118 Usage Notes ....................................................................................................................... 121 5.8.1 Conflict between Interrupt Generation and Disabling .......................................... 121 5.8.2 Instructions that Disable Interrupts ....................................................................... 122 5.8.3 Times when Interrupts are Disabled ..................................................................... 122 5.8.4 Interrupts during Execution of EEPMOV Instruction........................................... 122 5.8.5 Interrupts during Execution of MOVMD and MOVSD Instructions.................... 123 5.8.6 Interrupt Flags of Peripheral Modules .................................................................. 123 5.4 5.5 5.6 5.7 5.8 Section 6 Bus Controller (BSC).........................................................................125 6.1 6.2 6.3 6.4 6.5 Features.............................................................................................................................. 125 Register Descriptions ......................................................................................................... 126 6.2.1 Bus Control Register 2 (BCR2) ............................................................................ 126 Bus Configuration.............................................................................................................. 127 Multi-Clock Function......................................................................................................... 128 Internal Bus........................................................................................................................ 129 6.5.1 Access to Internal Address Space ......................................................................... 129 Rev. 2.00 Mar. 15, 2006 page xi of xxxviii 6.6 6.7 6.8 6.9 Write Data Buffer Function ............................................................................................... 130 6.6.1 Write Data Buffer Function for Peripheral Module.............................................. 130 Bus Arbitration .................................................................................................................. 131 6.7.1 Operation .............................................................................................................. 131 6.7.2 Bus Transfer Timing............................................................................................. 131 Bus Controller Operation in Reset ..................................................................................... 133 Usage Notes ....................................................................................................................... 133 Section 7 DMA Controller (DMAC)................................................................. 135 7.1 7.2 Features.............................................................................................................................. 135 Register Descriptions......................................................................................................... 138 7.2.1 DMA Source Address Register (DSAR) .............................................................. 139 7.2.2 DMA Destination Address Register (DDAR) ...................................................... 140 7.2.3 DMA Offset Register (DOFR).............................................................................. 141 7.2.4 DMA Transfer Count Register (DTCR) ............................................................... 142 7.2.5 DMA Block Size Register (DBSR) ...................................................................... 143 7.2.6 DMA Mode Control Register (DMDR)................................................................ 144 7.2.7 DMA Address Control Register (DACR)............................................................. 153 7.2.8 DMA Module Request Select Register (DMRSR) ............................................... 160 Transfer Modes .................................................................................................................. 160 Operations.......................................................................................................................... 161 7.4.1 Address Modes ..................................................................................................... 161 7.4.2 Transfer Modes..................................................................................................... 165 7.4.3 Activation Sources................................................................................................ 169 7.4.4 Bus Access Modes................................................................................................ 171 7.4.5 Extended Repeat Area Function ........................................................................... 172 7.4.6 Address Update Function using Offset ................................................................. 175 7.4.7 Register during DMA Transfer............................................................................. 179 7.4.8 Priority of Channels.............................................................................................. 184 7.4.9 DMA Basic Bus Cycle.......................................................................................... 185 7.4.10 Bus Cycles in Dual Address Mode ................................................................... 186 7.4.11 Bus Cycles in Single Address Mode................................................................. 194 DMA Transfer End ............................................................................................................ 199 Relationship among DMAC and Other Bus Masters ......................................................... 201 7.6.1 CPU Priority Control Function Over DMAC ....................................................... 201 7.6.2 Bus Arbitration among DMAC and Other Bus Masters ....................................... 202 Interrupt Sources................................................................................................................ 203 Notes on Usage .................................................................................................................. 206 7.3 7.4 7.5 7.6 7.7 7.8 Section 8 Data Transfer Controller (DTC)........................................................ 207 8.1 8.2 Features.............................................................................................................................. 207 Register Descriptions......................................................................................................... 209 8.2.1 DTC Mode Register A (MRA) ............................................................................. 210 Rev. 2.00 Mar. 15, 2006 page xii of xxxviii 8.3 8.4 8.5 8.6 8.7 8.8 8.9 8.2.2 DTC Mode Register B (MRB).............................................................................. 211 8.2.3 DTC Source Address Register (SAR)................................................................... 212 8.2.4 DTC Destination Address Register (DAR)........................................................... 213 8.2.5 DTC Transfer Count Register A (CRA) ............................................................... 213 8.2.6 DTC Transfer Count Register B (CRB)................................................................ 214 8.2.7 DTC Enable Registers A to H (DTCERA to DTCERH) ...................................... 214 8.2.8 DTC Control Register (DTCCR) .......................................................................... 216 8.2.9 DTC Vector Base Register (DTCVBR)................................................................ 217 Activation Sources ............................................................................................................. 217 Location of Transfer Information and DTC Vector Table ................................................. 218 Operation ........................................................................................................................... 223 8.5.1 Bus Cycle Division ............................................................................................... 225 8.5.2 Transfer Information Read Skip Function ............................................................ 227 8.5.3 Transfer Information Writeback Skip Function .................................................... 228 8.5.4 Normal Transfer Mode ......................................................................................... 228 8.5.5 Repeat Transfer Mode........................................................................................... 229 8.5.6 Block Transfer Mode ............................................................................................ 231 8.5.7 Chain Transfer ...................................................................................................... 232 8.5.8 Operation Timing.................................................................................................. 233 8.5.9 Number of DTC Execution Cycles ....................................................................... 235 8.5.10 DTC Bus Release Timing ................................................................................. 236 8.5.11 DTC Priority Level Control to the CPU ........................................................... 236 DTC Usage Procedure ....................................................................................................... 237 8.6.1 Activation by Interrupt.......................................................................................... 237 Examples of Use of the DTC ............................................................................................. 238 8.7.1 Normal Transfer Mode ......................................................................................... 238 8.7.2 Chain Transfer ...................................................................................................... 239 8.7.3 Chain Transfer when Counter = 0......................................................................... 240 Interrupt Sources................................................................................................................ 241 Usage Notes ....................................................................................................................... 241 8.9.1 Module Stop Mode Setting ................................................................................... 241 8.9.2 On-Chip RAM ...................................................................................................... 241 8.9.3 DMAC Transfer End Interrupt.............................................................................. 242 8.9.4 DTCE Bit Setting.................................................................................................. 242 8.9.5 Chain Transfer ...................................................................................................... 242 8.9.6 Transfer Information Start Address, Source Address, and Destination Address ....................................................................................... 242 8.9.7 Endian ................................................................................................................... 242 Section 9 I/O Ports .............................................................................................243 9.1 Register Descriptions ......................................................................................................... 249 9.1.1 Data Direction Register (PnDDR) (n = 1 to 3, 6, A, B, D, H, I, J, and K)............ 251 9.1.2 Data Register (PnDR) (n = 1 to 3, 6, A, B, D, H, I, J, and K)............................... 251 Rev. 2.00 Mar. 15, 2006 page xiii of xxxviii 9.2 9.3 9.4 9.1.3 Port Register (PORTn) (n = 1 to 6, A, B, D, H, I, J, and K) ................................. 252 9.1.4 Input Buffer Control Register (PnICR) (n = 1 to 6, A, B, D, H, I, J, and K) ........ 252 9.1.5 Pull-Up MOS Control Register (PnPCR) (n = D, H, I, J, and K) ......................... 253 9.1.6 Open-Drain Control Register (PnODR) (n = 2).................................................... 254 9.1.7 Port H Realtime Input Data Register (PHRTIDR)................................................ 254 Output Buffer Control........................................................................................................ 255 9.2.1 Port 1..................................................................................................................... 255 9.2.2 Port 2..................................................................................................................... 258 9.2.3 Port 3..................................................................................................................... 261 9.2.4 Port 6..................................................................................................................... 264 9.2.5 Port A.................................................................................................................... 267 9.2.6 Port B.................................................................................................................... 269 9.2.7 Port D.................................................................................................................... 270 9.2.8 Port H.................................................................................................................... 273 9.2.9 Port I ..................................................................................................................... 274 9.2.10 Port J ................................................................................................................. 274 9.2.11 Port K................................................................................................................ 277 Port Function Controller .................................................................................................... 284 9.3.1 Port Function Control Register 9 (PFCR9)........................................................... 284 9.3.2 Port Function Control Register A (PFCRA) ......................................................... 286 9.3.3 Port Function Control Register B (PFCRB) ......................................................... 287 Usage Notes ....................................................................................................................... 289 9.4.1 Notes on Input Buffer Control Register (ICR) Setting ......................................... 289 9.4.2 Notes on Port Function Control Register (PFCR) Settings................................... 289 Section 10 16-Bit Timer Pulse Unit (TPU) ....................................................... 291 10.1 10.2 10.3 Features............................................................................................................................. 291 Input/Output Pins.............................................................................................................. 298 Register Descriptions........................................................................................................ 300 10.3.1 Timer Control Register (TCR).......................................................................... 305 10.3.2 Timer Mode Register (TMDR)......................................................................... 310 10.3.3 Timer I/O Control Register (TIOR).................................................................. 311 10.3.4 Timer Interrupt Enable Register (TIER)........................................................... 329 10.3.5 Timer Status Register (TSR)............................................................................. 331 10.3.6 Timer Counter (TCNT)..................................................................................... 335 10.3.7 Timer General Register (TGR) ......................................................................... 335 10.3.8 Timer Start Register (TSTR) ............................................................................ 336 10.3.9 Timer Synchronous Register (TSYR)............................................................... 337 Operation .......................................................................................................................... 338 10.4.1 Basic Functions................................................................................................. 338 10.4.2 Synchronous Operation..................................................................................... 344 10.4.3 Buffer Operation............................................................................................... 346 10.4.4 Cascaded Operation .......................................................................................... 349 10.4 Rev. 2.00 Mar. 15, 2006 page xiv of xxxviii 10.4.5 PWM Modes ..................................................................................................... 351 10.4.6 Phase Counting Mode ....................................................................................... 356 10.5 Interrupt Sources............................................................................................................... 362 10.6 DTC Activation................................................................................................................. 365 10.7 DMAC Activation............................................................................................................. 365 10.8 A/D Converter Activation................................................................................................. 365 10.9 Operation Timing.............................................................................................................. 366 10.9.1 Input/Output Timing ......................................................................................... 366 10.9.2 Interrupt Signal Timing..................................................................................... 370 10.10 Usage Notes ...................................................................................................................... 373 10.10.1 Module Stop Mode Setting ............................................................................... 373 10.10.2 Input Clock Restrictions ................................................................................... 373 10.10.3 Caution on Cycle Setting .................................................................................. 374 10.10.4 Conflict between TCNT Write and Clear Operations....................................... 374 10.10.5 Conflict between TCNT Write and Increment Operations ............................... 375 10.10.6 Conflict between TGR Write and Compare Match........................................... 375 10.10.7 Conflict between Buffer Register Write and Compare Match .......................... 376 10.10.8 Conflict between TGR Read and Input Capture ............................................... 376 10.10.9 Conflict between TGR Write and Input Capture .............................................. 377 10.10.10 Conflict between Buffer Register Write and Input Capture.............................. 377 10.10.11 Conflict between Overflow/Underflow and Counter Clearing ......................... 378 10.10.12 Conflict between TCNT Write and Overflow/Underflow ................................ 379 10.10.13 Multiplexing of I/O Pins ................................................................................... 379 10.10.14 Interrupts and Module Stop Mode .................................................................... 379 Section 11 Programmable Pulse Generator (PPG) ............................................381 11.1 11.2 11.3 Features............................................................................................................................. 381 Input/Output Pins.............................................................................................................. 382 Register Descriptions........................................................................................................ 382 11.3.1 Next Data Enable Registers H, L (NDERH, NDERL) ..................................... 383 11.3.2 Output Data Registers H, L (PODRH, PODRL)............................................... 384 11.3.3 Next Data Registers H, L (NDRH, NDRL) ...................................................... 386 11.3.4 PPG Output Control Register (PCR) ................................................................ 389 11.3.5 PPG Output Mode Register (PMR) .................................................................. 390 Operation .......................................................................................................................... 391 11.4.1 Output Timing................................................................................................... 392 11.4.2 Sample Setup Procedure for Normal Pulse Output........................................... 393 11.4.3 Example of Normal Pulse Output (Example of 5-Phase Pulse Output)............ 394 11.4.4 Non-Overlapping Pulse Output......................................................................... 395 11.4.5 Sample Setup Procedure for Non-Overlapping Pulse Output ........................... 397 11.4.6 Example of Non-Overlapping Pulse Output (Example of 4-Phase Complementary Non-Overlapping Pulse Output) .......... 398 11.4.7 Inverted Pulse Output ....................................................................................... 400 Rev. 2.00 Mar. 15, 2006 page xv of xxxviii 11.4 11.5 11.4.8 Pulse Output Triggered by Input Capture ......................................................... 401 Usage Notes ...................................................................................................................... 402 11.5.1 Module Stop Mode Setting ............................................................................... 402 11.5.2 Operation of Pulse Output Pins......................................................................... 402 Section 12 Watchdog Timer (WDT) ................................................................. 403 12.1 12.2 Features............................................................................................................................. 403 Register Descriptions........................................................................................................ 404 12.2.1 Timer Counter (TCNT)..................................................................................... 404 12.2.2 Timer Control/Status Register (TCSR)............................................................. 404 12.2.3 Reset Control/Status Register (RSTCSR)......................................................... 406 Operation .......................................................................................................................... 408 12.3.1 Watchdog Timer Mode..................................................................................... 408 12.3.2 Interval Timer Mode......................................................................................... 409 Interrupt Source ................................................................................................................ 409 Usage Notes ...................................................................................................................... 410 12.5.1 Notes on Register Access ................................................................................. 410 12.5.2 Conflict between Timer Counter (TCNT) Write and Increment....................... 411 12.5.3 Changing Values of Bits CKS2 to CKS0.......................................................... 411 12.5.4 Switching between Watchdog Timer Mode and Interval Timer Mode............. 411 12.5.5 Transition to Watchdog Timer Mode or Software Standby Mode.................... 412 12.3 12.4 12.5 Section 13 Serial Communication Interface (SCI)............................................ 413 13.1 13.2 13.3 Features............................................................................................................................. 413 Input/Output Pins.............................................................................................................. 415 Register Descriptions........................................................................................................ 415 13.3.1 Receive Shift Register (RSR) ........................................................................... 416 13.3.2 Receive Data Register (RDR)........................................................................... 416 13.3.3 Transmit Data Register (TDR).......................................................................... 417 13.3.4 Transmit Shift Register (TSR) .......................................................................... 417 13.3.5 Serial Mode Register (SMR) ............................................................................ 417 13.3.6 Serial Control Register (SCR) .......................................................................... 420 13.3.7 Serial Status Register (SSR) ............................................................................. 424 13.3.8 Smart Card Mode Register (SCMR)................................................................. 431 13.3.9 Bit Rate Register (BRR) ................................................................................... 432 Operation in Asynchronous Mode .................................................................................... 439 13.4.1 Data Transfer Format........................................................................................ 440 13.4.2 Receive Data Sampling Timing and Reception Margin in Asynchronous Mode..................................................................................... 441 13.4.3 Clock................................................................................................................. 442 13.4.4 SCI Initialization (Asynchronous Mode).......................................................... 443 13.4.5 Serial Data Transmission (Asynchronous Mode) ............................................. 444 13.4.6 Serial Data Reception (Asynchronous Mode) .................................................. 445 13.4 Rev. 2.00 Mar. 15, 2006 page xvi of xxxviii 13.5 13.6 13.7 13.8 13.9 Multiprocessor Communication Function......................................................................... 449 13.5.1 Multiprocessor Serial Data Transmission ......................................................... 451 13.5.2 Multiprocessor Serial Data Reception .............................................................. 452 Operation in Clocked Synchronous Mode ........................................................................ 455 13.6.1 Clock................................................................................................................. 455 13.6.2 SCI Initialization (Clocked Synchronous Mode) .............................................. 456 13.6.3 Serial Data Transmission (Clocked Synchronous Mode) ................................. 457 13.6.4 Serial Data Reception (Clocked Synchronous Mode)....................................... 459 13.6.5 Simultaneous Serial Data Transmission and Reception (Clocked Synchronous Mode) .......................................................................... 461 Operation in Smart Card Interface Mode.......................................................................... 463 13.7.1 Sample Connection ........................................................................................... 463 13.7.2 Data Format (Except in Block Transfer Mode) ................................................ 464 13.7.3 Block Transfer Mode ........................................................................................ 465 13.7.4 Receive Data Sampling Timing and Reception Margin.................................... 466 13.7.5 Initialization ...................................................................................................... 467 13.7.6 Data Transmission (Except in Block Transfer Mode) ...................................... 468 13.7.7 Serial Data Reception (Except in Block Transfer Mode).................................. 471 13.7.8 Clock Output Control........................................................................................ 472 Interrupt Sources............................................................................................................... 474 13.8.1 Interrupts in Normal Serial Communication Interface Mode ........................... 474 13.8.2 Interrupts in Smart Card Interface Mode .......................................................... 475 Usage Notes ...................................................................................................................... 476 13.9.1 Module Stop Mode Setting ............................................................................... 476 13.9.2 Break Detection and Processing ....................................................................... 476 13.9.3 Mark State and Break Detection ....................................................................... 476 13.9.4 Receive Error Flags and Transmit Operations (Clocked Synchronous Mode Only) ................................................................. 476 13.9.5 Relation between Writing to TDR and TDRE Flag .......................................... 477 13.9.6 Restrictions on Using DTC or DMAC.............................................................. 477 13.9.7 SCI Operations during Mode Transitions ......................................................... 478 Section 14 Synchronous Serial Communication Unit (SSU) ............................481 14.1 14.2 14.3 Features............................................................................................................................. 481 Input/Output Pins.............................................................................................................. 483 Register Descriptions........................................................................................................ 484 14.3.1 SS Control Register H (SSCRH) ...................................................................... 486 14.3.2 SS Control Register L (SSCRL) ....................................................................... 488 14.3.3 SS Mode Register (SSMR) ............................................................................... 489 14.3.4 SS Enable Register (SSER) .............................................................................. 490 14.3.5 SS Status Register (SSSR) ................................................................................ 491 14.3.6 SS Control Register 2 (SSCR2) ........................................................................ 495 14.3.7 SS Transmit Data Registers 0 to 3 (SSTDR0 to SSTDR3)............................... 496 Rev. 2.00 Mar. 15, 2006 page xvii of xxxviii 14.4 14.5 14.6 14.3.8 SS Receive Data Registers 0 to 3 (SSRDR0 to SSRDR3)................................ 498 14.3.9 SS Shift Register (SSTRSR)............................................................................. 499 Operation .......................................................................................................................... 500 14.4.1 Transfer Clock .................................................................................................. 500 14.4.2 Relationship of Clock Phase, Polarity, and Data .............................................. 500 14.4.3 Relationship between Data Input/Output Pins and Shift Register .................... 501 14.4.4 Communication Modes and Pin Functions ....................................................... 502 14.4.5 SSU Mode......................................................................................................... 504 14.4.6 SCS Pin Control and Conflict Error.................................................................. 512 14.4.7 Clock Synchronous Communication Mode ...................................................... 513 Interrupt Requests............................................................................................................. 519 Usage Note ....................................................................................................................... 520 14.6.1 Setting of Module Stop Mode........................................................................... 520 14.6.2 Note on Clearing Module Stop Mode ............................................................... 520 Section 15 A/D Converter ................................................................................. 521 15.1 15.2 15.3 Features............................................................................................................................. 521 Input/Output Pins.............................................................................................................. 524 Register Descriptions........................................................................................................ 525 15.3.1 A/D Data Registers A to H (ADDRA to ADDRH) .......................................... 526 15.3.2 A/D Control/Status Register (ADCSR) ............................................................ 527 15.3.3 A/D Control Register (ADCR) ......................................................................... 529 15.3.4 Analog Port Pull-Down Control Register (APPDCR) ...................................... 530 Operation .......................................................................................................................... 531 15.4.1 Single Mode...................................................................................................... 531 15.4.2 Scan Mode ........................................................................................................ 533 15.4.3 Input Sampling and A/D Conversion Time ...................................................... 535 15.4.4 External Trigger Input Timing.......................................................................... 537 Interrupt Source ................................................................................................................ 537 A/D Conversion Accuracy Definitions ............................................................................. 538 Analog Port Pull-Down Function ..................................................................................... 540 Usage Notes ...................................................................................................................... 541 15.8.1 Module Stop Mode Setting ............................................................................... 541 15.8.2 Permissible Signal Source Impedance .............................................................. 541 15.8.3 Influences on Absolute Accuracy ..................................................................... 542 15.8.4 Setting Range of Analog Power Supply and Other Pins................................... 542 15.8.5 Notes on Board Design ..................................................................................... 542 15.8.6 Notes on Noise Countermeasures ..................................................................... 542 15.8.7 A/D Input Hold Function in Software Standby Mode ...................................... 544 15.4 15.5 15.6 15.7 15.8 Section 16 RAM ................................................................................................ 545 Rev. 2.00 Mar. 15, 2006 page xviii of xxxviii Section 17 Flash Memory (0.18-m F-ZTAT Version) ....................................547 17.1 17.2 17.3 17.4 17.5 17.6 17.7 Features............................................................................................................................. 547 Mode Transition Diagram................................................................................................. 549 Memory MAT Configuration ........................................................................................... 551 Block Structure ................................................................................................................. 552 Programming/Erasing Interface ........................................................................................ 553 Input/Output Pins.............................................................................................................. 555 Register Descriptions........................................................................................................ 555 17.7.1 Programming/Erasing Interface Registers ........................................................ 556 17.7.2 Programming/Erasing Interface Parameters ..................................................... 563 17.7.3 RAM Emulation Register (RAMER)................................................................ 575 On-Board Programming Mode ......................................................................................... 576 17.8.1 Boot Mode ........................................................................................................ 576 17.8.2 User Program Mode.......................................................................................... 580 17.8.3 User Boot Mode................................................................................................ 590 17.8.4 On-Chip Program and Storable Area for Program Data ................................... 594 Protection.......................................................................................................................... 600 17.9.1 Hardware Protection ......................................................................................... 600 17.9.2 Software Protection........................................................................................... 601 17.9.3 Error Protection................................................................................................. 601 Flash Memory Emulation Using RAM............................................................................. 603 Switching between User MAT and User Boot MAT........................................................ 606 Programmer Mode ............................................................................................................ 607 Standard Serial Communication Interface Specifications for Boot Mode ........................ 607 Usage Notes ...................................................................................................................... 636 17.8 17.9 17.10 17.11 17.12 17.13 17.14 Section 18 Clock Pulse Generator .....................................................................639 18.1 18.2 Register Description ......................................................................................................... 640 18.1.1 System Clock Control Register (SCKCR) ........................................................ 640 Oscillator........................................................................................................................... 643 18.2.1 Connecting Crystal Resonator .......................................................................... 643 18.2.2 External Clock Input ......................................................................................... 644 PLL Circuit ....................................................................................................................... 645 Frequency Divider ............................................................................................................ 645 Usage Notes ...................................................................................................................... 645 18.5.1 Notes on Clock Pulse Generator ....................................................................... 645 18.5.2 Notes on Resonator ........................................................................................... 646 18.5.3 Notes on Board Design ..................................................................................... 646 18.5.4 Notes on Input Clock Frequency ...................................................................... 647 18.3 18.4 18.5 Section 19 Power-Down Modes ........................................................................649 19.1 Features............................................................................................................................. 649 Rev. 2.00 Mar. 15, 2006 page xix of xxxviii 19.2 19.3 19.4 19.5 19.6 19.7 19.8 19.9 Register Descriptions........................................................................................................ 651 19.2.1 Standby Control Register (SBYCR) ................................................................. 651 19.2.2 Module Stop Control Registers A and B (MSTPCRA and MSTPCRB) .......... 653 19.2.3 Module Stop Control Register C (MSTPCRC)................................................. 656 Multi-Clock Function ....................................................................................................... 657 Module Stop Mode ........................................................................................................... 657 Sleep Mode ....................................................................................................................... 658 19.5.1 Transition to Sleep Mode.................................................................................. 658 19.5.2 Clearing Sleep Mode ........................................................................................ 658 All-Module-Clock-Stop Mode.......................................................................................... 658 Software Standby Mode.................................................................................................... 659 19.7.1 Transition to Software Standby Mode .............................................................. 659 19.7.2 Clearing Software Standby Mode..................................................................... 659 19.7.3 Setting Oscillation Settling Time after Clearing Software Standby Mode ....... 660 19.7.4 Software Standby Mode Application Example................................................. 661 B Clock Output Control.................................................................................................. 662 Usage Notes ...................................................................................................................... 663 19.9.1 I/O Port Status................................................................................................... 663 19.9.2 Current Consumption during Oscillation Settling Standby Period ................... 663 19.9.3 DTC and DMAC Module Stop ......................................................................... 663 19.9.4 On-Chip Peripheral Module Interrupts ............................................................. 663 19.9.5 Writing to MSTPCRA, MSTPCRB, and MSTPCRC....................................... 663 Section 20 List of Registers............................................................................... 665 20.1 20.2 20.3 Register Addresses (Address Order)................................................................................. 666 Register Bits ..................................................................................................................... 678 Register States in Each Operating Mode .......................................................................... 695 Section 21 Electrical Characteristics ................................................................. 705 21.1 21.2 21.3 Absolute Maximum Ratings ............................................................................................. 705 DC Characteristics ............................................................................................................ 706 AC Characteristics ............................................................................................................ 708 21.3.1 Clock Timing .................................................................................................... 709 21.3.2 Control Signal Timing ...................................................................................... 711 21.3.3 Timing of On-Chip Peripheral Modules ........................................................... 712 21.3.4 A/D Conversion Characteristics ....................................................................... 719 21.3.5 Flash Memory Characteristics .......................................................................... 720 Appendix ............................................................................................................. 721 A. B. C. Port States in Each Pin State.............................................................................................. 721 Product Lineup................................................................................................................... 722 Package Dimensions .......................................................................................................... 723 Rev. 2.00 Mar. 15, 2006 page xx of xxxviii Main Revisions and Additions in this Edition .....................................................725 Index ....................................................................................................................749 Rev. 2.00 Mar. 15, 2006 page xxi of xxxviii Rev. 2.00 Mar. 15, 2006 page xxii of xxxviii Figures Section 1 Overview Figure 1.1 Block Diagram of H8SX/1582 ...................................................................................... 2 Figure 1.2 Pin Assignments of H8SX/1582.................................................................................... 3 Section 2 CPU Figure 2.1 CPU Operating Modes ................................................................................................ 19 Figure 2.2 Exception Vector Table (Normal Mode)..................................................................... 20 Figure 2.3 Stack Structure (Normal Mode) .................................................................................. 20 Figure 2.4 Exception Vector Table (Middle and Advanced Modes) ............................................ 22 Figure 2.5 Stack Structure (Middle and Advanced Modes).......................................................... 23 Figure 2.6 Exception Vector Table (Maximum Modes)............................................................... 24 Figure 2.7 Stack Structure (Maximum Mode) .............................................................................. 24 Figure 2.8 Memory Map............................................................................................................... 25 Figure 2.9 CPU Registers ............................................................................................................. 26 Figure 2.10 Usage of General Registers ....................................................................................... 27 Figure 2.11 Stack .......................................................................................................................... 28 Figure 2.12 General Register Data Formats ................................................................................. 32 Figure 2.13 Memory Data Formats............................................................................................... 33 Figure 2.14 Instruction Formats.................................................................................................... 51 Figure 2.15 Branch Address Specification in Memory Indirect Mode ......................................... 58 Figure 2.16 State Transitions ........................................................................................................ 62 Section 3 MCU Operating Modes Figure 3.1 Address Map ............................................................................................................... 68 Section 4 Figure 4.1 Figure 4.2 Figure 4.3 Section 5 Figure 5.1 Figure 5.2 Figure 5.3 Figure 5.4 Figure 5.5 Figure 5.6 Figure 5.7 Exception Handling Reset Sequence (On-Chip ROM Enabled Advanced Mode)....................................... 73 Stack Status after Exception Handling ........................................................................ 80 Operation when SP Value Is Odd................................................................................ 81 Interrupt Controller Block Diagram of Interrupt Controller........................................................................ 84 Block Diagram of Interrupts IRQn............................................................................ 101 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 0... 110 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 2... 112 Interrupt Exception Handling .................................................................................... 113 Block Diagram of DMAC and Interrupt Controller .................................................. 116 Conflict between Interrupt Generation and Disabling............................................... 121 Section 6 Bus Controller (BSC) Figure 6.1 Block Diagram of Bus Controller.............................................................................. 125 Figure 6.2 Internal Bus Configuration ........................................................................................ 127 Rev. 2.00 Mar. 15, 2006 Page xxiii of xxxviii Figure 6.3 Example of Timing when Write Data Buffer Function is Used ................................ 130 Section 7 DMA Controller (DMAC) Figure 7.1 Block Diagram of DMAC ......................................................................................... 137 Figure 7.2 Example of Signal Timing in Dual Address Mode ................................................... 162 Figure 7.3 Operations in Dual Address Mode ............................................................................ 162 Figure 7.4 Data Flow in Single Address Mode........................................................................... 163 Figure 7.5 Example of Signal Timing in Single Address Mode ................................................. 164 Figure 7.6 Operations in Single Address Mode.......................................................................... 164 Figure 7.7 Example of Signal Timing in Normal Transfer Mode............................................... 165 Figure 7.8 Operations in Normal Transfer Mode ....................................................................... 165 Figure 7.9 Operations in Repeat Transfer Mode ........................................................................ 166 Figure 7.10 Operations in Block Transfer Mode ........................................................................ 167 Figure 7.11 Operation in Single Address Mode in Block Transfer Mode (Block Area Specified) ........................................................................................... 168 Figure 7.12 Operation in Dual Address Mode in Block Transfer Mode (Block Area Not Specified) .................................................................................... 168 Figure 7.13 Example of Timing in Cycle Stealing Mode ........................................................... 172 Figure 7.14 Example of Timing in Burst Mode.......................................................................... 172 Figure 7.15 Example of Extended Repeat Area Operation......................................................... 173 Figure 7.16 Example of Extended Repeat Area Function in Block Transfer Mode ................... 174 Figure 7.17 Address Update Method.......................................................................................... 175 Figure 7.18 Operation of Offset Addition .................................................................................. 176 Figure 7.19 XY Conversion Operation Using Offset Addition in Repeat Transfer Mode.......... 177 Figure 7.20 XY Conversion Flowchart Using Offset Addition in Repeat Transfer Mode ......... 178 Figure 7.21 Procedure for Changing Register Setting For Channel being Transferred .............. 182 Figure 7.22 Example of Timing for Channel Priority................................................................. 185 Figure 7.23 Example of Bus Timing of DMA Transfer ............................................................. 185 Figure 7.24 Example of Transfer in Normal Transfer Mode by Cycle Stealing......................... 186 Figure 7.25 Example of Transfer in Normal Transfer Mode by Cycle Stealing (Transfer Source DSAR = Odd Address and Source Address Increment).............. 187 Figure 7.26 Example of Transfer in Normal Transfer Mode by Cycle Stealing (Transfer Destination DDAR = Odd Address and Destination Address Decrement) ............................................................................................................. 187 Figure 7.27 Example of Transfer in Normal Transfer Mode by Burst Access ........................... 188 Figure 7.28 Example of Transfer in Block Transfer Mode......................................................... 189 Figure 7.29 Example of Transfer in Normal Transfer Mode Activated by DREQ Falling Edge ........................................................................................... 190 Figure 7.30 Example of Transfer in Normal Transfer Mode Activated by DREQ Low Level .............................................................................................. 191 Figure 7.31 Example of Transfer in Block Transfer Mode Activated by DREQ Low Level .............................................................................................. 192 Rev. 2.00 Mar. 15, 2006 Page xxiv of xxxviii Figure 7.32 Example of Transfer in Normal Transfer Mode Activated by DREQ Low Level with NRD = 1....................................................................... 193 Figure 7.33 Example of Transfer in Single Address Mode (Byte Read) .................................... 194 Figure 7.34 Example of Transfer in Single Address Mode (Byte Write) ................................... 195 Figure 7.35 Example of Transfer in Single Address Mode Activated by DREQ Falling Edge ........................................................................................... 196 Figure 7.36 Example of Transfer in Single Address Mode Activated by DREQ Low Level .............................................................................................. 197 Figure 7.37 Example of Transfer in Single Address Mode Activated by DREQ Low Level with NRD = 1....................................................................... 198 Figure 7.38 Interrupt and Interrupt Sources................................................................................ 205 Figure 7.39 Procedure Example of Resuming Transfer by Clearing Interrupt Source ............... 205 Section 8 Figure 8.1 Figure 8.2 Figure 8.3 Figure 8.4 Figure 8.5 Figure 8.6 Figure 8.7 Figure 8.8 Data Transfer Controller (DTC) Block Diagram of DTC ............................................................................................. 208 Transfer Information on Data Area ........................................................................... 218 Correspondence between DTC Vector Address and Transfer Information............... 219 Flowchart of DTC Operation..................................................................................... 224 Bus Cycle Division Example..................................................................................... 226 Transfer Information Read Skip Timing ................................................................... 227 Memory Map in Normal Transfer Mode................................................................... 229 Memory Map in Repeat Transfer Mode (When Transfer Source is Specified as Repeat Area) ................................................ 230 Figure 8.9 Memory Map in Block Transfer Mode (When Transfer Destination is Specified as Block Area) .......................................... 231 Figure 8.10 Operation of Chain Transfer.................................................................................... 232 Figure 8.11 DTC Operation Timing (Example of Short Address Mode in Normal Transfer Mode or Repeat Transfer Mode) .............................................. 233 Figure 8.12 DTC Operation Timing (Example of Short Address Mode in Block Transfer Mode with Block Size of 2) ........................................................ 233 Figure 8.13 DTC Operation Timing (Example of Short Address Mode in Chain Transfer) ...... 234 Figure 8.14 DTC Operation Timing (Example of Full Address Mode in Normal Transfer Mode or Repeat Transfer Mode) .............................................. 234 Figure 8.15 Using DTC with Interrupt Activation...................................................................... 237 Figure 8.16 Chain Transfer when Counter = 0 ........................................................................... 241 Section 9 I/O Ports Figure 9.1 Port Block Diagram................................................................................................... 250 Section 10 Figure 10.1 Figure 10.2 Figure 10.3 Figure 10.4 16-Bit Timer Pulse Unit (TPU) Block Diagram of TPU (Unit 0) .............................................................................. 296 Block Diagram of TPU (Unit 1) .............................................................................. 297 Example of Counter Operation Setting Procedure .................................................. 338 Free-Running Counter Operation ............................................................................ 339 Rev. 2.00 Mar. 15, 2006 Page xxv of xxxviii Figure 10.5 Periodic Counter Operation..................................................................................... 340 Figure 10.6 Example of Setting Procedure for Waveform Output by Compare Match.............. 340 Figure 10.7 Example of 0-Output/1-Output Operation............................................................... 341 Figure 10.8 Example of Toggle Output Operation ..................................................................... 341 Figure 10.9 Example of Setting Procedure for Input Capture Operation.................................... 342 Figure 10.10 Example of Input Capture Operation .................................................................... 343 Figure 10.11 Example of Synchronous Operation Setting Procedure ........................................ 344 Figure 10.12 Example of Synchronous Operation...................................................................... 345 Figure 10.13 Compare Match Buffer Operation......................................................................... 346 Figure 10.14 Input Capture Buffer Operation............................................................................. 347 Figure 10.15 Example of Buffer Operation Setting Procedure................................................... 347 Figure 10.16 Example of Buffer Operation (1) .......................................................................... 348 Figure 10.17 Example of Buffer Operation (2) .......................................................................... 349 Figure 10.18 Example of Cascaded Operation Setting Procedure.............................................. 350 Figure 10.19 Example of Cascaded Operation (1)...................................................................... 350 Figure 10.20 Example of Cascaded Operation (2)...................................................................... 351 Figure 10.21 Example of PWM Mode Setting Procedure .......................................................... 353 Figure 10.22 Example of PWM Mode Operation (1) ................................................................. 354 Figure 10.23 Example of PWM Mode Operation (2) ................................................................. 354 Figure 10.24 Example of PWM Mode Operation (3) ................................................................. 355 Figure 10.25 Example of Phase Counting Mode Setting Procedure........................................... 356 Figure 10.26 Example of Phase Counting Mode 1 Operation .................................................... 357 Figure 10.27 Example of Phase Counting Mode 2 Operation .................................................... 358 Figure 10.28 Example of Phase Counting Mode 3 Operation .................................................... 359 Figure 10.29 Example of Phase Counting Mode 4 Operation .................................................... 360 Figure 10.30 Phase Counting Mode Application Example......................................................... 361 Figure 10.31 Count Timing in Internal Clock Operation............................................................ 366 Figure 10.32 Count Timing in External Clock Operation .......................................................... 366 Figure 10.33 Output Compare Output Timing ........................................................................... 367 Figure 10.34 Input Capture Input Signal Timing........................................................................ 367 Figure 10.35 Counter Clear Timing (Compare Match) .............................................................. 368 Figure 10.36 Counter Clear Timing (Input Capture) .................................................................. 368 Figure 10.37 Buffer Operation Timing (Compare Match) ......................................................... 369 Figure 10.38 Buffer Operation Timing (Input Capture) ............................................................. 369 Figure 10.39 TGI Interrupt Timing (Compare Match) ............................................................... 370 Figure 10.40 TGI Interrupt Timing (Input Capture) ................................................................... 370 Figure 10.41 TCIV Interrupt Setting Timing.............................................................................. 371 Figure 10.42 TCIU Interrupt Setting Timing.............................................................................. 371 Figure 10.43 Timing for Status Flag Clearing by CPU .............................................................. 372 Figure 10.44 Timing for Status Flag Clearing by DMAC Activation (1)................................... 372 Figure 10.45 Timing for Status Flag Clearing by DMAC Activation (2)................................... 373 Figure 10.46 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode ................ 373 Figure 10.47 Conflict between TCNT Write and Clear Operations ........................................... 374 Rev. 2.00 Mar. 15, 2006 Page xxvi of xxxviii Figure 10.48 Figure 10.49 Figure 10.50 Figure 10.51 Figure 10.52 Figure 10.53 Figure 10.54 Figure 10.55 Conflict between TCNT Write and Increment Operations .................................... 375 Conflict between TGR Write and Compare Match ............................................... 375 Conflict between Buffer Register Write and Compare Match............................... 376 Conflict between TGR Read and Input Capture.................................................... 376 Conflict between TGR Write and Input Capture................................................... 377 Conflict between Buffer Register Write and Input Capture .................................. 378 Conflict between Overflow and Counter Clearing ................................................ 378 Conflict between TCNT Write and Overflow ....................................................... 379 Section 11 Programmable Pulse Generator (PPG) Figure 11.1 Block Diagram of PPG............................................................................................ 381 Figure 11.2 Schematic Diagram of PPG..................................................................................... 391 Figure 11.3 Timing of Transfer and Output of NDR Contents (Example) ................................. 392 Figure 11.4 Setup Procedure for Normal Pulse Output (Example)............................................. 393 Figure 11.5 Normal Pulse Output Example (5-Phase Pulse Output) .......................................... 394 Figure 11.6 Non-Overlapping Pulse Output ............................................................................... 395 Figure 11.7 Non-Overlapping Operation and NDR Write Timing ............................................. 396 Figure 11.8 Setup Procedure for Non-Overlapping Pulse Output (Example)............................. 397 Figure 11.9 Non-Overlapping Pulse Output Example (4-Phase Complementary) ..................... 398 Figure 11.10 Inverted Pulse Output (Example) .......................................................................... 400 Figure 11.11 Pulse Output Triggered by Input Capture (Example)............................................ 401 Section 12 Figure 12.1 Figure 12.2 Figure 12.3 Figure 12.4 Figure 12.5 Watchdog Timer (WDT) Block Diagram of WDT .......................................................................................... 403 Operation in Watchdog Timer Mode....................................................................... 408 Operation in Interval Timer Mode........................................................................... 409 Writing to TCNT, TCSR, and RSTCSR.................................................................. 410 Conflict between TCNT Write and Increment ........................................................ 411 Section 13 Serial Communication Interface (SCI) Figure 13.1 Block Diagram of SCI............................................................................................. 414 Figure 13.2 Data Format in Asynchronous Communication (Example with 8-Bit Data, Parity, Two Stop Bits) .................................................. 439 Figure 13.3 Receive Data Sampling Timing in Asynchronous Mode ........................................ 441 Figure 13.4 Phase Relation between Output Clock and Transmit Data (Asynchronous Mode) ............................................................................................. 442 Figure 13.5 Sample SCI Initialization Flowchart ....................................................................... 443 Figure 13.6 Example of Operation for Transmission in Asynchronous Mode (Example with 8-Bit Data, Parity, One Stop Bit).................................................... 444 Figure 13.7 Sample Serial Transmission Flowchart ................................................................... 445 Figure 13.8 Example of SCI Operation for Reception (Example with 8-Bit Data, Parity, One Stop Bit)..................................................... 446 Figure 13.9 Sample Serial Reception Flowchart (1)................................................................... 447 Figure 13.9 Sample Serial Reception Flowchart (2)................................................................... 448 Rev. 2.00 Mar. 15, 2006 Page xxvii of xxxviii Figure 13.10 Example of Communication Using Multiprocessor Format (Transmission of Data H'AA to Receiving Station A).......................................... 450 Figure 13.11 Sample Multiprocessor Serial Transmission Flowchart ........................................ 451 Figure 13.12 Example of SCI Operation for Reception (Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit) .............................. 452 Figure 13.13 Sample Multiprocessor Serial Reception Flowchart (1)........................................ 453 Figure 13.13 Sample Multiprocessor Serial Reception Flowchart (2)........................................ 454 Figure 13.14 Data Format in Clocked Synchronous Communication (LSB-First)..................... 455 Figure 13.15 Sample SCI Initialization Flowchart ..................................................................... 456 Figure 13.16 Example of Operation for Transmission in Clocked Synchronous Mode ............. 458 Figure 13.17 Sample Serial Transmission Flowchart ................................................................. 458 Figure 13.18 Example of Operation for Reception in Clocked Synchronous Mode .................. 459 Figure 13.19 Sample Serial Reception Flowchart ...................................................................... 460 Figure 13.20 Sample Flowchart of Simultaneous Serial Transmission and Reception .............. 462 Figure 13.21 Pin Connection for Smart Card Interface .............................................................. 463 Figure 13.22 Data Formats in Normal Smart Card Interface Mode ........................................... 464 Figure 13.23 Direct Convention (SDIR = SINV = O/E = 0) ...................................................... 464 Figure 13.24 Inverse Convention (SDIR = SINV = O/E = 1) .................................................... 465 Figure 13.25 Receive Data Sampling Timing in Smart Card Interface Mode (When Clock Frequency is 372 Times the Bit Rate) ............................................ 466 Figure 13.26 Data Re-Transfer Operation in SCI Transmission Mode ...................................... 469 Figure 13.27 TEND Flag Set Timing during Transmission........................................................ 469 Figure 13.28 Sample Transmission Flowchart ........................................................................... 470 Figure 13.29 Data Re-Transfer Operation in SCI Reception Mode............................................ 471 Figure 13.30 Sample Reception Flowchart................................................................................. 472 Figure 13.31 Clock Output Fixing Timing ................................................................................. 472 Figure 13.32 Clock Stop and Restart Procedure......................................................................... 473 Figure 13.33 Sample Transmission using DTC or DMAC in Clocked Synchronous Mode ...... 477 Figure 13.34 Sample Flowchart for Mode Transition during Transmission............................... 479 Figure 13.35 Port Pin States during Mode Transition (Internal Clock, Asynchronous Transmission) ...................................................... 479 Figure 13.36 Port Pin States during Mode Transition (Internal Clock, Clocked Synchronous Transmission) .......................................... 480 Figure 13.37 Sample Flowchart for Mode Transition during Reception .................................... 480 Section 14 Figure 14.1 Figure 14.2 Figure 14.3 Figure 14.4 Figure 14.5 Figure 14.6 Figure 14.7 Synchronous Serial Communication Unit (SSU) Block Diagram of SSU............................................................................................ 482 Relationship of Clock Phase, Polarity, and Data..................................................... 500 Relationship between Data Input/Output Pins and the Shift Register ..................... 501 Example of Initial Settings in SSU Mode ............................................................... 504 Example of Transmission Operation (SSU Mode).................................................. 506 Flowchart Example of Data Transmission (SSU Mode) ......................................... 507 Example of Reception Operation (SSU Mode) ....................................................... 509 Rev. 2.00 Mar. 15, 2006 Page xxviii of xxxviii Figure 14.8 Flowchart Example of Data Reception (SSU Mode)............................................... 510 Figure 14.9 Flowchart Example of Simultaneous Transmission/Reception (SSU Mode) .......... 511 Figure 14.10 Conflict Error Detection Timing (Before Transfer) .............................................. 512 Figure 14.11 Conflict Error Detection Timing (After Transfer End) ......................................... 512 Figure 14.12 Example of Initial Settings in Clock Synchronous Communication Mode ........... 513 Figure 14.13 Example of Transmission Operation (Clock Synchronous Communication Mode)........................................................ 514 Figure 14.14 Flowchart Example of Transmission Operation (Clock Synchronous Communication Mode)........................................................ 515 Figure 14.15 Example of Reception Operation (Clock Synchronous Communication Mode)... 516 Figure 14.16 Flowchart Example of Data Reception (Clock Synchronous Communication Mode)......................................................... 517 Figure 14.17 Flowchart Example of Simultaneous Transmission/Reception (Clock Synchronous Communication Mode)........................................................ 518 Section 15 Figure 15.1 Figure 15.2 Figure 15.3 Figure 15.4 A/D Converter Block Diagram of A/D Converter (Unit 0/AD_0) ................................................... 522 Block Diagram of A/D Converter (Unit 1/AD_1) ................................................... 523 Example of A/D Converter Operation (Single Mode, Channel 1 Selected) ............ 532 Example of A/D Conversion (Scan Mode, Three Channels (AN0 to AN2) Selected) .......................................... 534 Figure 15.5 A/D Conversion Timing .......................................................................................... 535 Figure 15.6 External Trigger Input Timing ................................................................................ 537 Figure 15.7 A/D Conversion Accuracy Definitions.................................................................... 539 Figure 15.8 A/D Conversion Accuracy Definitions.................................................................... 539 Figure 15.9 Diagram of Analog Port Pull-Down Function......................................................... 540 Figure 15.10 Example of Analog Input Circuit .......................................................................... 541 Figure 15.11 Example of Analog Input Protection Circuit ......................................................... 543 Figure 15.12 Analog Input Pin Equivalent Circuit ..................................................................... 543 Section 17 Flash Memory (0.18-mm F-ZTAT Version) Figure 17.1 Block Diagram of Flash Memory............................................................................ 548 Figure 17.2 Mode Transition of Flash Memory.......................................................................... 549 Figure 17.3 Memory MAT Configuration .................................................................................. 551 Figure 17.4 Block Structure of User MAT ................................................................................. 552 Figure 17.5 Procedure for Creating Procedure Program............................................................. 553 Figure 17.6 System Configuration in Boot Mode....................................................................... 576 Figure 17.7 Automatic-Bit-Rate Adjustment Operation............................................................. 577 Figure 17.8 Boot Mode State Transition Diagram...................................................................... 578 Figure 17.9 Programming/Erasing Flow..................................................................................... 580 Figure 17.10 RAM Map when Programming/Erasing is Executed ............................................ 581 Figure 17.11 Programming Procedure in User Program Mode .................................................. 582 Figure 17.12 Erasing Procedure in User Program Mode ............................................................ 587 Rev. 2.00 Mar. 15, 2006 Page xxix of xxxviii Figure 17.13 Repeating Procedure of Erasing, Programming, and RAM Emulation in User Program Mode ....................................................... 589 Figure 17.14 Procedure for Programming User MAT in User Boot Mode ................................ 591 Figure 17.15 Procedure for Erasing User MAT in User Boot Mode .......................................... 593 Figure 17.16 Transitions to Error Protection State ..................................................................... 602 Figure 17.17 RAM Emulation Flow ........................................................................................... 603 Figure 17.18 Address Map of Overlaid RAM Area ................................................................... 604 Figure 17.19 Programming Tuned Data ..................................................................................... 605 Figure 17.20 Switching between User MAT and User Boot MAT ............................................ 606 Figure 17.21 Boot Program States.............................................................................................. 608 Figure 17.22 Bit-Rate-Adjustment Sequence ............................................................................. 609 Figure 17.23 Communication Protocol Format .......................................................................... 610 Figure 17.24 New Bit-Rate Selection Sequence......................................................................... 621 Figure 17.25 Programming Sequence......................................................................................... 625 Figure 17.26 Erasure Sequence .................................................................................................. 626 Section 18 Figure 18.1 Figure 18.2 Figure 18.3 Figure 18.4 Figure 18.5 Figure 18.6 Figure 18.7 Clock Pulse Generator Block Diagram of Clock Pulse Generator ............................................................... 639 Connection of Crystal Resonator (Example)........................................................... 643 Crystal Resonator Equivalent Circuit...................................................................... 643 External Clock Input (Examples) ............................................................................ 644 Clock Modification Timing..................................................................................... 646 Note on Board Design for Oscillation Circuit ......................................................... 647 Connection Example of Bypass Capacitor .............................................................. 647 Section 19 Power-Down Modes Figure 19.1 Mode Transitions..................................................................................................... 650 Figure 19.2 Software Standby Mode Application Example ....................................................... 661 Section 21 Electrical Characteristics Figure 21.1 Output Load Circuit ................................................................................................ 708 Figure 21.2 System Bus Clock Timing....................................................................................... 709 Figure 21.3 Oscillation Settling Timing after Software Standby Mode ..................................... 710 Figure 21.4 Oscillation Settling Timing ..................................................................................... 710 Figure 21.5 External Input Clock Timing................................................................................... 710 Figure 21.6 Reset Input Timing.................................................................................................. 711 Figure 21.7 Interrupt Input Timing............................................................................................. 712 Figure 21.8 I/O Port Input/Output Timing.................................................................................. 715 Figure 21.9 Data Input Timing for Realtime Input Port ............................................................. 715 Figure 21.10 TPU Input/Output Timing ..................................................................................... 715 Figure 21.11 TPU Clock Input Timing....................................................................................... 716 Figure 21.12 PPG Output Timing............................................................................................... 716 Figure 21.13 SCK Clock Input/Output Timing .......................................................................... 716 Figure 21.14 SCI Input/Output Timing: Clocked Synchronous Mode ....................................... 716 Rev. 2.00 Mar. 15, 2006 Page xxx of xxxviii Figure 21.15 Figure 21.16 Figure 21.17 Figure 21.18 Figure 21.19 A/D Converter External Trigger Input Timing...................................................... 716 SSU Timing (Master, CPHS = 1) .......................................................................... 717 SSU Timing (Master, CPHS = 0) .......................................................................... 717 SSU Timing (Slave, CPHS = 1) ............................................................................ 718 SSU Timing (Slave, CPHS = 0) ............................................................................ 718 Appendix Figure C.1 Package Dimensions (PLQP0120LA-A) .................................................................. 723 Rev. 2.00 Mar. 15, 2006 Page xxxi of xxxviii Rev. 2.00 Mar. 15, 2006 Page xxxii of xxxviii Tables Section 1 Overview Table 1.1 Pin Configuration in Each Operating Mode.............................................................. 4 Table 1.2 Pin Functions ............................................................................................................ 8 Section 2 CPU Table 2.1 Instruction Classification ........................................................................................ 34 Table 2.2 Combinations of Instructions and Addressing Modes (1)....................................... 36 Table 2.2 Combinations of Instructions and Addressing Modes (2)....................................... 39 Table 2.3 Operation Notation ................................................................................................. 40 Table 2.4 Data Transfer Instructions....................................................................................... 41 Table 2.5 Block Transfer Instructions..................................................................................... 42 Table 2.6 Arithmetic Operation Instructions .......................................................................... 43 Table 2.7 Logic Operation Instructions .................................................................................. 45 Table 2.8 Shift Operation Instructions.................................................................................... 46 Table 2.9 Bit Manipulation Instructions ................................................................................. 47 Table 2.10 Branch Instructions ................................................................................................. 49 Table 2.11 System Control Instructions.................................................................................... 50 Table 2.12 Addressing Modes .................................................................................................. 52 Table 2.13 Absolute Address Access Ranges ........................................................................... 56 Table 2.14 Effective Address Calculation for Transfer and Operation Instructions ................. 59 Table 2.15 Effective Address Calculation for Branch Instructions........................................... 60 Section 3 MCU Operating Modes Table 3.1 MCU Operating Mode Settings .............................................................................. 63 Table 3.2 Settings of Bits MSD3 to MSD0 ............................................................................ 65 Section 4 Exception Handling Table 4.1 Exception Types and Priority.................................................................................. 69 Table 4.2 Exception Handling Vector Table........................................................................... 70 Table 4.3 Calculation Method of Exception Handling Vector Table Address........................ 72 Table 4.4 Status of CCR and EXR after Trace Exception Handling....................................... 74 Table 4.5 Bus Cycle and Address Error.................................................................................. 75 Table 4.6 States of CCR and EXR after Address Error Exception Handling ......................... 76 Table 4.7 Interrupt Sources..................................................................................................... 77 Table 4.8 Status of CCR and EXR after Trap Instruction Exception Handling...................... 78 Table 4.9 Status of CCR and EXR after Illegal Instruction Exception Handling ................... 79 Section 5 Interrupt Controller Table 5.1 Pin Configuration.................................................................................................... 85 Rev. 2.00 Mar. 15, 2006 Page xxxiii of xxxviii Table 5.2 Table 5.3 Table 5.4 Table 5.5 Table 5.6 Table 5.7 Table 5.8 Interrupt Sources, Vector Address Offsets, and Interrupt Priority........................ 102 Interrupt Control Modes ....................................................................................... 109 Interrupt Response Times ..................................................................................... 114 Number of Execution States in Interrupt Handling Routine ................................. 115 Interrupt Source Selection and Clear Control ....................................................... 117 CPU Priority Control ............................................................................................ 119 Example of Priority Control Function Setting and Control State ......................... 120 Section 6 Bus Controller (BSC) Table 6.1 Synchronization Clocks and Their Corresponding Functions............................... 128 Table 6.2 Number of Access Cycles for On-Chip Memory Spaces...................................... 129 Table 6.3 Number of Access Cycles for Registers of On-Chip Peripheral Modules ............ 129 Section 7 DMA Controller (DMAC) Data Access Size, Valid Bits, and Settable Size ................................................... 144 Table 7.1 Table 7.2 Settings and Areas of Extended Repeat Area ....................................................... 159 Table 7.3 Transfer Modes..................................................................................................... 160 Table 7.4 List of On-chip module interrupts to DMAC........................................................ 170 Table 7.5 Priority among DMAC Channels.......................................................................... 184 Table 7.6 Interrupt Sources and Priority............................................................................... 203 Section 8 Data Transfer Controller (DTC) Table 8.1 Interrupt Sources, DTC Vector Addresses, and Corresponding DTCEs .............. 220 Table 8.2 DTC Transfer Modes ............................................................................................ 223 Table 8.3 Chain Transfer Conditions.................................................................................... 225 Table 8.4 Number of Bus Cycle Divisions and Access Size ................................................ 225 Table 8.5 Transfer Information Writeback Skip Condition and Writeback Skipped Registers ......................................................................... 228 Table 8.6 Register Function in Normal Transfer Mode........................................................ 228 Table 8.7 Register Function in Repeat Transfer Mode ......................................................... 230 Table 8.8 Register Function in Block Transfer Mode........................................................... 231 Table 8.9 DTC Execution Status .......................................................................................... 235 Table 8.10 Number of Cycles Required for Each Execution State ......................................... 236 Section 9 I/O Ports Table 9.1 Port Functions....................................................................................................... 243 Table 9.2 Register Configuration in Each Port ..................................................................... 249 Table 9.3 Input Pull-Up MOS State...................................................................................... 253 Table 9.4 Available Output Signals and Settings in Each Port............................................. 280 Section 10 16-Bit Timer Pulse Unit (TPU) Table 10.1 Unit Configuration for Each Product.................................................................... 292 Table 10.2 TPU Functions (Unit 0) ........................................................................................ 292 Rev. 2.00 Mar. 15, 2006 Page xxxiv of xxxviii Table 10.3 Table 10.4 Table 10.5 Table 10.6 Table 10.7 Table 10.8 Table 10.9 Table 10.10 Table 10.11 Table 10.12 Table 10.13 Table 10.14 Table 10.15 Table 10.16 Table 10.17 Table 10.18 Table 10.19 Table 10.20 Table 10.21 Table 10.22 Table 10.23 Table 10.24 Table 10.25 Table 10.26 Table 10.27 Table 10.28 Table 10.29 Table 10.30 Table 10.31 Table 10.32 Table 10.33 Table 10.34 Table 10.35 Table 10.36 Table 10.37 Table 10.38 Table 10.39 TPU Functions (Unit 1) ........................................................................................ 294 Pin Configuration.................................................................................................. 298 CCLR2 to CCLR0 (Channels 0 and 3) ................................................................. 306 CCLR2 to CCLR0 (Channels 1, 2, 4, and 5) ........................................................ 306 Input Clock Edge Selection .................................................................................. 307 TPSC2 to TPSC0 (Channel 0) .............................................................................. 307 TPSC2 to TPSC0 (Channel 1) .............................................................................. 307 TPSC2 to TPSC0 (Channel 2) .......................................................................... 308 TPSC2 to TPSC0 (Channel 3) .......................................................................... 308 TPSC2 to TPSC0 (Channel 4) .......................................................................... 309 TPSC2 to TPSC0 (Channel 5) .......................................................................... 309 MD3 to MD0 .................................................................................................... 311 TIORH_0 .......................................................................................................... 313 TIORL_0........................................................................................................... 314 TIOR_1 ............................................................................................................. 315 TIOR_2 ............................................................................................................. 316 TIORH_3 .......................................................................................................... 317 TIORL_3........................................................................................................... 318 TIOR_4 ............................................................................................................. 319 TIOR_5 ............................................................................................................. 320 TIORH_0 .......................................................................................................... 320 TIORL_0........................................................................................................... 322 TIOR_1 ............................................................................................................. 323 TIOR_2 ............................................................................................................. 324 TIORH_3 .......................................................................................................... 325 TIORL_3........................................................................................................... 326 TIOR_4 ............................................................................................................. 327 TIOR_5 ............................................................................................................. 328 Register Combinations in Buffer Operation ..................................................... 346 Cascaded Combinations.................................................................................... 349 PWM Output Registers and Output Pins .......................................................... 352 Clock Input Pins in Phase Counting Mode ....................................................... 356 Up/Down-Count Conditions in Phase Counting Mode 1.................................. 357 Up/Down-Count Conditions in Phase Counting Mode 2.................................. 358 Up/Down-Count Conditions in Phase Counting Mode 3................................. 359 Up/Down-Count Conditions in Phase Counting Mode 4.................................. 360 TPU Interrupts .................................................................................................. 362 Section 11 Programmable Pulse Generator (PPG) Table 11.1 Pin Configuration.................................................................................................. 382 Rev. 2.00 Mar. 15, 2006 Page xxxv of xxxviii Section 12 Watchdog Timer (WDT) Table 12.1 WDT Interrupt Source .......................................................................................... 409 Section 13 Serial Communication Interface (SCI) Table 13.1 Pin Configuration.................................................................................................. 415 Table 13.2 Relationships between N Setting in BRR and Bit Rate B..................................... 432 Table 13.3 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (1) ...... 433 Table 13.3 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (2) ...... 434 Table 13.4 Maximum Bit Rate for Each Operating Frequency (Asynchronous Mode).......... 435 Table 13.5 Maximum Bit Rate with External Clock Input (Asynchronous Mode) ................ 436 Table 13.6 BRR Settings for Various Bit Rates (Clocked Synchronous Mode)..................... 436 Table 13.7 Maximum Bit Rate with External Clock Input (Clocked Synchronous Mode) .... 437 Table 13.8 BRR Settings for Various Bit Rates (Smart Card Interface Mode, n = 0, S = 372) ....................................................... 438 Table 13.9 Maximum Bit Rate for Each Operating Frequency (Smart Card Interface Mode, S = 372).................................................................. 438 Table 13.10 Serial Transfer Formats (Asynchronous Mode)................................................ 440 Table 13.11 SSR Status Flags and Receive Data Handling .................................................. 447 Table 13.12 SCI Interrupt Sources........................................................................................ 474 Table 13.13 SCI Interrupt Sources........................................................................................ 475 Section 14 Synchronous Serial Communication Unit (SSU) Table 14.1 Pin Configuration.................................................................................................. 483 Table 14.2 Correspondence Between DATS Bit Setting and SSTDR .................................... 497 Table 14.3 Correspondence Between DATS Bit Setting and SSRDR.................................... 499 Table 14.4 Communication Modes and Pin States of SSI and SSO Pins ............................... 502 Table 14.5 Communication Modes and Pin States of SSCK Pin............................................ 503 Table 14.6 Communication Modes and Pin States of SCS Pin............................................... 503 Table 14.7 Interrupt Sources................................................................................................... 519 Section 15 A/D Converter Table 15.1 Pin Configuration.................................................................................................. 524 Table 15.2 Analog Input Channels and Corresponding ADDR Registers .............................. 526 Table 15.3 A/D Conversion Characteristics (Single Mode) ................................................... 536 Table 15.4 A/D Conversion Characteristics (Scan Mode)...................................................... 536 Table 15.5 A/D Converter Interrupt Source............................................................................ 537 Table 15.6 Analog Pin Specifications..................................................................................... 543 Section 17 Flash Memory (0.18-mm F-ZTAT Version) Table 17.1 Differences between Boot Mode, User Program Mode, User Boot Mode, and Programmer Mode ......................................................................................... 550 Table 17.2 Pin Configuration.................................................................................................. 555 Rev. 2.00 Mar. 15, 2006 Page xxxvi of xxxviii Table 17.3 Table 17.4 Table 17.5 Table 17.6 Table 17.7 Table 17.8 Table 17.9 Table 17.10 Table 17.11 Table 17.12 Table 17.13 Table 17.14 Table 17.15 Table 17.16 Table 17.17 Table 17.18 Registers/Parameters and Target Modes............................................................... 556 Parameters and Target Modes............................................................................... 563 On-Board Programming Mode Setting ................................................................. 576 System Clock Frequency for Automatic-Bit-Rate Adjustment............................. 577 Executable Memory MAT .................................................................................... 595 Usable Area for Programming in User Program Mode......................................... 596 Usable Area for Erasure in User Program Mode .................................................. 597 Usable Area for Programming in User Boot Mode........................................... 598 Usable Area for Erasure in User Boot Mode .................................................... 599 Hardware Protection ......................................................................................... 600 Software Protection........................................................................................... 601 Device Types Supported in Programmer Mode................................................ 607 Inquiry and Selection Commands ..................................................................... 611 Programming/Erasing Commands .................................................................... 625 Status Code ....................................................................................................... 634 Error Code ........................................................................................................ 635 Section 18 Clock Pulse Generator Table 18.1 Damping Resistance Value ................................................................................... 643 Table 18.2 Crystal Resonator Characteristics ......................................................................... 644 Section 19 Power-Down Modes Table 19.1 Operating States.................................................................................................... 650 Table 19.2 Oscillation Settling Time Settings ........................................................................ 660 Table 19.3 B Pin (PA7) State in Each Processing State ....................................................... 662 Section 21 Electrical Characteristics Table 21.1 Absolute Maximum Ratings ................................................................................. 705 Table 21.2 DC Characteristics (1)........................................................................................... 706 Table 21.2 DC Characteristics (2)........................................................................................... 707 Table 21.3 Permissible Output Currents ................................................................................. 708 Table 21.4 Clock Timing ........................................................................................................ 709 Table 21.5 Control Signal Timing .......................................................................................... 711 Table 21.6 Timing of On-Chip Peripheral Modules (1).......................................................... 712 Table 21.6 Timing of On-Chip Peripheral Modules (2).......................................................... 714 Table 21.7 A/D Conversion Characteristics............................................................................ 719 Table 21.8 Flash Memory Characteristics .............................................................................. 720 Appendix Table A.1 Port States in Each Pin State................................................................................. 721 Rev. 2.00 Mar. 15, 2006 Page xxxvii of xxxviii Rev. 2.00 Mar. 15, 2006 Page xxxviii of xxxviii Section 1 Overview Section 1 Overview 1.1 Features * 32-bit high-speed H8SX CPU Upward compatible with the H8/300 CPU, H8/300H CPU, and H8S CPU Sixteen 16-bit general registers 87 basic instructions * Extensive peripheral functions DMA controller (DMAC) Data transfer controller (DTC) 16-bit timer pulse unit (TPU) Programmable pulse generator (PPG) Watch dog timer (WDT) Serial communication interface (SCI) can be used in asynchronous and clocked synchronous mode Synchronous serial communication unit (SSU) 10-bit A/D converter Clock pulse generator * On-chip memory Product Classification Flash memory version H8SX/1582 Product Model R5F61582 ROM 256 kbytes RAM 12 kbytes * General I/O port 82 input/output ports 17 input ports * Supports power-down modes * Small package Package LQFP1414-120 Code PLQP0120LA-A (FP-120B) Body Size 14.0 x 14.0 mm Pin Pitch 0.40 mm Rev. 2.00 Mar. 15, 2006 Page 1 of 754 REJ09B0199-0200 Section 1 Overview 1.2 Block Diagram WDT Interrupt controller TPU (unit 0) x 6 channels TPU (unit 1) x 6 channels PPG Port 1 Port 2 RAM Port 3 Port 4 Port 5 Port 6 ROM BSC Peripheral bus Internal bus H8SX CPU SCI x 2 channels SSU x 3 channels A/D (unit 0) x 8 channels A/D (unit 1) x 8 channels On-chip debugging function for E10A Port A Port B Port D Port H Port I Port J Port K DTC DMAC x 4 channels Clock pulse generator [Legend] CPU: Central processing unit DTC: Data transfer controller DMAC: DMA controller BSC: Bus controller WDT: Watchdog timer TPU: PPG: SCI: SSU: 16-bit timer pulse unit Programmable pulse generator Serial communication interface Synchronous serial communication unit Figure 1.1 Block Diagram of H8SX/1582 Rev. 2.00 Mar. 15, 2006 Page 2 of 754 REJ09B0199-0200 Section 1 Overview 1.3 1.3.1 Pin Assignments Pin Assignments Vss EXTAL XTAL Vcc P26/TIOCA5/IRQ14-A NMI RES P25/TIOCA4/IRQ13-A P37/PO15/TIOCA2/TIOCB2/TCLKD/TCK*1 P36/PO14/TIOCA2/TDI*1 P35/PO13/TIOCA1/TIOCB1/TCLKC/TMS*1 P34/PO12/TIOCA1/TRST*1 PA0 MD1 P40/AN12 P41/AN13 P42/AN14 P43/AN15 P44/AN8 P45/AN9 P46/AN10 AVcc1 P47/AN11 AVss P50/AN0 AVcc0 P51/AN1 P52/AN2 P53/AN3 P54/AN4 P55/AN5 P56/AN6 P57/AN7 MD0 PI0 PD0/SSO0 PI1 PD1/SSI0 PD2/SSCK0 PI2 PD3/SCS0 PD4/SSO1 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 PA1/SSCK2 PA2/SSI2 P27/TIOCA5/TIOCB5/IRQ15-A PA3/SSO2 EMLE*1 P24/TIOCA4/TIOCB4/IRQ12-A P33/PO11/TIOCC0/TIOCD0/TCLKB P32/PO10/TIOCC0/TCLKA P31/PO9/TIOCA0/TIOCB0 P30/PO8/TIOCA0 PA4 PA5 PA6 PB2 Vcc PA7/B Vss P23/TIOCC3/TIOCD3/IRQ11-A P64/IRQ12-B P65/IRQ13-B PI3 P66/IRQ14-B PJ0/TIOCA6 PJ1/TIOCA6/TIOCB6 PJ2/TIOCC6/TCLKE PJ3/TIOCC6/TIOCD6/TCLKF P67/IRQ15-B PJ4/TIOCA7 PJ5/TIOCA7/TIOCB7/TCLKG PJ6/TIOCA8 PJ7/TIOCA8/TIOCB8/TCLKH PI4 Vss PK0/TIOCA9 Vcc PK1/TIOCA9/TIOCB9 PI5 PK2/TIOCC9 PK3/TIOCC9/TIOCD9 PD5/SSI1 PD6/SSCK1 PD7/SCS1 Vcc P60/TxD4/IRQ8-B Vss P61/RxD4/IRQ9-B P62/SCK4/IRQ10-B P63/IRQ11-B/TDO*1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 PLQP0120LA-A (FP-120B) (top view) Index*2 P22/TIOCC3/IRQ10-A P21/TIOCA3/IRQ9-A/SCS2 P20/TIOCA3/TIOCB3/IRQ8-A P17/ADTRG1/IRQ7 P16/SCK3/IRQ6 P15/RxD3/IRQ5 P14/TxD3/IRQ4 P13/ADTRG0/IRQ3 P12/IRQ2 PB1 VCL P11/IRQ1 Vss P10/IRQ0 Vcc PH7 PH6 PB0 PH5 PH4 PH3 PH2 PH1 PI7 PH0 PK7/TIOCA11/TIOCB11 PK6/TIOCA11 PI6 PK5/TIOCA10/TIOCB10 PK4/TIOCA10 Previous package Example: TFP-120 (TQFP1414-120L) 120 120 1 FP-120B (LQFP1414-120) 1 Index Index Notes: 1. The EMLE (emulator enable) pin enables/disables the on-chip debugging functions. When the EMLE pin is driven high, the TDO, TDI, TCK, and TRST pins are used specific for the E10A. In this case, other pin functions are disabled. 2. The index of this package differs from that of previous ones. A small circular indentation is the index of this package. Figure 1.2 Pin Assignments of H8SX/1582 Rev. 2.00 Mar. 15, 2006 Page 3 of 754 REJ09B0199-0200 Section 1 Overview 1.3.2 Table 1.1 Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Pin Configuration in Each Operating Mode Pin Configuration in Each Operating Mode Abbreviation in Mode 1, Mode 2, and Mode 3 PD5/SSI1 PD6/SSCK1 PD7/SCS1 Vcc P60/TxD4/IRQ8-B Vss P61/RxD4/IRQ9-B P62/SCK4/IRQ10-B P63/IRQ11-B/TDO* P64/IRQ12-B P65/IRQ13-B PI3 P66/IRQ14-B PJ0/TIOCA6 PJ1/TIOCA6/TIOCB6 PJ2/TIOCC6/TCLKE PJ3/TIOCC6/TIOCD6/TCLKF P67/IRQ15-B PJ4/TIOCA7 PJ5/TIOCA7/TIOCB7/TCLKG PJ6/TIOCA8 PJ7/TIOCA8/TIOCB8/TCLKH PI4 Vss PK0/TIOCA9 Vcc PK1/TIOCA9/TIOCB9 PI5 Rev. 2.00 Mar. 15, 2006 Page 4 of 754 REJ09B0199-0200 Section 1 Overview Pin No. 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 Abbreviation in Mode 1, Mode 2, and Mode 3 PK2/TIOCC9 PK3/TIOCC9/TIOCD9 PK4/TIOCA10 PK5/TIOCA10/TIOCB10 PI6 PK6/TIOCA11 PK7/TIOCA11/TIOCB11 PH0 PI7 PH1 PH2 PH3 PH4 PH5 PB0 PH6 PH7 Vcc P10/IRQ0 Vss P11/IRQ1 VCL PB1 P12/IRQ2 P13/ADTRG0/IRQ3 P14/TxD3/IRQ4 P15/RxD3/IRQ5 P16/SCK3/IRQ6 P17/ADTRG1/IRQ7 P20/TIOCA3/TIOCB3/IRQ8-A P21/TIOCA3/IRQ9-A/SCS2 P22/TIOCC3/IRQ10-A Rev. 2.00 Mar. 15, 2006 Page 5 of 754 REJ09B0199-0200 Section 1 Overview Pin No. 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 Abbreviation in Mode 1, Mode 2, and Mode 3 P23/TIOCC3/TIOCD3/IRQ11-A Vss PA7/B Vcc PB2 PA6 PA5 PA4 P30/PO8/TIOCA0 P31/PO9/TIOCA0/TIOCB0 P32/PO10/TIOCC0/TCLKA P33/PO11/TIOCC0/TIOCD0/TCLKB P24/TIOCA4/TIOCB4/IRQ12-A P34/PO12/TIOCA1/TRST* P35/PO13/TIOCA1/TIOCB1/TCLKC/TMS* P36/PO14/TIOCA2/TDI* P37/PO15/TIOCA2/TIOCB2/TCLKD/TCK* P25/TIOCA4/IRQ13-A RES NMI P26/TIOCA5/IRQ14-A Vcc XTAL EXTAL Vss EMLE* PA3/SSO2 P27/TIOCA5/TIOCB5/IRQ15-A PA2/SSI2 PA1/SSCK2 Rev. 2.00 Mar. 15, 2006 Page 6 of 754 REJ09B0199-0200 Section 1 Overview Pin No. 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 Note: * Abbreviation in Mode 1, Mode 2, and Mode 3 PA0 MD1 P40/AN12 P41/AN13 P42/AN14 P43/AN15 P44/AN8 P45/AN9 P46/AN10 AVcc1 P47/AN11 AVss P50/AN0 AVcc0 P51/AN1 P52/AN2 P53/AN3 P54/AN4 P55/AN5 P56/AN6 P57/AN7 MD0 PI0 PD0/SSO0 PI1 PD1/SSI0 PD2/SSCK0 PI2 PD3/SCS0 PD4/SSO1 The EMLE (emulator enable) pin enables/disables the on-chip debugging functions. When the EMLE pin is driven high, the TDO, TDI, TCK, TMS, and TRST pins are used specific for the E10A. In this case, other pin functions are disabled. Rev. 2.00 Mar. 15, 2006 Page 7 of 754 REJ09B0199-0200 Section 1 Overview 1.3.3 Table 1.2 Pin Functions Pin Functions Pin Number Classification Abbreviation Power supply VCC VCL VSS Clock XTAL EXTAL B Operating mode control MD1 MD0 H8SX/1582 I/O Description Power supply pins. Connect to the system power supply. Connect to VSS via a 0.1-uF capacitor (place it close to this pin). Ground pins. Connect to the system power supply (0 V). Pins for a crystal resonator. External clock can be input to the EXTAL pin. For a connection example, see section 18, Clock Pulse Generator. 4, 26, 46, 64, Input 82 50 Input 6, 24, 48, 62, Input 85 83 84 63 92 112 79 86 80 Input Input Input Input Input Output Supplies the system clock to external devices. Input Pins for setting the operating mode. The signal levels of these pins must not be changed during operation. Reset signal input pin. This LSI enters the reset state when this signal goes low. Input pin for on-chip emulator enable signal. Normally the signal level should be fixed low. Non-maskable interrupt request signal. When this pin is not in use, this signal must be fixed high. System control RES EMLE Interrupts NMI Rev. 2.00 Mar. 15, 2006 Page 8 of 754 REJ09B0199-0200 Section 1 Overview Pin Number Classification Abbreviation Interrupts IRQ15-A/IRQ15-B IRQ14-A/IRQ14-B IRQ13-A/IRQ13-B IRQ12-A/IRQ12-B IRQ11-A/IRQ11-B IRQ10-A/IRQ10-B IRQ9-A/IRQ9-B IRQ8-A/IRQ8-B IRQ7 IRQ6 IRQ5 IRQ4 IRQ3 IRQ2 IRQ1 IRQ0 Debugging interface TRST TMS TDO TDI TCK 16-bit timer pulse unit (TPU) (unit 0) TCLKA TCLKB TCLKC TCLKD TIOCA0 TIOCB0 TIOCC0 TIOCD0 H8SX/1582 88/18 81/13 78/11 73/10 61/9 60/8 59/7 58/5 57 56 55 54 53 52 49 47 74 75 9 76 77 71 72 75 77 69, 70 70 72, 71 72 I/O Signals for TGRA_0 to TGRD_0. These are used for the input capture inputs/output compare outputs/PWM outputs. Input Input Output Input Input Input Input pins for the external clocks. Interface pins for debugging by the on-chip emulator. I/O Input Description Maskable interrupt request signal. Rev. 2.00 Mar. 15, 2006 Page 9 of 754 REJ09B0199-0200 Section 1 Overview Pin Number Classification Abbreviation 16-bit timer pulse unit (TPU) (unit 0) TIOCA1 TIOCB1 TIOCA2 TIOCB2 TIOCA3 TIOCB3 TIOCC3 TIOCD3 TIOCA4 TIOCB4 TIOCA5 TIOCB5 16-bit timer pulse unit (TPU) (unit 1) TCLKE TCLKF TCLKG TCLKH TIOCA6 TIOCB6 TIOCC6 TIOCD6 TIOCA7 TIOCB7 TIOCA8 TIOCB8 TIOCA9 TIOCB9 TIOCC9 TIOCD9 H8SX/1582 74, 75 75 76, 77 77 58, 59 58 60, 61 61 73, 78 73 81, 88 88 16 17 20 22 14, 15 15 16, 17 17 19, 20 20 21, 22 22 25, 27 27 29, 30 30 I/O I/O I/O Signals for TGRA_7 toTGRB_7. These are used for the input capture inputs/output compare outputs/PWM outputs. Signals for TGRA_8 toTGRB_8. These are used for the input capture inputs/output compare outputs/PWM outputs. Signals for TGRA_9 toTGRD_9. These are used for the input capture inputs/output compare outputs/PWM outputs. I/O Signals for TGRA_6 toTGRD_6. These are used for the input capture inputs/output compare outputs/PWM outputs. Input I/O I/O Signals for TGRA_4 and TGRB_4. These are used for the input capture inputs/output compare outputs/PWM outputs. Signals for TGRA_5 and TGRB_5. These are used for the input capture inputs/output compare outputs/PWM outputs. Input pins for the external clocks. I/O I/O I/O I/O Description Signals for TGRA_1 and TGRB_1. These are used for the input capture inputs/output compare outputs/PWM outputs. Signals for TGRA_2 and TGRB_2. These are used for the input capture inputs/output compare outputs/PWM outputs. Signals for TGRA_3 toTGRD_3. These are used for the input capture inputs/output compare outputs/PWM outputs. Rev. 2.00 Mar. 15, 2006 Page 10 of 754 REJ09B0199-0200 Section 1 Overview Pin Number Classification Abbreviation 16-bit timer pulse unit (TPU) (unit 1) TIOCA10 TIOCB10 TIOCA11 TIOCB11 Programmable pulse generator (PPG) PO15 PO14 PO13 PO12 PO11 PO10 PO9 PO8 Serial TxD3 communiTxD4 cation interface RxD3 (SCI) RxD4 SCK3 SCK4 Synchro-nous serial communication unit (SSU) SSO2 SSO1 SSO0 SSI2 SSI1 SSI0 SSCK2 SSCK1 SSCK0 SCS2 SCS1 SCS0 H8SX/1582 31, 32 32 34, 35 35 77 76 75 74 72 71 70 69 54 5 55 7 56 8 87 120 114 89 1 116 90 2 117 59 3 119 I/O Input/output pins for chip select. I/O Input/output pins for clock. I/O Input/output pins for data. I/O Input/output pins for data. I/O Input/output pins for clock signals. Input Input pins for receive data. Output Output pins for transmit data. I/O I/O I/O Description Signals for TGRA_10 toTGRB_10. These are used for the input capture inputs/output compare outputs/PWM outputs. Signals for TGRA_11 toTGRB_11. These are used for the input capture inputs/output compare outputs/PWM outputs. Output Output pins for the pulse signals. Rev. 2.00 Mar. 15, 2006 Page 11 of 754 REJ09B0199-0200 Section 1 Overview Pin Number Classification Abbreviation A/D converter AN15 AN14 AN13 AN12 AN11 AN10 AN9 AN8 AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0 ADTRG0 ADTRG1 AVCC0 AVCC1 H8SX/1582 96 95 94 93 101 99 98 97 111 110 109 108 107 106 105 103 53 57 104 100 Input Input Input pins for the external trigger signal to start A/D conversion. Analog power supply and reference power supply pins for the A/D converter. When the A/D converter is not in use, connect to the system power supply. Ground pin for the A/D and D/A converters. Connect to the system power supply (0 V). I/O Input Description Input pins for the analog signals for the A/D converter. AVSS 102 Input Rev. 2.00 Mar. 15, 2006 Page 12 of 754 REJ09B0199-0200 Section 1 Overview Pin Number Classification Abbreviation I/O port P17 P16 P15 P14 P13 P12 P11 P10 P27 P26 P25 P24 P23 P22 P21 P20 P37 P36 P35 P34 P33 P32 P31 P30 P47 P46 P45 P44 P43 P42 P41 P40 H8SX/1582 57 56 55 54 53 52 49 47 88 81 78 73 61 60 59 58 77 76 75 74 72 71 70 69 101 99 98 97 96 95 94 93 Input 8-bit input pins. I/O 8-bit input/output pins. I/O 8-bit input/output pins. I/O I/O Description 8-bit input/output pins. Rev. 2.00 Mar. 15, 2006 Page 13 of 754 REJ09B0199-0200 Section 1 Overview Pin Number Classification Abbreviation I/O port P57 P56 P55 P54 P53 P52 P51 P50 P67 P66 P65 P64 P63 P62 P61 P60 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 PB2 PB1 PB0 H8SX/1582 111 110 109 108 107 106 105 103 18 13 11 10 9 8 7 5 63 66 67 68 87 89 90 91 65 51 43 I/O 3-bit input/output pins. Input I/O 1-bit input pin. 7-bit input/output pins. I/O 8-bit input/output pins. I/O Input Description 8-bit input pins. Rev. 2.00 Mar. 15, 2006 Page 14 of 754 REJ09B0199-0200 Section 1 Overview Pin Number Classification Abbreviation I/O port PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PH7 PH6 PH5 PH4 PH3 PH2 PH1 PH0 PI7 PI6 PI5 PI4 PI3 PI2 PI1 PI0 PJ7 PJ6 PJ5 PJ4 PJ3 PJ2 PJ1 PJ0 H8SX/1582 3 2 1 120 119 117 116 114 45 44 42 41 40 39 38 36 37 33 28 23 12 118 115 113 22 21 20 19 17 16 15 14 I/O 8-bit input/output pins. I/O 8-bit input/output pins. I/O 8-bit input/output pins. I/O I/O Description 8-bit input/output pins. Rev. 2.00 Mar. 15, 2006 Page 15 of 754 REJ09B0199-0200 Section 1 Overview Pin Number Classification Abbreviation I/O port PK7 PK6 PK5 PK4 PK3 PK2 PK1 PK0 H8SX/1582 35 34 32 31 30 29 27 25 I/O I/O Description 8-bit input/output pins. Rev. 2.00 Mar. 15, 2006 Page 16 of 754 REJ09B0199-0200 Section 2 CPU Section 2 CPU The H8SX CPU is a high-speed CPU with an internal 32-bit architecture that is upwardcompatible with the H8/300, H8/300H, and H8S CPUs. The H8SX CPU has sixteen 16-bit general registers, can handle a 4-Gbyte linear address space, and is ideal for a realtime control system. 2.1 Features * Upward-compatible with H8/300, H8/300H, and H8S CPUs Can execute H8/300, H8/300H, and H8S/2000 object programs * Sixteen 16-bit general registers Also usable as sixteen 8-bit registers or eight 32-bit registers * 87 basic instructions 8/16/32-bit arithmetic and logic instructions Multiply and divide instructions Bit field transfer instructions Powerful bit-manipulation instructions Bit condition branch instructions Multiply-and-accumulate instruction * Eleven addressing modes Register direct [Rn] Register indirect [@ERn] Register indirect with displacement [@(d:2,ERn), @(d:16,ERn), or @(d:32,ERn)] Index register indirect with displacement [@(d:16,RnL.B), @(d:32,RnL.B), @(d:16,Rn.W), @(d:32,Rn.W), @(d:16,ERn.L), or @(d:32,ERn.L)] Register indirect with pre-/post-increment or pre-/post-decrement [@+ERn, @ERn+, @-ERn, or @ERn-] Absolute address [@aa:8, @aa:16, @aa:24, or @aa:32] Immediate [#xx:3, #xx:4, #xx:8, #xx:16, or #xx:32] Program-counter relative [@(d:8,PC) or @(d:16,PC)] Program-counter relative with index register [@(RnL.B,PC), @(Rn.W,PC), or @(ERn.L,PC)] Memory indirect [@@aa:8] Extended memory indirect [@@vec:7] Rev. 2.00 Mar. 15, 2006 Page 17 of 754 REJ09B0199-0200 Section 2 CPU * Two base registers Vector base register Short address base register * 4-Gbyte address space Program: 4 Gbytes Data: 4 Gbytes * High-speed operation All frequently-used instructions executed in one or two states 8/16/32-bit register-register add/subtract: 1 state 8 x 8-bit register-register multiply: 1 state 16 / 8-bit register-register divide: 10 states 16 x 16-bit register-register multiply: 1 state 32 / 16-bit register-register divide: 18 states 32 x 32-bit register-register multiply: 5 states 32 / 32-bit register-register divide: 18 states * Four CPU operating modes Normal mode Middle mode Advanced mode Maximum mode * Power-down modes Transition is made by execution of SLEEP instruction Choice of CPU operating clocks Notes: 1. Advanced mode is only supported as the CPU operating mode of the H8SX/1582. Normal, middle, and maximum modes are not supported. 2. The multiplier and divider are supported by the H8SX/1582. 3. In the H8SX/1582, an instruction is fetched in 32-bit mode. Rev. 2.00 Mar. 15, 2006 Page 18 of 754 REJ09B0199-0200 Section 2 CPU 2.2 CPU Operating Modes The H8SX CPU has four operating modes: normal, middle, advanced and maximum modes. For details on mode settings, see section 3.1, Operating Mode Selection. Maximum 64 kbytes for program Normal mode and data areas combined Maximum 16-Mbyte program Middle mode area and 64-kbyte data area, maximum 16 Mbytes for program and data areas combined CPU operating modes Maximum 16-Mbyte program Advanced mode area and 4-Gbyte data area, maximum 4 Gbytes for program and data areas combined Maximum 4 Gbytes for program and data areas combined Maximum mode Figure 2.1 CPU Operating Modes 2.2.1 Normal Mode The exception vector table and stack have the same structure as in the H8/300 CPU. Note: Normal mode is not supported in this LSI. * Address Space The maximum address space of 64 kbytes can be accessed. * Extended Registers (En) The extended registers (E0 to E7) can be used as 16-bit registers, or as the upper 16-bit segments of 32-bit registers. When the extended register En is used as a 16-bit register it can contain any value, even when the corresponding general register Rn is used as an address register. (If the general register Rn is referenced in the register indirect addressing mode with pre-/post-increment or pre-/post-decrement and a carry or borrow occurs, however, the value in the corresponding extended register En will be affected.) * Instruction Set All instructions and addressing modes can be used. Only the lower 16 bits of effective addresses (EA) are valid. Rev. 2.00 Mar. 15, 2006 Page 19 of 754 REJ09B0199-0200 Section 2 CPU * Exception Vector Table and Memory Indirect Branch Addresses In normal mode, the top area starting at H'0000 is allocated to the exception vector table. One branch address is stored per 16 bits. The structure of the exception vector table is shown in figure 2.2. H'0000 H'0001 H'0002 H'0003 Reset exception vector Reset exception vector Exception vector table Figure 2.2 Exception Vector Table (Normal Mode) The memory indirect (@@aa:8) and extended memory indirect (@@vec:7) addressing modes are used in the JMP and JSR instructions. An 8-bit absolute address included in the instruction code specifies a memory location. Execution branches to the contents of the memory location. * Stack Structure The stack structure of PC at a subroutine branch and that of PC and CCR at an exception handling are shown in figure 2.3. The PC contents are saved or restored in 16-bit units. SP PC (16 bits) SP *2 (SP ) EXR*1 Reserved*1,*3 CCR CCR*3 PC (16 bits) (a) Subroutine Branch (b) Exception Handling Notes: 1. When EXR is not used it is not stored on the stack. 2. SP when EXR is not used. 3. Ignored on return. Figure 2.3 Stack Structure (Normal Mode) Rev. 2.00 Mar. 15, 2006 Page 20 of 754 REJ09B0199-0200 Section 2 CPU 2.2.2 Middle Mode The program area in middle mode is extended to 16 Mbytes as compared with that in normal mode. * Address Space The maximum address space of 16 Mbytes can be accessed as a total of the program and data areas. For individual areas, up to 16 Mbytes of the program area or up to 64 kbytes of the data area can be allocated. * Extended Registers (En) The extended registers (E0 to E7) can be used as 16-bit registers, or as the upper 16-bit segments of 32-bit registers. When the extended register En is used as a 16-bit register (in other than the JMP and JSR instructions), it can contain any value even when the corresponding general register Rn is used as an address register. (If the general register Rn is referenced in the register indirect addressing mode with pre-/post-increment or pre-/postdecrement and a carry or borrow occurs, however, the value in the corresponding extended register En will be affected.) * Instruction Set All instructions and addressing modes can be used. Only the lower 16 bits of effective addresses (EA) are valid and the upper eight bits are sign-extended. * Exception Vector Table and Memory Indirect Branch Addresses In middle mode, the top area starting at H'000000 is allocated to the exception vector table. One branch address is stored per 32 bits. The upper eight bits are ignored and the lower 24 bits are stored. The structure of the exception vector table is shown in figure 2.4. The memory indirect (@@aa:8) and extended memory indirect (@@vec:7) addressing modes are used in the JMP and JSR instructions. An 8-bit absolute address included in the instruction code specifies a memory location. Execution branches to the contents of the memory location. In middle mode, an operand is a 32-bit (longword) operand, providing a 32-bit branch address. The upper eight bits are reserved and assumed to be H'00. * Stack Structure The stack structure of PC at a subroutine branch and that of PC and CCR at an exception handling are shown in figure 2.5. The PC contents are saved or restored in 24-bit units. Rev. 2.00 Mar. 15, 2006 Page 21 of 754 REJ09B0199-0200 Section 2 CPU 2.2.3 Advanced Mode The data area is extended to 4 Gbytes as compared with that in middle mode. * Address Space The maximum address space of 4 Gbytes can be linearly accessed. For individual areas, up to 16 Mbytes of the program area and up to 4 Gbytes of the data area can be allocated. * Extended Registers (En) The extended registers (E0 to E7) can be used as 16-bit registers, or as the upper 16-bit segments of 32-bit registers or address registers. * Instruction Set All instructions and addressing modes can be used. * Exception Vector Table and Memory Indirect Branch Addresses In advanced mode, the top area starting at H'00000000 is allocated to the exception vector table. One branch address is stored per 32 bits. The upper eight bits are ignored and the lower 24 bits are stored. The structure of the exception vector table is shown in figure 2.4. H'00000000 H'00000001 H'00000002 H'00000003 H'00000004 H'00000005 H'00000006 H'00000007 Reserved Exception vector table Reset exception vector Reserved Figure 2.4 Exception Vector Table (Middle and Advanced Modes) The memory indirect (@@aa:8) and extended memory indirect (@@vec:7) addressing modes are used in the JMP and JSR instructions. An 8-bit absolute address included in the instruction code specifies a memory location. Execution branches to the contents of the memory location. In advanced mode, an operand is a 32-bit (longword) operand, providing a 32-bit branch address. The upper eight bits are reserved and assumed to be H'00. Rev. 2.00 Mar. 15, 2006 Page 22 of 754 REJ09B0199-0200 Section 2 CPU * Stack Structure The stack structure of PC at a subroutine branch and that of PC and CCR at an exception handling are shown in figure 2.5. The PC contents are saved or restored in 24-bit units. SP SP Reserved PC (24 bits) (SP *2 ) EXR*1 Reserved*1,*3 CCR PC (24 bits) (a) Subroutine Branch (b) Exception Handling Notes: 1. When EXR is not used it is not stored on the stack. 2. SP when EXR is not used. 3. Ignored on return. Figure 2.5 Stack Structure (Middle and Advanced Modes) 2.2.4 Maximum Mode The program area is extended to 4 Gbytes as compared with that in advanced mode. * Address Space The maximum address space of 4 Gbytes can be linearly accessed. * Extended Registers (En) The extended registers (E0 to E7) can be used as 16-bit registers or as the upper 16-bit segments of 32-bit registers or address registers. * Instruction Set All instructions and addressing modes can be used. * Exception Vector Table and Memory Indirect Branch Addresses In maximum mode, the top area starting at H'00000000 is allocated to the exception vector table. One branch address is stored per 32 bits. The structure of the exception vector table is shown in figure 2.6. Rev. 2.00 Mar. 15, 2006 Page 23 of 754 REJ09B0199-0200 Section 2 CPU H'00000000 H'00000001 H'00000002 H'00000003 H'00000004 H'00000005 H'00000006 H'00000007 Exception vector table Reset exception vector Figure 2.6 Exception Vector Table (Maximum Modes) The memory indirect (@@aa:8) and extended memory indirect (@@vec:7) addressing modes are used in the JMP and JSR instructions. An 8-bit absolute address included in the instruction code specifies a memory location. Execution branches to the contents of the memory location. In maximum mode, an operand is a 32-bit (longword) operand, providing a 32-bit branch address. * Stack Structure The stack structure of PC at a subroutine branch and that of PC and CCR at an exception handling are shown in figure 2.7. The PC contents are saved or restored in 32-bit units. The EXR contents are saved or restored regardless of whether or not EXR is in use. SP PC (32 bits) SP EXR CCR PC (32 bits) (a) Subroutine Branch (b) Exception Handling Figure 2.7 Stack Structure (Maximum Mode) Rev. 2.00 Mar. 15, 2006 Page 24 of 754 REJ09B0199-0200 Section 2 CPU 2.3 Instruction Fetch The H8SX CPU has two modes for instruction fetch: 16-bit and 32-bit modes. It is recommended that the mode be set according to the bus width of the memory in which a program is stored. The instruction-fetch mode setting does not affect operation other than instruction fetch such as data accesses. Note: In the H8SX/1582, an instruction is fetched in 32-bit mode. 2.4 Address Space Figure 2.8 shows a memory map of the H8SX CPU. The address space differs depending on the CPU operating mode. Normal mode H'0000 H'000000 H'007FFF Program area Data area (64 kbytes) Middle mode H'00000000 Advanced mode H'00000000 Maximum mode H'FFFF Program area (16 Mbytes) Program area (16 Mbytes) Data area (64 kbytes) H'FF8000 H'FFFFFF H'00FFFFFF Program area Data area (4 Gbytes) Data area (4 Gbytes) H'FFFFFFFF H'FFFFFFFF Figure 2.8 Memory Map Rev. 2.00 Mar. 15, 2006 Page 25 of 754 REJ09B0199-0200 Section 2 CPU 2.5 Registers The H8SX CPU has the internal registers shown in figure 2.9. There are two types of registers: general registers and control registers. The control registers are the 32-bit program counter (PC), 8-bit extended control register (EXR), 8-bit condition-code register (CCR), 32-bit vector base register (VBR), 32-bit short address base register (SBR), and 64-bit multiply-accumulate register (MAC). General Registers and Extended Registers 15 ER0 ER1 ER2 ER3 ER4 ER5 ER6 ER7 (SP) Control Registers 31 PC E0 E1 E2 E3 E4 E5 E6 E7 07 R0H R1H R2H R3H R4H R5H R6H R7H 07 R0L R1L R2L R3L R4L R5L R6L R7L 0 0 76543210 CCR I UI H U N Z V C 76543210 EXR T -- -- -- -- I2 I1 I0 31 VBR 31 SBR 63 MAC 31 [Legend] Stack pointer SP: Program counter PC: Condition-code register CCR: Interrupt mask bit I: User bit or interrupt mask bit UI: Half-carry flag H: User bit U: Negative flag N: Z: V: C: EXR: T: I2 to I0: VBR: SBR: MAC: Zero flag Overflow flag Carry flag Extended control register Trace bit Interrupt mask bits Vector base register Short address base register Multiply-accumulate register Sign extension MACL 0 41 MACH 12 (Reserved) 8 (Reserved) 32 0 0 Figure 2.9 CPU Registers Rev. 2.00 Mar. 15, 2006 Page 26 of 754 REJ09B0199-0200 Section 2 CPU 2.5.1 General Registers The H8SX CPU has eight 32-bit general registers. These general registers are all functionally alike and can be used as both address registers and data registers. When a general register is used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. Figure 2.10 illustrates the usage of the general registers. When the general registers are used as 32-bit registers or address registers, they are designated by the letters ER (ER0 to ER7). When the general registers are used as 16-bit registers, the ER registers are divided into 16-bit general registers designated by the letters E (E0 to E7) and R (R0 to R7). These registers are functionally equivalent, providing a maximum sixteen 16-bit registers. The E registers (E0 to E7) are also referred to as extended registers. When the general registers are used as 8-bit registers, the R registers are divided into 8-bit general registers designated by the letters RH (R0H to R7H) and RL (R0L to R7L). These registers are functionally equivalent, providing a maximum sixteen 8-bit registers. The general registers ER (ER0 to ER7), R (R0 to R7), and RL (R0L to R7L) are also used as index registers. The size in the operand field determines which register is selected. The usage of each register can be selected independently. * Address registers * 32-bit registers * 32-bit index registers General registers ER (ER0 to ER7) * 16-bit registers General registers E (E0 to E7) * 16-bit registers * 16-bit index registers General registers R (R0 to R7) * 8-bit registers General registers RH (R0H to R7H) * 8-bit registers * 8-bit index registers General registers RL (R0L to R7L) Figure 2.10 Usage of General Registers General register ER7 has the function of stack pointer (SP) in addition to its general-register function, and is used implicitly in exception handling and subroutine branches. Figure 2.11 shows the stack. Rev. 2.00 Mar. 15, 2006 Page 27 of 754 REJ09B0199-0200 Section 2 CPU Free area SP (ER7) Stack area Figure 2.11 Stack 2.5.2 Program Counter (PC) PC is a 32-bit counter that indicates the address of the next instruction the CPU will execute. The length of all CPU instructions is 16 bits (one word) or a multiple of 16 bits, so the least significant bit is ignored. (When the instruction code is fetched, the least significant bit is regarded as 0. 2.5.3 Condition-Code Register (CCR) CCR is an 8-bit register that contains internal CPU status information, including an interrupt mask (I) and user (UI, U) bits and half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags. Operations can be performed on the CCR bits by the LDC, STC, ANDC, ORC, and XORC instructions. The N, Z, V, and C flags are used as branch conditions for conditional branch (Bcc) instructions. Bit 7 Bit Name I Initial Value 1 R/W R/W Description Interrupt Mask Bit Masks interrupts when set to 1. This bit is set to 1 at the start of an exception handling. 6 UI Undefined R/W User Bit or Interrupt Mask Bit Can be written to and read from by software using the LDC, STC, ANDC, ORC, and XORC instructions. This bit can also be used as an interrupt mask bit. Rev. 2.00 Mar. 15, 2006 Page 28 of 754 REJ09B0199-0200 Section 2 CPU Bit 5 Bit Name H Initial Value R/W Description Half-Carry Flag When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B, or NEG.B instruction is executed, this flag is set to 1 if there is a carry or borrow at bit 3, and cleared to 0 otherwise. When the ADD.W, SUB.W, CMP.W, or NEG.W instruction is executed, this flag is set to 1 if there is a carry or borrow at bit 11, and cleared to 0 otherwise. When the ADD.L, SUB.L, CMP.L, or NEG.L instruction is executed, this flag is set to 1 if there is a carry or borrow at bit 27, and cleared to 0 otherwise. Undefined R/W 4 U Undefined R/W User Bit Can be written to and read from by software using the LDC, STC, ANDC, ORC, and XORC instructions. 3 N Undefined R/W Negative Flag Stores the value of the most significant bit (regarded as sign bit) of data. 2 Z Undefined R/W Zero Flag Set to 1 to indicate zero data, and cleared to 0 to indicate non-zero data. 1 V Undefined R/W Overflow Flag Set to 1 when an arithmetic overflow occurs, and cleared to 0 otherwise. 0 C Undefined R/W Carry Flag Set to 1 when a carry occurs, and cleared to 0 otherwise. A carry has the following types: * * * Carry from the result of addition Borrow from the result of subtraction Carry from the result of shift or rotation The carry flag is also used as a bit accumulator by bit manipulation instructions. Rev. 2.00 Mar. 15, 2006 Page 29 of 754 REJ09B0199-0200 Section 2 CPU 2.5.4 Extended Control Register (EXR) EXR is an 8-bit register that contains the trace bit (T) and three interrupt mask bits (I2 to I0). Operations can be performed on the EXR bits by the LDC, STC, ANDC, ORC, and XORC instructions. For details, see the hardware manual for the corresponding product. Bit 7 Bit Name T Initial Value 0 R/W R/W Description Trace Bit When this bit is set to 1, a trace exception is generated each time an instruction is executed. When this bit is cleared to 0, instructions are executed in sequence. 6 to 3 2 1 0 I2 I1 I0 All 1 1 1 1 R/W R/W R/W R/W Reserved These bits are always read as 1. Interrupt Mask Bits These bits designate the interrupt mask level (0 to 7). 2.5.5 Vector Base Register (VBR) VBR is a 32-bit register in which the upper 20 bits are valid. The lower 12 bits of this register are read as 0s. This register is a base address of the vector area for exception handlings other than a reset and a CPU address error (extended memory indirect is also out of the target). The initial value is H'00000000. The VBR contents are changed with the LDC and STC instructions. 2.5.6 Short Address Base Register (SBR) SBR is a 32-bit register in which the upper 24 bits are valid. The lower eight bits are read as 0s. In 8-bit absolute address addressing mode (@aa:8), this register is used as the upper address. The initial value is H'FFFFFF00. The SBR contents are changed with the LDC and STC instructions. Rev. 2.00 Mar. 15, 2006 Page 30 of 754 REJ09B0199-0200 Section 2 CPU 2.5.7 Multiply-Accumulate Register (MAC) MAC is a 64-bit register that stores the results of multiply-and-accumulate operations. It consists of two 32-bit registers denoted MACH and MACL. The lower 10 bits of MACH are valid; the upper bits are sign extended. The MAC contents are changed with the MAC, CLRMAC, LDMAC, and STMAC instructions. 2.5.8 Initial Values of CPU Registers Reset exception handling loads the start address from the vector table into the PC, clears the T bit in EXR to 0, and sets the I bits in CCR and EXR to 1. The general registers, MAC, and the other bits in CCR are not initialized. In particular, the initial value of the stack pointer (ER7) is undefined. The SP should therefore be initialized using an MOV.L instruction executed immediately after a reset. 2.6 Data Formats The H8SX CPU can process 1-bit, 4-bit BCD, 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2, ..., 7) of byte operand data. The DAA and DAS decimal-adjust instructions treat byte data as two digits of 4-bit BCD data. 2.6.1 General Register Data Formats Figure 2.12 shows the data formats in general registers. Rev. 2.00 Mar. 15, 2006 Page 31 of 754 REJ09B0199-0200 Section 2 CPU 1-bit data RnH 0 7 76543210 Don't care 7 0 76543210 1-bit data RnL Don't care 7 Upper 43 0 Lower 4-bit BCD data RnH Don't care 7 43 0 Lower 4-bit BCD data RnL Don't care Upper 0 Byte data RnH 7 Don't care MSB LSB 7 Don't care MSB 15 0 LSB 0 LSB Byte data RnL Word data Rn Word data En Longword data ERn MSB 0 LSB 16 15 En Rn RnL: General register RL MSB: Most significant bit LSB: Least significant bit 15 MSB 31 MSB 0 LSB [Legend] ERn: General register ER En: General register E Rn: General register R RnH: General register RH Figure 2.12 General Register Data Formats Rev. 2.00 Mar. 15, 2006 Page 32 of 754 REJ09B0199-0200 Section 2 CPU 2.6.2 Memory Data Formats Figure 2.13 shows the data formats in memory. The H8SX CPU can access word data and longword data which are stored at any addresses in memory. When word data begins at an odd address or longword data begins at an address other than a multiple of 4, a bus cycle is divided into two or more accesses. For example, when longword data begins at an odd address, the bus cycle is divided into byte, word, and byte accesses. In this case, these accesses are assumed to be individual bus cycles. However, instructions to be fetched, word and longword data to be accessed during execution of the stack manipulation, branch table manipulation, block transfer instructions, and MAC instruction should be located to even addresses. When SP (ER7) is used as an address register to access the stack, the operand size should be word size or longword size. Data Type Address 7 1-bit data Address L 7 6 5 4 3 2 1 0 0 Data Format Byte data Address L MSB LSB Word data Address 2M MSB Address 2M + 1 LSB Longword data Address 2N MSB Address 2N + 1 Address 2N + 2 Address 2N + 3 LSB Figure 2.13 Memory Data Formats Rev. 2.00 Mar. 15, 2006 Page 33 of 754 REJ09B0199-0200 Section 2 CPU 2.7 Instruction Set The H8SX CPU has 87 types of instructions. The instructions are classified by function as shown in table 2.1. The arithmetic operation, logic operation, shift, and bit manipulation instructions are called operation instruction in this manual. Table 2.1 Function Data transfer Instruction Classification Instructions MOV MOVFPE* , MOVTPE* POP, PUSH* LDM, STM MOVA 1 6 6 Size B/W/L B W/L L B/W*2 B B/W/L B B/W/L B L B/W W/L L W/L B B/W/L Types 6 Block transfer EEPMOV MOVMD MOVSD 3 Arithmetic operations ADD, ADDX, SUB, SUBX, CMP, NEG, INC, DEC DAA, DAS ADDS, SUBS MULXU, DIVXU, MULXS, DIVXS MULU, DIVU, MULS, DIVS MULU/U, MULS/U EXTU, EXTS TAS MAC LDMAC, STMAC CLRMAC 27 Logic operations Shift Bit manipulation AND, OR, XOR, NOT 4 8 20 SHLL, SHLR, SHAL, SHAR, ROTL, ROTR, ROTXL, ROTXR B/W/L BSET, BCLR, BNOT, BTST, BAND, BIAND, BOR, BIOR, BXOR, BIXOR, BLD, BILD, BST, BIST BSET/EQ, BSET/NE, BCLR/EQ, BCLR/NE, BSTZ, BISTZ BFLD, BFST B B B Rev. 2.00 Mar. 15, 2006 Page 34 of 754 REJ09B0199-0200 Section 2 CPU Function Branch Instructions BRA/BS, BRA/BC, BSR/BS, BSR/BC Bcc* , JMP, BSR, JSR, RTS RTS/L BRA/S 5 Size B* L*5 L* 5 3 Types 9 System control TRAPA, RTE, SLEEP, NOP RTE/L LDC, STC, ANDC, ORC, XORC 10 B/W/L Total 87 [Legend] B: Byte size W: Word size L: Longword size Notes: 1. POP.W Rn and PUSH.W Rn are identical to MOV.W @SP+, Rn and MOV.W Rn, @-SP. POP.L ERn and PUSH.L ERn are identical to MOV.L @SP+, ERn and MOV.L ERn, @-SP. 2. Size of data to be added with a displacement 3. Size of data to specify a branch condition 4. Bcc is the generic designation of a conditional branch instruction. 5. Size of general register to be restored 6. Not available in this LSI. Rev. 2.00 Mar. 15, 2006 Page 35 of 754 REJ09B0199-0200 Section 2 CPU 2.7.1 Instructions and Addressing Modes Table 2.2 indicates the combinations of instructions and addressing modes that the H8SX CPU can use. Table 2.2 Combinations of Instructions and Addressing Modes (1) Addressing Mode @(d, RnL.B/ Rn.W/ @(d,ERn) ERn.L) SD SD @-ERn/ @ERn+/ @ERn-/ @+ERn SD S/D S/D*1 S/D*2 S/D*2 S S S S S SD*3 SD*3 SD*3 S D S D D D S SD S S S D SD SD D D S SD S S S S D D D S:4 S:4 SD SD SD SD SD SD*5 SD D D S SD SD D D S SD SD D D S SD SD D D S SD SD D D S SD SD D D S SD SD D D S D D S D D S SD SD D D S SD SD Classification Data transfer Instruction MOV Size B/W/L B #xx S Rn SD S/D S/D S/D S/D S @ERn SD @aa:8 @aa:16/ @aa:32 SD MOVFPE, MOVTPE*12 POP, PUSH LDM, STM MOVA* Block transfer 4 B W/L L B/W B B/W/L B B B B B W/L EEPMOV MOVMD MOVSD Arithmetic operations ADD, CMP SUB B B B B W/L ADDX, SUBX B/W/L B/W/L B/W/L INC, DEC ADDS, SUBS DAA, DAS MULXU, DIVXU MULU, DIVU B/W/L L B B/W W/L Rev. 2.00 Mar. 15, 2006 Page 36 of 754 REJ09B0199-0200 Section 2 CPU Addressing Mode @(d, RnL.B/ Rn.W/ @(d,ERn) ERn.L) @-ERn/ @ERn+/ @ERn-/ @+ERn Classification Arithmetic operations Instruction Size #xx S:4 S:4 Rn SD SD D D D @ERn @aa:8 @aa:16/ @aa:32 MULXS, DIVXS B/W MULS, DIVS NEG W/L B W/L EXTU, EXTS TAS MAC CLRMAC LDMAC STMAC W/L B B B B W/L NOT B W/L D D D D D D D D D D D D D D D D D O S D S D D S SD S SD D D D D D D D D D D D D D D D D D D D D D D SD D D D D D S SD SD D D D D D S SD SD D D D D D S SD SD D D D D D D D S D S SD SD D D D D Logic operations AND, OR, XOR Shift SHLL, SHLR B W/L*6 B/W/L*7 SHAL, SHAR B ROTL, ROTR W/L ROTXL, ROTXR Bit manipulation BSET, BCLR, BNOT, BTST, BSET/cc, BCLR/cc BAND, BIAND, BOR, BIOR, BXOR, BIXOR, BLD, BILD, BST, BIST, BSTZ, BISTZ Bit manipulation BFLD BFST B B D D D D B B D S S D S D S D Rev. 2.00 Mar. 15, 2006 Page 37 of 754 REJ09B0199-0200 Section 2 CPU Addressing Mode @(d, RnL.B/ Rn.W/ @(d,ERn) ERn.L) @-ERn/ @ERn+/ @ERn-/ @+ERn Classification Branch Instruction BRA/BS, BRA/BC*8 BSR/BS, BSR/BC*8 Size B B B/W*9 L B/W*9 L B #xx Rn @ERn S S @aa:8 S S @aa:16/ @aa:32 S S S System control LDC (CCR, EXR) LDC (VBR, SBR) STC (CCR, EXR) STC (VBR, SBR) ANDC, ORC, XORC SLEEP NOP S S S D D S S S*10 D D D*11 D S O O [Legend] d: d:16 or d:32 S: Can be specified as a source operand. D: Can be specified as a destination operand. SD: Can be specified as either a source or destination operand or both. S/D: Can be specified as either a source or destination operand. S:4: 4-bit immediate data can be specified as a source operand. Notes: 1. Only @aa:16 is available. 2. @ERn+ as a source operand and @-ERn as a destination operand 3. Specified by ER5 as a source address and ER6 as a destination address for data transfer. 4. Size of data to be added with a displacement 5. Only @ERn- is available 6. When the number of bits to be shifted is 1, 2, 4, 8, or 16 7. When the number of bits to be shifted is specified by 5-bit immediate data or a general register 8. Size of data to specify a branch condition 9. Byte when immediate or register direct, otherwise, word 10. Only @ERn+ is available 11. Only @-ERn is available 12. Not available in this LSI. Rev. 2.00 Mar. 15, 2006 Page 38 of 754 REJ09B0199-0200 Section 2 CPU Table 2.2 Combinations of Instructions and Addressing Modes (2) Addressing Mode @(RnL. B/Rn.W/ Classification Branch Instruction BRA/BS, BRA/BC BSR/BS, BSR/BC Bcc BRA BRA/S JMP BSR JSR RTS, RTS/L System control TRAPA RTE, RTE/L O O O O O O* O Size @ERn ERn.L, @(d,PC) PC) O @aa:24 @ aa:32 @@ aa:8 @@vec:7 O O O O O O O O O O O O [Legend] d: d:8 or d:16 Note: * Only @(d:8, PC) is available. Rev. 2.00 Mar. 15, 2006 Page 39 of 754 REJ09B0199-0200 Section 2 CPU 2.7.2 Table of Instructions Classified by Function Tables 2.4 to 2.11 summarize the instructions in each functional category. The notation used in these tables is defined in table 2.3. Table 2.3 Operation Notation Description General register (destination)* General register (source)* General register* General register (32-bit register) Destination operand Source operand Extended control register Condition-code register Vector base register Short address base register N (negative) flag in CCR Z (zero) flag in CCR V (overflow) flag in CCR C (carry) flag in CCR Program counter Stack pointer Immediate data Displacement Addition Subtraction Multiplication Division Logical AND Logical OR Logical exclusive OR Move Logical not (logical complement) 8-, 16-, 24-, or 32-bit length Operation Notation Rd Rs Rn ERn (EAd) (EAs) EXR CCR VBR SBR N Z V C PC SP #IMM disp + - x / :8/:16/:24/:32 Note: * General registers include 8-bit registers (R0H to R7H, R0L to R7L), 16-bit registers (R0 to R7, E0 to E7), and 32-bit registers (ER0 to ER7). Rev. 2.00 Mar. 15, 2006 Page 40 of 754 REJ09B0199-0200 Section 2 CPU Table 2.4 Instruction MOV MOVFPE* MOVTPE* POP PUSH LDM Data Transfer Instructions Size B/W/L B B W/L W/L L Function #IMM (EAd), (EAs) (EAd) Transfers data between immediate data, general registers, and memory. (EAs) Rd Rs (EAs) @SP+ Rn Restores the data from the stack to a general register. Rn @-SP Saves general register contents on the stack. @SP+ Rn (register list) Restores the data from the stack to multiple general registers. Two, three, or four general registers which have serial register numbers can be specified. STM L Rn (register list) @-SP Saves the contents of multiple general registers on the stack. Two, three, or four general registers which have serial register numbers can be specified. MOVA B/W EA Rd Zero-extends and shifts the contents of a specified general register or memory data and adds them with a displacement. The result is stored in a general register. Note: * Not available in this LSI. Rev. 2.00 Mar. 15, 2006 Page 41 of 754 REJ09B0199-0200 Section 2 CPU Table 2.5 Instruction EEPMOV.B EEPMOV.W Block Transfer Instructions Size B Function Transfers a data block. Transfers byte data which begins at a memory location specified by ER5 to a memory location specified by ER6. The number of byte data to be transferred is specified by R4 or R4L. B Transfers a data block. Transfers byte data which begins at a memory location specified by ER5 to a memory location specified by ER6. The number of byte data to be transferred is specified by R4. MOVMD.B MOVMD.W W Transfers a data block. Transfers word data which begins at a memory location specified by ER5 to a memory location specified by ER6. The number of word data to be transferred is specified by R4. MOVMD.L L Transfers a data block. Transfers longword data which begins at a memory location specified by ER5 to a memory location specified by ER6. The number of longword data to be transferred is specified by R4. MOVSD.B B Transfers a data block with zero data detection. Transfers byte data which begins at a memory location specified by ER5 to a memory location specified by ER6. The number of byte data to be transferred is specified by R4. When zero data is detected during transfer, the transfer stops and execution branches to a specified address. Rev. 2.00 Mar. 15, 2006 Page 42 of 754 REJ09B0199-0200 Section 2 CPU Table 2.6 Instruction ADD SUB Arithmetic Operation Instructions Size B/W/L Function (EAd) #IMM (EAd), (EAd) (EAs) (EAd) Performs addition or subtraction on data between immediate data, general registers, and memory. Immediate byte data cannot be subtracted from byte data in a general register. B/W/L (EAd) #IMM C (EAd), (EAd) (EAs) C (EAd) Performs addition or subtraction with carry on data between immediate data, general registers, and memory. The addressing mode which specifies a memory location can be specified as register indirect with post-decrement or register indirect. B/W/L Rd 1 Rd, Rd 2 Rd Increments or decrements a general register by 1 or 2. (Byte operands can be incremented or decremented by 1 only.) L B Rd 1 Rd, Rd 2 Rd, Rd 4 Rd Adds or subtracts the value 1, 2, or 4 to or from data in a general register. Rd (decimal adjust) Rd Decimal-adjusts an addition or subtraction result in a general register by referring to the CCR to produce 2-digit 4-bit BCD data. B/W Rd x Rs Rd Performs unsigned multiplication on data in two general registers: either 8 bits x 8 bits 16 bits, or 16 bits x 16 bits 32 bits. ADDX SUBX INC DEC ADDS SUBS DAA DAS MULXU MULU W/L Rd x Rs Rd Performs unsigned multiplication on data in two general registers: either 8 bits x 8 bits 16 bits, or 16 bits x 16 bits 32 bits. MULU/U L Rd x Rs Rd Performs unsigned multiplication on data in two general registers (32 bits x 32 bits upper 32 bits). MULXS B/W Rd x Rs Rd Performs signed multiplication on data in two general registers: either 8 bits x 8 bits 16 bits, or 16 bits x 16 bits 32 bits. MULS W/L Rd x Rs Rd Performs signed multiplication on data in two general registers: either 16 bits x 16 bits 16 bits, or 32 bits x 32 bits 32 bits. MULS/U L Rd x Rs Rd Performs signed multiplication on data in two general registers (32 bits x 32 bits upper 32 bits). Rev. 2.00 Mar. 15, 2006 Page 43 of 754 REJ09B0199-0200 Section 2 CPU Instruction DIVXU Size B/W Function Rd / Rs Rd Performs unsigned division on data in two general registers: either 16 bits / 8 bits 8-bit quotient and 8-bit remainder, or 32 bits / 16 bits 16-bit quotient and 16-bit remainder. DIVU W/L Rd / Rs Rd Performs unsigned division on data in two general registers: either 16 bits / 16 bits 16-bit quotient, or 32 bits / 32 bits 32-bit quotient. DIVXS B/W Rd / Rs Rd Performs signed division on data in two general registers: either 16 bits / 8 bits 8-bit quotient and 8-bit remainder, or 32 bits / 16 bits 16-bit quotient and 16-bit remainder. DIVS W/L Rd / Rs Rd Performs signed division on data in two general registers: either 16 bits / 16 bits 16-bit quotient, or 32 bits / 32 bits 32-bit quotient. CMP B/W/L (EAd) - #IMM, (EAd) - (EAs) Compares data between immediate data, general registers, and memory and stores the result in CCR. NEG B/W/L 0 - (EAd) (EAd) Takes the two's complement (arithmetic complement) of data in a general register or the contents of a memory location. EXTU W/L (EAd) (zero extension) (EAd) Performs zero-extension on the lower 8 or 16 bits of data in a general register or memory to word or longword size. The lower 8 bits to word or longword, or the lower 16 bits to longword can be zero-extended. EXTS W/L (EAd) (sign extension) (EAd) Performs sign-extension on the lower 8 or 16 bits of data in a general register or memory to word or longword size. The lower 8 bits to word or longword, or the lower 16 bits to longword can be sign-extended. TAS MAC B @ERd - 0, 1 ( CLRMAC 0 MAC Clears MAC to zero. Rev. 2.00 Mar. 15, 2006 Page 44 of 754 REJ09B0199-0200 Section 2 CPU Instruction LDMAC STMAC Size Function Rs MAC Loads data from a general register to MAC. MAC Rd Stores data from MAC to a general register. Table 2.7 Instruction AND Logic Operation Instructions Size B/W/L Function (EAd) #IMM (EAd), (EAd) (EAs) (EAd) Performs a logical AND operation on data between immediate data, general registers, and memory. OR B/W/L (EAd) #IMM (EAd), (EAd) (EAs) (EAd) Performs a logical OR operation on data between immediate data, general registers, and memory. XOR B/W/L (EAd) #IMM (EAd), (EAd) (EAs) (EAd) Performs a logical exclusive OR operation on data between immediate data, general registers, and memory. NOT B/W/L (EAd) (EAd) Takes the one's complement of the contents of a general register or a memory location. Rev. 2.00 Mar. 15, 2006 Page 45 of 754 REJ09B0199-0200 Section 2 CPU Table 2.8 Instruction SHLL SHLR Shift Operation Instructions Size B/W/L Function (EAd) (shift) (EAd) Performs a logical shift on the contents of a general register or a memory location. The contents of a general register or a memory location can be shifted by 1, 2, 4, 8, or 16 bits. The contents of a general register can be shifted by any bits. In this case, the number of bits is specified by 5-bit immediate data or the lower 5 bits of the contents of a general register. SHAL SHAR B/W/L (EAd) (shift) (EAd) Performs an arithmetic shift on the contents of a general register or a memory location. 1-bit or 2-bit shift is possible. ROTL ROTR ROTXL ROTXR B/W/L (EAd) (rotate) (EAd) Rotates the contents of a general register or a memory location. 1-bit or 2-bit rotation is possible. B/W/L (EAd) (rotate) (EAd) Rotates the contents of a general register or a memory location with the carry bit. 1-bit or 2-bit rotation is possible. Rev. 2.00 Mar. 15, 2006 Page 46 of 754 REJ09B0199-0200 Section 2 CPU Table 2.9 Instruction BSET Bit Manipulation Instructions Size B Function 1 ( BSET/cc B if cc, 1 ( BCLR B 0 ( BCLR/cc B if cc, 0 ( BNOT B ( BTST B ( BAND B C ( BIAND B C [ ( Rev. 2.00 Mar. 15, 2006 Page 47 of 754 REJ09B0199-0200 Section 2 CPU Instruction BOR Size B Function C ( BIOR B C [~ ( BXOR B C ( BIXOR B C [~ ( BLD B ( BILD B ~ ( BST B C ( BSTZ B Z ( BIST B C ( Rev. 2.00 Mar. 15, 2006 Page 48 of 754 REJ09B0199-0200 Section 2 CPU Instruction BISTZ Size B Function Z ( BFLD B (EAs) (bit field) Rd Transfers a specified bit field in memory location contents to the lower bits of a specified general register. BFST B Rs (EAd) (bit field) Transfers the lower bits of a specified general register to a specified bit field in memory location contents. Table 2.10 Branch Instructions Instruction BRA/BS BRA/BC BSR/BS BSR/BC Bcc BRA/S B Size B Function Tests a specified bit in memory location contents. If the specified condition is satisfied, execution branches to a specified address. Tests a specified bit in memory location contents. If the specified condition is satisfied, execution branches to a subroutine at a specified address. Branches to a specified address if the specified condition is satisfied. Branches unconditionally to a specified address after executing the next instruction. The next instruction should be a 1-word instruction except for the block transfer and branch instructions. Branches unconditionally to a specified address. Branches to a subroutine at a specified address. Branches to a subroutine at a specified address. Returns from a subroutine. Returns from a subroutine, restoring data from the stack to multiple general registers. JMP BSR JSR RTS RTS/L Rev. 2.00 Mar. 15, 2006 Page 49 of 754 REJ09B0199-0200 Section 2 CPU Table 2.11 System Control Instructions Instruction TRAPA RTE RTE/L SLEEP LDC Size B/W Function Starts trap-instruction exception handling. Returns from an exception-handling routine. Returns from an exception-handling routine, restoring data from the stack to multiple general registers. Causes a transition to a power-down state. #IMM CCR, (EAs) CCR, #IMM EXR, (EAs) EXR Loads immediate data or the contents of a general register or a memory location to CCR or EXR. Although CCR and EXR are 8-bit registers, word-size transfers are performed between them and memory. The upper 8 bits are valid. L STC B/W Rs VBR, Rs SBR Transfers the general register contents to VBR or SBR. CCR (EAd), EXR (EAd) Transfers the contents of CCR or EXR to a general register or memory. Although CCR and EXR are 8-bit registers, word-size transfers are performed between them and memory. The upper 8 bits are valid. L ANDC ORC XORC NOP B B B VBR Rd, SBR Rd Transfers the contents of VBR or SBR to a general register. CCR #IMM CCR, EXR #IMM EXR Logically ANDs the CCR or EXR contents with immediate data. CCR #IMM CCR, EXR #IMM EXR Logically ORs the CCR or EXR contents with immediate data. CCR #IMM CCR, EXR #IMM EXR Logically exclusive-ORs the CCR or EXR contents with immediate data. PC + 2 PC Only increments the program counter. Rev. 2.00 Mar. 15, 2006 Page 50 of 754 REJ09B0199-0200 Section 2 CPU 2.7.3 Basic Instruction Formats The H8SX CPU instructions consist of 2-byte (1-word) units. An instruction consists of an operation field (op field), a register field (r field), an effective address extension (EA field), and a condition field (cc). Figure 2.14 shows examples of instruction formats. (1) Operation field only op NOP, RTS, etc. (2) Operation field and register fields op rm rn ADD.B Rn, Rm, etc. (3) Operation field, register fields, and effective address extension op EA (disp) rn rm MOV.B @(d:16, Rn), Rm, etc. (4) Operation field, effective address extension, and condition field op cc EA (disp) BRA d:16, etc Figure 2.14 Instruction Formats * Operation Field Indicates the function of the instruction, and specifies the addressing mode and operation to be carried out on the operand. The operation field always includes the first four bits of the instruction. Some instructions have two operation fields. * Register Field Specifies a general register. Address registers are specified by 3 bits, data registers by 3 bits or 4 bits. Some instructions have two register fields. Some have no register field. * Effective Address Extension 8, 16, or 32 bits specifying immediate data, an absolute address, or a displacement. * Condition Field Specifies the branch condition of Bcc instructions. Rev. 2.00 Mar. 15, 2006 Page 51 of 754 REJ09B0199-0200 Section 2 CPU 2.8 Addressing Modes and Effective Address Calculation The H8SX CPU supports the 11 addressing modes listed in table 2.12. Each instruction uses a subset of these addressing modes. Bit manipulation instructions use register direct, register indirect, or absolute addressing mode to specify an operand, and register direct (BSET, BCLR, BNOT, and BTST instructions) or immediate (3-bit) addressing mode to specify a bit number in the operand. Table 2.12 Addressing Modes No. Addressing Mode 1 2 3 4 5 Register direct Register indirect Register indirect with displacement Index register indirect with displacement Register indirect with post-increment Register indirect with pre-decrement Register indirect with pre-increment Register indirect with post-decrement 6 7 8 9 10 11 Absolute address Immediate Program-counter relative Program-counter relative with index register Memory indirect Extended memory indirect Symbol Rn @ERn @(d:2,ERn)/@(d:16,ERn)/@(d:32,ERn) @(d:16, RnL.B)/@(d:16,Rn.W)/@(d:16,ERn.L) @(d:32, RnL.B)/@(d:32,Rn.W)/@(d:32,ERn.L) @ERn+ @-ERn @+ERn @ERn- @aa:8/@aa:16/@aa:24/@aa:32 #xx:3/#xx:4/#xx:8/#xx:16/#xx:32 @(d:8,PC)/@(d:16,PC) @(RnL.B,PC)/@(Rn.W,PC)/@(ERn.L,PC) @@aa:8 @@vec:7 Rev. 2.00 Mar. 15, 2006 Page 52 of 754 REJ09B0199-0200 Section 2 CPU 2.8.1 Register Direct--Rn The operand value is the contents of an 8-, 16-, or 32-bit general register which is specified by the register field in the instruction code. R0H to R7H and R0L to R7L can be specified as 8-bit registers. R0 to R7 and E0 to E7 can be specified as 16-bit registers. ER0 to ER7 can be specified as 32-bit registers. 2.8.2 Register Indirect--@ERn The operand value is the contents of the memory location which is pointed to by the contents of an address register (ERn). ERn is specified by the register field of the instruction code. In advanced mode, if this addressing mode is used in a branch instruction, the lower 24 bits are valid and the upper 8 bits are all assumed to be 0 (H'00). 2.8.3 Register Indirect with Displacement --@(d:2, ERn), @(d:16, ERn), or @(d:32, ERn) The operand value is the contents of a memory location which is pointed to by the sum of the contents of an address register (ERn) and a 16- or 32-bit displacement. ERn is specified by the register field of the instruction code. The displacement is included in the instruction code and the 16-bit displacement is sign-extended when added to ERn. This addressing mode has a short format (@(d:2, ERn)). The short format can be used when the displacement is 1, 2, or 3 and the operand is byte data, when the displacement is 2, 4, or 6 and the operand is word data, or when the displacement is 4, 8, or 12 and the operand is longword data. Rev. 2.00 Mar. 15, 2006 Page 53 of 754 REJ09B0199-0200 Section 2 CPU 2.8.4 Index Register Indirect with Displacement--@(d:16,RnL.B), @(d:32,RnL.B), @(d:16,Rn.W), @(d:32,Rn.W), @(d:16,ERn.L), or @(d:32,ERn.L) The operand value is the contents of a memory location which is pointed to by the sum of the following operation result and a 16- or 32-bit displacement: a specified bits of the contents of an address register (RnL, Rn, ERn) specified by the register field in the instruction code are zeroextended to 32-bit data and multiplied by 1, 2, or 4. The displacement is included in the instruction code and the 16-bit displacement is sign-extended when added to ERn. If the operand is byte data, ERn is multiplied by 1. If the operand is word or longword data, ERn is multiplied by 2 or 4, respectively. 2.8.5 Register Indirect with Post-Increment, Pre-Decrement, Pre-Increment, or Post-Decrement--@ERn+, @-ERn, @+ERn, or @ERn- Register indirect with post-increment--@ERn+ (1) The operand value is the contents of a memory location which is pointed to by the contents of an address register (ERn). ERn is specified by the register field of the instruction code. After the memory location is accessed, 1, 2, or 4 is added to the address register contents and the sum is stored in the address register. The value added is 1 for byte access, 2 for word access, or 4 for longword access. (2) Register indirect with pre-decrement--@-ERn The operand value is the contents of a memory location which is pointed to by the following operation result: the value 1, 2, or 4 is subtracted from the contents of an address register (ERn). ERn is specified by the register field of the instruction code. After that, the operand value is stored in the address register. The value subtracted is 1 for byte access, 2 for word access, or 4 for longword access. (3) Register indirect with pre-increment--@+ERn The operand value is the contents of a memory location which is pointed to by the following operation result: the value 1, 2, or 4 is added to the contents of an address register (ERn). ERn is specified by the register field of the instruction code. After that, the operand value is stored in the address register. The value added is 1 for byte access, 2 for word access, or 4 for longword access. Rev. 2.00 Mar. 15, 2006 Page 54 of 754 REJ09B0199-0200 Section 2 CPU (4) Register indirect with post-decrement--@ERn- The operand value is the contents of a memory location which is pointed to by the contents of an address register (ERn). ERn is specified by the register field of the instruction code. After the memory location is accessed, 1, 2, or 4 is subtracted from the address register contents and the remainder is stored in the address register. The value subtracted is 1 for byte access, 2 for word access, or 4 for longword access. If the contents of a general register which is also used as an address register is written to memory using this addressing mode, data to be written is the contents of the general register after calculating an effective address. If the same general register is specified in an instruction and two effective addresses are calculated, the contents of the general register after the first calculation of an effective address is used in the second calculation of an effective address. Example 1: MOV.W R0, @ER0+ When ER0 before execution is H'12345678, H'567A is written at H'12345678. Example 2: MOV.B @ER0+, @ER0+ When ER0 before execution is H'00001000, H'00001000 is read and the contents is written at H'00001001. After execution, ER0 is H'00001002. 2.8.6 Absolute Address--@aa:8, @aa:16, @aa:24, or @aa:32 The operand value is the contents of a memory location which is pointed to by an absolute address included in the instruction code. There are 8-bit (@aa:8), 16-bit (@aa:16), 24-bit (@aa:24), and 32-bit (@aa:32) absolute addresses. To access the data area, the absolute address of 8 bits (@aa:8), 16 bits (@aa:16), or 32 bits (@aa:32) is used. For an 8-bit absolute address, the upper 24 bits are specified by SBR. For a 16bit absolute address, the upper 16 bits are sign-extended. A 32-bit absolute address can access the entire address space. To access the program area, the absolute address of 24 bits (@aa:24) or 32 bits (@aa:32) is used. For a 24-bit absolute address, the upper 8 bits are all assumed to be 0 (H'00). Rev. 2.00 Mar. 15, 2006 Page 55 of 754 REJ09B0199-0200 Section 2 CPU Table 2.13 shows the accessible absolute address ranges. Table 2.13 Absolute Address Access Ranges Absolute Address Data area 8 bits (@aa:8) 16 bits (@aa:16) 32 bits (@aa:32) Program area 24 bits (@aa:24) 32 bits (@aa:32) Normal Mode Middle Mode Advanced Mode Maximum Mode A consecutive 256-byte area (the upper address is set in SBR) H'0000 to H'FFFF H'000000 to H'007FFF, H'FF8000 to H'FFFFFF H'000000 to H'FFFFFF H'00000000 to H'00007FFF, H'FFFF8000 to H'FFFFFFFF H'00000000 to H'FFFFFFFF H'00000000 to H'00FFFFFF H'00000000 to H'00FFFFFF H'00000000 to H'FFFFFFFF 2.8.7 Immediate--#xx The operand value is 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) data included in the instruction code. This addressing mode has short formats in which 3- or 4-bit immediate data can be used. When the size of immediate data is less than that of the destination operand value (byte, word, or longword) the immediate data is zero-extended. The ADDS, SUBS, INC, and DEC instructions contain immediate data implicitly. Some bit manipulation instructions contain 3-bit immediate data in the instruction code, for specifying a bit number. The BFLD and BFST instructions contain 8-bit immediate data in the instruction code, for specifying a bit field. The TRAPA instruction contains 2-bit immediate data in the instruction code, for specifying a vector address. Rev. 2.00 Mar. 15, 2006 Page 56 of 754 REJ09B0199-0200 Section 2 CPU 2.8.8 Program-Counter Relative--@(d:8, PC) or @(d:16, PC) This mode is used in the Bcc and BSR instructions. The operand value is a 32-bit branch address, which is the sum of an 8- or 16-bit displacement in the instruction code and the 32-bit address of the PC contents. The 8-bit or 16-bit displacement is sign-extended to 32 bits when added to the PC contents. The PC contents to which the displacement is added is the address of the first byte of the next instruction, so the possible branching range is -126 to +128 bytes (-63 to +64 words) or -32766 to +32768 bytes (-16383 to +16384 words) from the branch instruction. The resulting value should be an even number. In advanced mode, only the lower 24 bits of this branch address are valid; the upper 8 bits are all assumed to be 0 (H'00). 2.8.9 Program-Counter Relative with Index Register--@(RnL.B, PC), @(Rn.W, PC), or @(ERn.L, PC) This mode is used in the Bcc and BSR instructions. The operand value is a 32-bit branch address, which is the sum of the following operation result and the 32-bit address of the PC contents: the contents of an address register specified by the register field in the instruction code (RnL, Rn, or ERn) is zero-extended and multiplied by 2. The PC contents to which the displacement is added is the address of the first byte of the next instruction. In advanced mode, only the lower 24 bits of this branch address are valid; the upper 8 bits are all assumed to be 0 (H'00). 2.8.10 Memory Indirect--@@aa:8 This mode can be used by the JMP and JSR instructions. The operand value is a branch address, which is the contents of a memory location pointed to by an 8-bit absolute address in the instruction code. The upper bits of an 8-bit absolute address are all assumed to be 0, so the address range is 0 to 255 (H'0000 to H'00FF in normal mode, H'000000 to H'0000FF in other modes). In normal mode, the memory location is pointed to by word-size data and the branch address is 16 bits long. In other modes, the memory location is pointed to by longword-size data. In middle or advanced mode, the first byte of the longword-size data is assumed to be all 0 (H'00). Note that the top part of the address range is also used as the exception handling vector area. A vector address of an exception handling other than a reset or a CPU address error can be changed by VBR. Rev. 2.00 Mar. 15, 2006 Page 57 of 754 REJ09B0199-0200 Section 2 CPU Figure 2.15 shows an example of specification of a branch address using this addressing mode. Specified by @aa:8 Branch address Specified by @aa:8 Reserved Branch address (a) Normal Mode (b) Advanced Mode Figure 2.15 Branch Address Specification in Memory Indirect Mode 2.8.11 Extended Memory Indirect--@@vec:7 This mode can be used by the JMP and JSR instructions. The operand value is a branch address, which is the contents of a memory location pointed to by the following operation result: the sum of 7-bit data in the instruction code and the value of H'80 is multiplied by 2 or 4. The address range to store a branch address is H'0100 to H'01FF in normal mode and H'000200 to H'0003FF in other modes. In assembler notation, an address to store a branch address is specified. In normal mode, the memory location is pointed to by word-size data and the branch address is 16 bits long. In other modes, the memory location is pointed to by longword-size data. In middle or advanced mode, the first byte of the longword-size data is assumed to be all 0 (H'00). 2.8.12 Effective Address Calculation Tables 2.14 and 2.15 show how effective addresses are calculated in each addressing mode. The lower bits of the effective address are valid and the upper bits are ignored (zero extended or sign extended) according to the CPU operating mode. The valid bits in middle mode are as follows: * The lower 16 bits of the effective address are valid and the upper 16 bits are sign-extended for the transfer and operation instructions. * The lower 24 bits of the effective address are valid and the upper eight bits are zero-extended for the branch instructions. Rev. 2.00 Mar. 15, 2006 Page 58 of 754 REJ09B0199-0200 Section 2 CPU Table 2.14 Effective Address Calculation for Transfer and Operation Instructions No. 1 Addressing Mode and Instruction Format Immediate op 2 Register direct op 3 Register indirect op 4 r 31 31 General register contents 15 disp Sign extension 0 0 + 31 0 rm rn 31 General register contents 0 31 0 IMM Effective Address Calculation Effective Address (EA) Register indirect with 16-bit displacement op r disp Register indirect with 32-bit displacement op r disp 31 General register contents disp 0 + 31 0 5 Index register indirect with 16-bit displacement 31 Zero extension Contents of general register (RL, R, or ER) 31 15 Sign extension 31 Zero extension Contents of general register (RL, R, or ER) 31 disp 0 1, 2, or 4 x 0 disp 0 1, 2, or 4 x 0 + 31 0 + 31 0 op r disp Index register indirect with 32-bit displacement op r disp 6 Register indirect with post-increment or post-decrement op r 31 General register contents 0 1, 2, or 4 0 General register contents 1, 2, or 4 31 0 31 0 Register indirect with pre-increment or pre-decrement op r 31 7 8-bit absolute address 31 op aa SBR 7 aa 0 31 0 16-bit absolute address op aa 31 Sign extension 15 aa 0 31 0 32-bit absolute address op aa 31 aa 0 31 0 Rev. 2.00 Mar. 15, 2006 Page 59 of 754 REJ09B0199-0200 Section 2 CPU Table 2.15 Effective Address Calculation for Branch Instructions No. 1 Addressing Mode and Instruction Format Register indirect op 2 r Effective Address Calculation 31 General register contents 0 Effective Address (EA) 31 0 Program-counter relative with 8-bit displacement 31 PC contents 31 op disp Sign extension 7 disp 0 + 0 31 0 Program-counter relative with 16-bit displacement 31 op disp 31 PC contents 15 Sign extension 0 31 0 disp + 0 3 Program-counter relative with index register op r 0 Zero extension Contents of general register (RL, R, or ER) x 2 + 0 31 PC contents Zero 31extension23 31 31 0 4 24-bit absolute address op aa 0 aa 31 0 32-bit absolute address op aa 31 aa 0 31 0 5 Memory indirect 31 op aa 31 Memory contents Zero extension 7 aa 0 31 0 0 6 Extended memory indirect 31 op vec Zero extension 7 1 0 vec 2 or 4 x 0 0 Memory contents 31 0 31 31 2.8.13 MOVA Instruction The MOVA instruction stores the effective address in a general register. 1. Firstly, data is obtained by the addressing mode shown in item 2of table 2.14. 2. Next, the effective address is calculated using the obtained data as the index by the addressing mode shown in item 5 of table 2.14. The obtained data is used instead of the general register. The result is stored in a general register. For details, see H8SX Family Software Manual. Rev. 2.00 Mar. 15, 2006 Page 60 of 754 REJ09B0199-0200 Section 2 CPU 2.9 Processing States The H8SX CPU has five main processing states: the reset state, exception-handling state, program execution state, bus-released state, and program stop state. Figure 2.16 indicates the state transitions. * Reset state In this state the CPU and internal peripheral modules are all initialized and stopped. When the RES input goes low, all current processing stops and the CPU enters the reset state. All interrupts are masked in the reset state. Reset exception handling starts when the RES signal changes from low to high. The reset state can also be entered by a watchdog timer overflow. For details, refer to section 4, Exception Handling. * Exception-handling state The exception-handling state is a transient state that occurs when the CPU alters the normal processing flow due to activation of an exception source, such as, a reset, trace, interrupt, or trap instruction. The CPU fetches a start address (vector) from the exception handling vector table and branches to that address. For further details, refer to section 4, Exception Handling. * Program execution state In this state the CPU executes program instructions in sequence. * Bus-released state In this state, the bus has been released in response to a bus request from the DMA controller (DMAC) and data transfer controller (DTC). While the bus is released, the CPU halts operations. * Program stop state This is a power-down state in which the CPU stops operating. The program stop state occurs when a SLEEP instruction is executed or the CPU enters software standby mode. For details, refer to section 19, Power-Down Modes. Rev. 2.00 Mar. 15, 2006 Page 61 of 754 REJ09B0199-0200 Section 2 CPU Reset state* RES = high RES = low Bus-released state Exception-handling state Request for exception handling Interrupt Bus request request End of exception handling End of bus request Bus request End of bus request Program execution state Note: * Program stop state SLEEP instruction A transition to the reset state occurs whenever the RES signal goes low. A transition can also be made to the reset state when the watchdog timer overflows. Figure 2.16 State Transitions Rev. 2.00 Mar. 15, 2006 Page 62 of 754 REJ09B0199-0200 Section 3 MCU Operating Modes Section 3 MCU Operating Modes 3.1 Operating Mode Selection This LSI has three operating modes (modes 1 to 3). The operating mode is selected by the setting of mode pins (MD1 and MD0). Table 3.1 lists MCU operating mode settings. In this LSI, advanced mode for the CPU operating mode and 16-Mbyte address space are available. LSI initiation mode can be selected from boot mode and user boot mode for programming/erasing the flash memory and single chip initiation mode. Table 3.1 MCU Operating Mode Settings CPU Operating Mode Advanced Address Space 16 Mbytes MCU Operating Mode MD1 1 2 3 0 1 1 MD0 1 0 1 Description User boot mode Boot mode Single chip initiation mode On-Chip ROM Enabled Enabled Enabled In mode 1 and mode 2, which are user boot mode and boot mode, the flash memory can be programmed and erased. For details on user boot mode and boot mode, see section 17, Flash Memory (0.18-m F-ZTAT Version). In mode 3, this LSI operates in single chip mode. 3.2 Register Descriptions The following registers are related to the operating mode setting. * Mode control register (MDCR) * System control register (SYSCR) Rev. 2.00 Mar. 15, 2006 Page 63 of 754 REJ09B0199-0200 Section 3 MCU Operating Modes 3.2.1 Mode Control Register (MDCR) MDCR indicates the current operating mode. When MDCR is read, the states of signals input on pins MD1 and MD0 are latched. The latch is released by a reset. Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W 15 -- 0 R 7 -- 0 R 14 -- 1 R 6 -- 1 R 13 -- 0 R 5 -- 0 R 12 -- 1 R 4 -- 1 R 11 MDS3 Undefined* R 3 -- Undefined* R 10 MDS2 Undefined* R 2 -- Undefined* R 9 MDS1 Undefined* R 1 -- Undefined* R 8 MDS0 Undefined* R 0 -- Undefined* R Note: * Determined by pins MD1 and MD0. Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Note: * Bit Name MDS3 MDS2 MDS1 MDS0 Initial Value R/W 0 1 0 1 Undefined* Undefined* Undefined* Undefined* 0 1 0 1 Undefined* Undefined* Undefined* Undefined* R R R R R R R R R R R R R R R R Descriptions Reserved These are read-only bits and cannot be modified. Mode Select 3 to 0 These bits indicate the operating mode selected by the mode pins (MD1 and MD0) (see table 3.2). Reserved These are read-only bits and cannot be modified. Determined by pins MD1 and MD0. Rev. 2.00 Mar. 15, 2006 Page 64 of 754 REJ09B0199-0200 Section 3 MCU Operating Modes Table 3.2 Settings of Bits MSD3 to MSD0 MDCR MCU Operating Mode MD1 1 2 3 0 1 1 MD0 1 0 1 MDS3 1 1 0 MDS2 1 1 1 MDS1 0 0 0 MDS0 1 0 0 3.2.2 System Control Register (SYSCR) SYSCR controls MAC saturation operation, selects DTC operating mode, and enables/disables the on-chip RAM and the flash memory control registers. Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W 15 -- 1 R 7 FLSHE 0 R/W 14 -- 1 R 6 -- 0 R/W 13 MACS 0 R/W 5 -- 0 R/W 12 -- 1 R 4 -- 0 R/W 11 -- 0 R/W 3 -- 0 R/W 10 -- 1 R/W 2 -- 0 R/W 9 -- 0 R/W 1 DTCMD 1 R/W 8 RAME 1 R/W 0 -- 1 R/W Bit 15, 14 13 Bit Name MACS Initial Value All 1 0 R/W R R/W Descriptions Reserved These are read-only bits and cannot be modified. MAC Saturation Operation Control Selects either saturation operation or non-saturation operation for the MAC instruction. 0: MAC instruction is non-saturation operation 1: MAC instruction is saturation operation 12 11 1 0 R R/W Reserved This is a read-only bit and cannot be modified. Reserved This bit is always read as 0. The write value should always be 0. Rev. 2.00 Mar. 15, 2006 Page 65 of 754 REJ09B0199-0200 Section 3 MCU Operating Modes Bit 10 Bit Name Initial Value 1 R/W R/W Descriptions Reserved This bit is always read as 1. The write value should always be 1. 9 0 R/W Reserved This bit is always read as 0. The write value should always be 0. 8 RAME 1 R/W RAM Enable Enables or disables the on-chip RAM. This bit is initialized when the reset state is released. Do not write 0 during access to the on-chip RAM. 0: On-chip RAM disabled 1: On-chip RAM enabled 7 FLSHE 0 R/W Flash Memory Control Register Enable Controls accesses to the flash memory control registers. Setting this bit to 1 enables to read from and write to the flash memory control registers. Clearing this bit to 0 disables the flash memory control registers. At this time, the contents of the flash memory control registers are retained. The write value should be 0 when the LSI is not the flash memory version. 0: Disables the flash memory control registers 1: Enables the flash memory control registers 6 to 2 All 0 R/W Reserved These bits are always read as 0. The write value should always be 0. 1 DTCMD 1 R/W DTC Mode Select Selects DTC operating mode. 0: DTC is in full-address mode 1: DTC is in short address mode 0 1 R/W Reserved This bit is always read as 1. The write value should always be 1. Rev. 2.00 Mar. 15, 2006 Page 66 of 754 REJ09B0199-0200 Section 3 MCU Operating Modes 3.3 3.3.1 Operating Mode Descriptions Mode 1 Mode 1 is the user boot mode for the flash memory. The operations are the same as that in mode 3 other than programming/erasing the flash memory. 3.3.2 Mode 2 Mode 2 is the boot mode for the flash memory. The operations are the same as that in mode 3 other than programming/erasing the flash memory. 3.3.3 Mode 3 Mode 3 is advanced mode in which the address space is 16 Mbytes, and single-chip mode with the on-chip ROM enabled. Rev. 2.00 Mar. 15, 2006 Page 67 of 754 REJ09B0199-0200 Section 3 MCU Operating Modes 3.4 3.4.1 Address Map Address Map Figure 3.1 shows the address map. Mode 1 to mode 3 Single chip initiation mode (advanced mode) H'000000 On-chip ROM (256 kbytes) H'040000 Reserved H'FF9000 On-chip RAM (12 kbytes) H'FFC000 Reserved H'FFEA00 On-chip I/O register H'FFFF00 H'FFFF20 On-chip I/O register H'FFFFFF Reserved Figure 3.1 Address Map Rev. 2.00 Mar. 15, 2006 Page 68 of 754 REJ09B0199-0200 Section 4 Exception Handling Section 4 Exception Handling 4.1 Exception Handling Types and Priority As table 4.1 indicates, exception handling is caused by a reset, a trace, an address error, an interrupt, a trap instruction, and illegal instructions (general illegal instruction and slot illegal instruction). Exception handling is prioritized as shown in table 4.1. If two or more exceptions occur simultaneously, they are accepted and processed in order of priority. Exception sources, the stack structure, and operation of the CPU vary depending on the interrupt control mode. For details on the interrupt control mode, see section 5, Interrupt Controller. Table 4.1 Priority High Exception Types and Priority Exception Type Reset Exception Handling Start Timing Exception handling starts at the timing of level change from low to high on the RES pin, or when the watchdog timer overflows. The CPU enters the reset state when the RES pin is low. Exception handling starts when an undefined code is executed. Exception handling starts after execution of the current instruction or exception handling, if the trace (T) bit in EXR is set to 1. After an address error occurs, the exception handling starts on completion of the current instruction execution. Exception handling starts after execution of the current instruction or exception handling, if an interrupt request has occurred.*2 Exception handling starts by execution of a trap instruction (TRAPA). Illegal instruction Trace*1 Address error Interrupt Trap instruction*3 Low Notes: 1. Traces are enabled only in interrupt control mode 2. Trace exception handling is not executed after execution of an RTE instruction. 2. Interrupt detection is not performed on completion of ANDC, ORC, XORC, or LDC instruction execution, or on completion of reset exception handling. 3. Trap instruction exception handling requests are accepted at all times in the program execution state. Rev. 2.00 Mar. 15, 2006 Page 69 of 754 REJ09B0199-0200 Section 4 Exception Handling 4.2 Exception Sources and Exception Handling Vector Table Different vector table address offsets are assigned to different exception sources. The vector table addresses are calculated from the contents of the vector base register (VBR) and vector table address offset of the vector number. The start address of the exception service routine is fetched from the exception handling vector table indicated by this vector table address. Table 4.2 shows the correspondence between the exception sources and vector table address offsets. Table 4.3 shows the calculation method of exception handling vector table addresses. Since the usable modes differ depending on the product, for details on the available modes, see section 3, MCU Operating Modes. Table 4.2 Exception Handling Vector Table Vector Table Address Offset*1 Exception Source Reset Reserved for system use Vector Number 0 1 2 3 Illegal instruction Trace Reserved for system use Interrupt (NMI) Trap instruction (#0) (#1) (#2) (#3) CPU address error DMA address error*3 Reserved for system use 4 5 6 7 8 9 10 11 12 13 14 63 Normal Mode*2 H'0000 to H'0001 H'0002 to H'0003 H'0004 to H'0005 H'0006 to H'0007 H'0008 to H'0009 H'000A to H'000B H'000C to H'000D H'000E to H'000F H'0010 to H'0011 H'0012 to H'0013 H'0014 to H'0015 H'0016 to H'0017 H'0018 to H'0019 H'001A to H'001B H'001C to H'001D H'007E to H'007F Advanced, Middle, Maximum Modes H'0000 to H'0003 H'0004 to H'0007 H'0008 to H'000B H'000C to H'000F H'0010 to H'0013 H'0014 to H'0017 H'0018 to H'001B H'001C to H'001F H'0020 to H'0023 H'0024 to H'0027 H'0028 to H'002B H'002C to H'002F H'0030 to H'0033 H'0034 to H'0037 H'0038 to H'003B H'00FC to H'00FF Rev. 2.00 Mar. 15, 2006 Page 70 of 754 REJ09B0199-0200 Section 4 Exception Handling Vector Table Address Offset*1 Exception Source External interrupt IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 IRQ8 IRQ9 IRQ10 IRQ11 IRQ12 IRQ13 IRQ14 IRQ15 Reserved for system use Internal interrupt*4 Vector Number 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 255 Normal Mode*2 H'0080 to H'0081 H'0082 to H'0083 H'0084 to H'0085 H'0086 to H'0087 H'0088 to H'0089 H'008A to H'008B H'008C to H'008D H'008E to H'008F H'0090 to H'0091 H'0092 to H'0093 H'0094 to H'0095 H'0096 to H'0097 H'0098 to H'0099 H'009A to H'009B H'009C to H'009D H'009E to H'009F H'00A0 to H'00A1 H'00A2 to H'00A3 H'01FE to H'01FF Advanced, Middle, Maximum Modes H'0100 to H'0103 H'0104 to H'0107 H'0108 to H'010B H'010C to H'010F H'0110 to H'0113 H'0114 to H'0117 H'0118 to H'011B H'011C to H'011F H'0120 to H'0123 H'0124 to H'0127 H'0128 to H'012B H'012C to H'012F H'0130 to H'0133 H'0134 to H'0137 H'0138 to H'013B H'013C to H'013F H'0140 to H'0143 H'0144 to H'0147 H'03FC to H'03FF Notes: 1. 2. 3. 4. Lower 16 bits of the address. Not available in this LSI. A DMA address error is generated within the DTC and DMAC. For details on the interrupt vector table, see section 5.5, Interrupt Exception Handling Vector Table. Rev. 2.00 Mar. 15, 2006 Page 71 of 754 REJ09B0199-0200 Section 4 Exception Handling Table 4.3 Calculation Method of Exception Handling Vector Table Address Calculation Method of Vector Table Address Vector table address = (vector table address offset) Vector table address = VBR + (vector table address offset) Exception Source Reset, CPU address error Other than above [Legend] VBR: Vector base register Vector table address offset: See table 4.2. 4.3 Reset A reset has priority over any other exception. When the RES pin goes low, all processing halts and this LSI enters the reset state. To ensure that this LSI is reset, hold the RES pin low for at least 20 ms when the power is turned on. When operation is in progress, hold the RES pin low for at least 20 cycles. The chip can also be reset by overflow of the watchdog timer. For details, see section 12, Watchdog Timer (WDT). A reset initializes the internal state of the CPU and the registers of the on-chip peripheral modules. The interrupt control mode is 0 immediately after a reset. 4.3.1 Reset Exception Handling When the RES pin goes high after being held low for the necessary time, this LSI starts reset exception handling as follows: 1. The internal state of the CPU and the registers of the on-chip peripheral modules are initialized, VBR is cleared to H'00000000, the T bit is cleared to 0 in EXR, and the I bits are set to 1 in EXR and CCR. 2. The reset exception handling vector address is read and transferred to the PC, and program execution starts from the address indicated by the PC. Figure 4.1 shows an example of the reset sequence. Rev. 2.00 Mar. 15, 2006 Page 72 of 754 REJ09B0199-0200 Section 4 Exception Handling 4.3.2 Interrupts after Reset If an interrupt is accepted after a reset but before the stack pointer (SP) is initialized, the PC and CCR will not be saved correctly, leading to a program crash. To prevent this, all interrupt requests, including NMI, are disabled immediately after a reset. Since the first instruction of a program is always executed immediately after the reset state ends, make sure that this instruction initializes the stack pointer (example: MOV.L #xx: 32, SP). 4.3.3 On-Chip Peripheral Functions after Reset Release After the reset state is released, MSTPCRA, MSTPCRB, and MSTPCRC are initialized to H'0FFF, H'FFFF, and H'FF00 respectively, and all modules except the DMAC and DTC enter module stop mode. Consequently, on-chip peripheral module registers cannot be read from or written to. Register reading and writing is enabled when module stop mode is canceled. First instruction prefetch Vector fetch I Internal operation RES Internal address bus Internal read signal Internal write signal Internal data bus High (1) (3) (2) (4) (1) (2) (3) (4) Reset exception handling vector address (when reset, (1) = H'000000) Start address (contents of reset exception handling vector address) Start address ((3) = (2)) First instruction in the exception handling routine Figure 4.1 Reset Sequence (On-Chip ROM Enabled Advanced Mode) Rev. 2.00 Mar. 15, 2006 Page 73 of 754 REJ09B0199-0200 Section 4 Exception Handling 4.4 Traces Traces are enabled in interrupt control mode 2. Trace mode is not activated in interrupt control mode 0, irrespective of the state of the T bit. Before changing interrupt control modes, the T bit must be cleared to 0. For details on interrupt control modes, see section 5, Interrupt Controller. If the T bit in EXR is set to 1, trace mode is activated. In trace mode, a trace exception occurs on completion of each instruction. Trace mode is not affected by interrupt masking by CCR. Table 4.4 shows the state of CCR and EXR after execution of trace exception handling. Trace mode is canceled by clearing the T bit in EXR to 0 during the trace exception handling. However, the T bit saved on the stack retains its value of 1, and when control is returned from the trace exception handling routine by the RTE instruction, trace mode resumes. Trace exception handling is not carried out after execution of the RTE instruction. Interrupts are accepted even within the trace exception handling routine. Table 4.4 Status of CCR and EXR after Trace Exception Handling CCR Interrupt Control Mode 0 2 I UI I2 to I0 EXR T Trace exception handling cannot be used. 1 0 [Legend] 1: Set to 1 0: Cleared to 0 : Retains the previous value. 4.5 4.5.1 Address Error Address Error Source Instruction fetch, stack operation, data read/write, and single-address transfer shown in table 4.5 may cause an address error. Rev. 2.00 Mar. 15, 2006 Page 74 of 754 REJ09B0199-0200 Section 4 Exception Handling Table 4.5 Bus Cycle and Address Error Bus Cycle Type Bus Master Description Fetches instructions from even addresses Fetches instructions from odd addresses Fetches instructions from areas other than on-chip peripheral module space*1 Fetches instructions from on-chip peripheral module space*1 Fetches instructions from external memory space in single-chip mode Fetches instructions from access reserved area.*2 Address Error No (normal) Occurs No (normal) Occurs Occurs Occurs Instruction fetch CPU Stack operation CPU Accesses stack when the stack pointer value No (normal) is even address Accesses stack when the stack pointer value Occurs is odd Data read/write CPU Accesses word data from even addresses Accesses word data from odd addresses Accesses external memory space in singlechip mode Accesses to reserved area*2 No (normal) No (normal) Occurs Occurs No (normal) No (normal) Occurs Occurs No (normal) Data read/write DTC/DMAC Accesses word data from even addresses Accesses word data from odd addresses Accesses external memory space in singlechip mode Accesses to reserved area*2 Single address transfer DMAC In single address transfer, the device to be accessed with an address is in the external memory space In single address transfer, the device to be accessed with an address is not in the external memory space Occurs Notes: 1. For on-chip peripheral module space, see section 6, Bus Controller (BSC). 2. For the access reserved area, refer to figure 3.1 in section 3.4, Address Map. An address error will not occur when the reserved area from H'FF8000 to H'FF8FFF is accessed. Rev. 2.00 Mar. 15, 2006 Page 75 of 754 REJ09B0199-0200 Section 4 Exception Handling 4.5.2 Address Error Exception Handling When an address error occurs, address error exception handling starts after the bus cycle causing the address error ends and current instruction execution completes. The address error exception handling is as follows: 1. The contents of PC, CCR, and EXR are saved in the stack. 2. The interrupt mask bit is updated and the T bit is cleared to 0. 3. An exception handling vector table address corresponding to the address error is generated, the start address of the exception service routine is loaded from the vector table to PC, and program execution starts from that address. Even though an address error occurs during a transition to an address error exception handling, the address error is not accepted. This prevents an address error from occurring due to stacking for exception handling, thereby preventing infinitive stacking. If the SP contents are not a multiple of 2 when an address error exception handling occurs, the stacked values (PC, CCR, and EXR) are undefined. When an address error occurs, the following is performed to halt the DTC and DMAC. * ERR bit in DICCR of DTC is set to 1 * ERRF bit in DMDR_0 of the DMAC is set to 1 * DTE bits for all the channels of the DMAC are cleared to 0 and the DMAC is forced to halt Table 4.6 shows the states of CCR and EXR after the address error exception handling. Table 4.6 States of CCR and EXR after Address Error Exception Handling CCR Interrupt Control Mode 0 2 I 1 1 UI T 0 EXR I2 to I0 7 [Legend] 1: Set to 1. 0: Cleared to 0. : Retains the previous value. Rev. 2.00 Mar. 15, 2006 Page 76 of 754 REJ09B0199-0200 Section 4 Exception Handling 4.6 4.6.1 Interrupts Interrupt Sources Interrupt sources are NMI, IRQ0 to IRQ15, and on-chip peripheral modules, as shown in table 4.7. Table 4.7 Type NMI IRQ0 to IRQ14 On-chip peripheral module Interrupt Sources Source NMI pin (external input) Pins IRQ0 to IRQ15 (external input) Watchdog timer (WDT) A/D converter 16-bit timer pulse unit (TPU) DMA controller (DMAC) Serial communications interface (SCI) Synchronous serial communication unit (SSU) Number of Sources 1 15 1 2 52 8 8 9 Different vector numbers and vector table offsets are assigned to different interrupt sources. For vector number and vector table offset, refer to table 5.2 in section 5.5, Interrupt Exception Handling Vector Table. 4.6.2 Interrupt Exception Handling Interrupts are controlled by the interrupt controller. The interrupt controller has two interrupt control modes and can assign interrupts other than NMI to eight priority/mask levels to enable multiple-interrupt control. The source to start interrupt exception handling and the vector address differ depending on the product. For details, refer to section 5, Interrupt Controller. The interrupt exception handling is as follows: 1. The contents of PC, CCR, and EXR are saved in the stack. 2. The interrupt mask bit is updated and the T bit is cleared to 0. 3. An exception handling vector table address corresponding to the interrupt source is generated, the start address of the exception service routine is loaded from the vector table to PC, and program execution starts from that address. Rev. 2.00 Mar. 15, 2006 Page 77 of 754 REJ09B0199-0200 Section 4 Exception Handling 4.7 Instruction Exception Handling There are two types of instructions that cause exception handling: trap instruction and illegal instructions. 4.7.1 Trap Instruction Trap instruction exception handling starts when a TRAPA instruction is executed. Trap instruction exception handling can be executed at all times in the program execution state. The trap instruction exception handling is as follows: 1. The contents of PC, CCR, and EXR are saved in the stack. 2. The interrupt mask bit is updated and the T bit is cleared to 0. 3. An exception handling vector table address corresponding to the vector number specified in the TRAPA instruction is generated, the start address of the exception service routine is loaded from the vector table to PC, and program execution starts from that address. A start address is read from the vector table corresponding to a vector number from 0 to 3, as specified in the instruction code. Table 4.8 shows the state of CCR and EXR after execution of trap instruction exception handling. Table 4.8 Status of CCR and EXR after Trap Instruction Exception Handling CCR Interrupt Control Mode 0 2 I 1 1 UI T 0 EXR I2 to I0 [Legend] 1: Set to 1 0: Cleared to 0 : Retains the previous value. Rev. 2.00 Mar. 15, 2006 Page 78 of 754 REJ09B0199-0200 Section 4 Exception Handling 4.7.2 Exception Handling by General Illegal Instruction There are two illegal instructions: general illegal instruction and slot illegal instruction. The exception handling by the general illegal instruction starts when an undefined code is decoded. The exception handling by the slot illegal instruction starts when the following instruction which is placed in a delay slot (immediately after a delayed branch instruction) is executed: an instruction which consists of two words or more or which changes the contents of PC. The general illegal and slot illegal instructions are always executable in the program execution state. The exception handling for the general illegal and a slot illegal instructions is as follows: 1. The contents of PC, CCR, and EXR are saved in the stack. 2. The interrupt mask bit is updated and the T bit is cleared to 0. 3. An exception handling vector table address corresponding to the occurred exception is generated, the start address of the exception service routine is loaded from the vector table to PC, and program execution starts from that address. Table 4.9 shows the state of CCR and EXR after execution of illegal instruction exception handling. Table 4.9 Status of CCR and EXR after Illegal Instruction Exception Handling CCR Interrupt Control Mode 0 2 I 1 1 UI T 0 EXR I2 to I0 [Legend] 1: Set to 1 0: Cleared to 0 : Retains the previous value. Rev. 2.00 Mar. 15, 2006 Page 79 of 754 REJ09B0199-0200 Section 4 Exception Handling 4.8 Stack Status after Exception Handling Figure 4.2 shows the stack after completion of exception handling. Advanced mode SP EXR Reserved* SP CCR PC (24 bits) CCR PC (24 bits) Interrupt control mode 0 Interrupt control mode 2 Note: * Ignored on return. Figure 4.2 Stack Status after Exception Handling 4.9 Usage Note When performing stack-manipulating access, this LSI assumes that the lowest address bit is 0. The stack should always be accessed by a word transfer instruction or a longword transfer instruction, and the value of the stack pointer (SP: ER7) should always be kept even. Use the following instructions to save registers: * PUSH.W Rn (or MOV.W Rn, @-SP) * PUSH.L ERn (or MOV.L ERn, @-SP) Use the following instructions to restore registers: * POP.W Rn (or MOV.W @SP+, Rn) * POP.L ERn (or MOV.L @SP+, ERn) Performing stack manipulation while SP is set to an odd value leads to an address error. Figure 4.3 shows an example of operation when the SP value is odd. Rev. 2.00 Mar. 15, 2006 Page 80 of 754 REJ09B0199-0200 Section 4 Exception Handling Address CCR SP PC SP R1L H'FFFEFA H'FFFEFB PC H'FFFEFC H'FFFEFD H'FFFEFE SP H'FFFEFF TRAPA instruction executed SP set to H'FFFEFF MOV.B R1L, @-ER7 executed Contents of CCR lost Data saved above SP (Address error occurred) [Legend] CCR : PC : R1L : SP : Condition code register Program counter General register R1L Stack pointer Note: This diagram illustrates an example in which the interrupt control mode is 0, in advanced mode. Figure 4.3 Operation when SP Value Is Odd Rev. 2.00 Mar. 15, 2006 Page 81 of 754 REJ09B0199-0200 Section 4 Exception Handling Rev. 2.00 Mar. 15, 2006 Page 82 of 754 REJ09B0199-0200 Section 5 Interrupt Controller Section 5 Interrupt Controller 5.1 Features * Two interrupt control modes Any of two interrupt control modes can be set by means of bits INTM1 and INTM0 in the interrupt control register (INTCR). * Priority can be assigned by the interrupt priority register (IPR) IPR provides for setting interrupt priory. Eight levels can be set for each module for all interrupts except for the interrupt requests listed below. The following six interrupt requests are given priority of 8, therefore they are accepted at all times. NMI General illegal instructions Trace Trap instructions CPU address error DMA address error* * Independent vector addresses All interrupt sources are assigned independent vector addresses, making it unnecessary for the source to be identified in the interrupt handling routine. * 17 external interrupts NMI is the highest-priority interrupt, and is accepted at all times. Rising edge or falling edge detection can be selected for NMI. Falling edge, rising edge, or both edge detection, or level sensing, can be selected for IRQ15 to IRQ0. * DTC and DMAC control DTC and DMAC can be activated by means of interrupts. * CPU priority control function The priority levels can be assigned to the CPU, DTC and DMAC. The priority level of the CPU can be automatically assigned on an exception generation. Priority can be given to the CPU interrupt exception handling over that of the DTC and DMAC transfer. Note: * A DMA address error is generated within the DTC and DMAC. Rev. 2.00 Mar. 15, 2006 Page 83 of 754 REJ09B0199-0200 Section 5 Interrupt Controller A block diagram of the interrupt controller is shown in figure 5.1. INTCR NMIEG INTM1, INTM0 CPU IPR I I2 to I0 CCR EXR NMI input IRQ input NMI input unit IRQ input unit ISR Priority decision unit CPU interrupt request CPU vector ISCR IER SSIER DMAC activation enable DMAC DMAC priority control DMDR Internal interrupt sources WOVI to SSTXI2 Source selector CPU priority DTC activation request DTC vector Activation request clear signal DTC DTCER DTCCR CPUPCR DTC priority control DTC priority Interrupt controller [Legend] INTCR: CPUPCR: ISCR: IER: Interrupt control register CPU priority control register IRQ sense control register IRQ enable register ISR: SSIER: IPR: DTCER: DTCCR: IRQ status register Software standby release IRQ enable register Interrupt priority register DTC enable register DTC control register Figure 5.1 Block Diagram of Interrupt Controller Rev. 2.00 Mar. 15, 2006 Page 84 of 754 REJ09B0199-0200 Section 5 Interrupt Controller 5.2 Input/Output Pins Table 5.1 shows the pin configuration of the interrupt controller. Table 5.1 Name NMI IRQ15 to IRQ0 Pin Configuration I/O Input Input Function Nonmaskable External Interrupt Rising or falling edge can be selected. Maskable External Interrupts Rising, falling, or both edges, or level sensing, can be selected. 5.3 Register Descriptions The interrupt controller has the following registers. * Interrupt control register (INTCR) * CPU priority control register (CPUPCR) * Interrupt priority registers A to G, I, K to O, Q, and R (IPRA to IPRG, IPRI, IPRK to IPRO, IPRQ, and IPRR) * IRQ enable register (IER) * IRQ sense control registers H and L (ISCRH, ISCRL) * IRQ status register (ISR) * Software standby release IRQ enable register (SSIER) Rev. 2.00 Mar. 15, 2006 Page 85 of 754 REJ09B0199-0200 Section 5 Interrupt Controller 5.3.1 Interrupt Control Register (INTCR) INTCR selects the interrupt control mode, and the detected edge for NMI. Bit Bit Name Initial Value R/W 7 -- 0 R 6 -- 0 R 5 INTM1 0 R/W 4 INTM0 0 R/W 3 NMIEG 0 R/W 2 -- 0 R 1 -- 0 R 0 -- 0 R Bit 7, 6 5 4 Bit Name INTM1 INTM0 Initial Value All 0 0 0 R/W R R/W R/W Description Reserved These are read-only bits and cannot be modified. Interrupt Control Select Mode 1 and 0 These bits select either of two interrupt control modes for the interrupt controller. 00: Interrupt control mode 0 Interrupts are controlled by I bit in CCR. 01: Setting prohibited. 10: Interrupt control mode 2 Interrupts are controlled by bits I2 to I0 in EXR, and IPR. 11: Setting prohibited. 3 NMIEG 0 R/W NMI Edge Select Selects the input edge for the NMI pin. 0: Interrupt request generated at falling edge of NMI input 1: Interrupt request generated at rising edge of NMI input 2 to 0 All 0 R Reserved These are read-only bits and cannot be modified. Rev. 2.00 Mar. 15, 2006 Page 86 of 754 REJ09B0199-0200 Section 5 Interrupt Controller 5.3.2 CPU Priority Control Register (CPUPCR) CPUPCR sets whether or not the CPU has priority over the DTC and DMAC. The interrupt exception handling by the CPU can be given priority over that of the DMAC transfer. The priority level of the DTC is set by bits DTCP2 to DTCP0 in CPUPCR. The priority level of the DMAC for each channel is set by the DMAC control register. Bit Bit Name Initial Value R/W 7 CPUPCE 0 R/W 6 DTCP2 0 R/W 5 DTCP1 0 R/W 4 DTCP0 0 R/W 3 IPSETE 0 R/W 2 CPUP2 0 R/(W)* 1 CPUP1 0 R/(W)* 0 CPUP0 0 R/(W)* Note: * When the IPSETE bit is set to 1, the CPU priority is automatically updated, so these bits cannot be modified. Bit 7 Bit Name CPUPCE Initial Value 0 R/W R/W Description CPU Priority Control Enable Controls the CPU priority control function. Setting this bit to 1 enables the CPU priority control over the DMAC. 0: CPU always has the lowest priority 1: CPU priority control enabled 6 5 4 DTCP2 DTCP1 DTCP0 0 0 0 R/W R/W R/W DTC Priority Level 2 to 0 These bits set the DTC priority level. 000: Priority level 0 (lowest) 001: Priority level 1 010: Priority level 2 011: Priority level 3 100: Priority level 4 101: Priority level 5 110: Priority level 6 111: Priority level 7 (highest) Rev. 2.00 Mar. 15, 2006 Page 87 of 754 REJ09B0199-0200 Section 5 Interrupt Controller Bit 3 Bit Name IPSETE Initial Value 0 R/W R/W Description Interrupt Priority Set Enable Controls the function which automatically assigns the interrupt priority level of the CPU. Setting this bit to 1 automatically sets bits CPUP2 to CPUP0 by the CPU interrupt mask bit (I bit in CCR or bits I2 to I0 in EXR). 0: Bits CPUP2 to CPUP0 are not updated automatically 1: The interrupt mask bit value is reflected in bits CPUP2 to CPUP0 2 1 0 CPUP2 CPUP1 CPUP0 0 0 0 R/(W)* CPU Priority Level 2 to 0 R/(W)* These bits set the CPU priority level. When the R/(W)* CPUPCE is set to 1, the CPU priority control function over the DTC and DMAC becomes valid and the priority of CPU processing is assigned in accordance with the settings of bits CPUP2 to CPUP0. 000: Priority level 0 (lowest) 001: Priority level 1 010: Priority level 2 011: Priority level 3 100: Priority level 4 101: Priority level 5 110: Priority level 6 111: Priority level 7 (highest) Note: * When the IPSETE bit is set to 1, the CPU priority is automatically updated, so these bits cannot be modified. Rev. 2.00 Mar. 15, 2006 Page 88 of 754 REJ09B0199-0200 Section 5 Interrupt Controller 5.3.3 Interrupt Priority Registers A to G, I, K to O, and R (IPRA to IPRG, IPRI, IPRK to IPRO, and IPRR) IPR sets priory (levels 7 to 0) for interrupts other than NMI. Setting a value in the range from B'000 to B'111 in the 3-bit groups of bits 14 to 12, 10 to 8, 6 to 4, and 2 to 0 assigns a priority level to the corresponding interrupt. For the correspondence between the interrupt sources and the IPR settings, see table 5.2. Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W 15 -- 0 R 7 -- 0 R 14 IPR14 1 R/W 6 IPR6 1 R/W 13 IPR13 1 R/W 5 IPR5 1 R/W 12 IPR12 1 R/W 4 IPR4 1 R/W 11 -- 0 R 3 -- 0 R 10 IPR10 1 R/W 2 IPR2 1 R/W 9 IPR9 1 R/W 1 IPR1 1 R/W 8 IPR8 1 R/W 0 IPR0 1 R/W Bit 15 14 13 12 Bit Name IPR14 IPR13 IPR12 Initial Value 0 1 1 1 R/W R R/W R/W R/W Description Reserved This is a read-only bit and cannot be modified. Sets the priority level of the corresponding interrupt source. 000: Priority level 0 (lowest) 001: Priority level 1 010: Priority level 2 011: Priority level 3 100: Priority level 4 101: Priority level 5 110: Priority level 6 111: Priority level 7 (highest) 11 0 R Reserved This is a read-only bit and cannot be modified. Rev. 2.00 Mar. 15, 2006 Page 89 of 754 REJ09B0199-0200 Section 5 Interrupt Controller Bit 10 9 8 Bit Name IPR10 IPR9 IPR8 Initial Value 1 1 1 R/W R/W R/W R/W Description Sets the priority level of the corresponding interrupt source. 000: Priority level 0 (lowest) 001: Priority level 1 010: Priority level 2 011: Priority level 3 100: Priority level 4 101: Priority level 5 110: Priority level 6 111: Priority level 7 (highest) 7 6 5 4 IPR6 IPR5 IPR4 0 1 1 1 R R/W R/W R/W Reserved This is a read-only bit and cannot be modified. Sets the priority level of the corresponding interrupt source. 000: Priority level 0 (lowest) 001: Priority level 1 010: Priority level 2 011: Priority level 3 100: Priority level 4 101: Priority level 5 110: Priority level 6 111: Priority level 7 (highest) 3 2 1 0 IPR2 IPR1 IPR0 0 1 1 1 R R/W R/W R/W Reserved This is a read-only bit and cannot be modified. Sets the priority level of the corresponding interrupt source. 000: Priority level 0 (lowest) 001: Priority level 1 010: Priority level 2 011: Priority level 3 100: Priority level 4 101: Priority level 5 110: Priority level 6 111: Priority level 7 (highest) Rev. 2.00 Mar. 15, 2006 Page 90 of 754 REJ09B0199-0200 Section 5 Interrupt Controller 5.3.4 IRQ Enable Register (IER) IER enables or disables interrupt requests IRQ15 to IRQ0. Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W 15 IRQ15E 0 R/W 7 IRQ7E 0 R/W 14 IRQ14E 0 R/W 6 IRQ6E 0 R/W 13 IRQ13E 0 R/W 5 IRQ5E 0 R/W 12 IRQ12E 0 R/W 4 IRQ4E 0 R/W 11 IRQ11E 0 R/W 3 IRQ3E 0 R/W 10 IRQ10E 0 R/W 2 IRQ2E 0 R/W 9 IRQ9E 0 R/W 1 IRQ1E 0 R/W 8 IRQ8E 0 R/W 0 IRQ0E 0 R/W Bit 15 Bit Name IRQ15E Initial Value 0 R/W R/W Description IRQ15 Enable The IRQ15 interrupt request is enabled when this bit is 1. 14 IRQ14E 0 R/W IRQ14 Enable The IRQ14 interrupt request is enabled when this bit is 1. 13 IRQ13E 0 R/W IRQ13 Enable The IRQ13 interrupt request is enabled when this bit is 1. 12 IRQ12E 0 R/W IRQ12 Enable The IRQ12 interrupt request is enabled when this bit is 1. 11 IRQ11E 0 R/W IRQ11 Enable The IRQ11 interrupt request is enabled when this bit is 1. 10 IRQ10E 0 R/W IRQ10 Enable The IRQ10 interrupt request is enabled when this bit is 1. 9 IRQ9E 0 R/W IRQ9 Enable The IRQ9 interrupt request is enabled when this bit is 1. Rev. 2.00 Mar. 15, 2006 Page 91 of 754 REJ09B0199-0200 Section 5 Interrupt Controller Bit 8 7 6 5 4 3 2 1 0 Bit Name IRQ8E IRQ7E IRQ6E IRQ5E IRQ4E IRQ3E IRQ2E IRQ1E IRQ0E Initial Value 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Description IRQ8 Enable The IRQ8 interrupt request is enabled when this bit is 1. IRQ7 Enable The IRQ7 interrupt request is enabled when this bit is 1. IRQ6 Enable The IRQ6 interrupt request is enabled when this bit is 1. IRQ5 Enable The IRQ5 interrupt request is enabled when this bit is 1. IRQ4 Enable The IRQ4 interrupt request is enabled when this bit is 1. IRQ3 Enable The IRQ3 interrupt request is enabled when this bit is 1. IRQ2 Enable The IRQ2 interrupt request is enabled when this bit is 1. IRQ1 Enable The IRQ1 interrupt request is enabled when this bit is 1. IRQ0 Enable The IRQ0 interrupt request is enabled when this bit is 1. Rev. 2.00 Mar. 15, 2006 Page 92 of 754 REJ09B0199-0200 Section 5 Interrupt Controller 5.3.5 IRQ Sense Control Registers H and L (ISCRH and ISCRL) ISCRH and ISCRL select the source that generates an interrupt request on pins IRQ15 to IRQ0. Upon changing the setting of ISCR, IRQnF (n = 15 to 0) in ISR is often set to 1 accidentally through an internal operation. In this case, an interrupt exception handling is executed if an IRQn interrupt request is enabled. In order to prevent such an accidental interrupt from occurring, the setting of ISCR should be changed while the IRQn interrupt is disabled, and then the IRQnF in ISR should be cleared to 0. * ISCRH Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W 15 IRQ15SR 0 R/W 7 IRQ11SR 0 R/W 14 IRQ15SF 0 R/W 6 IRQ11SF 0 R/W 13 IRQ14SR 0 R/W 5 IRQ10SR 0 R/W 12 IRQ14SF 0 R/W 4 IRQ10SF 0 R/W 11 IRQ13SR 0 R/W 3 IRQ9SR 0 R/W 10 IRQ13SF 0 R/W 2 IRQ9SF 0 R/W 9 IRQ12SR 0 R/W 1 IRQ8SR 0 R/W 8 IRQ12SF 0 R/W 0 IRQ8SF 0 R/W * ISCRL Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W 15 IRQ7SR 0 R/W 7 IRQ3SR 0 R/W 14 IRQ7SF 0 R/W 6 IRQ3SF 0 R/W 13 IRQ6SR 0 R/W 5 IRQ2SR 0 R/W 12 IRQ6SF 0 R/W 4 IRQ2SF 0 R/W 11 IRQ5SR 0 R/W 3 IRQ1SR 0 R/W 10 IRQ5SF 0 R/W 2 IRQ1SF 0 R/W 9 IRQ4SR 0 R/W 1 IRQ0SR 0 R/W 8 IRQ4SF 0 R/W 0 IRQ0SF 0 R/W Rev. 2.00 Mar. 15, 2006 Page 93 of 754 REJ09B0199-0200 Section 5 Interrupt Controller * ISCRH Initial Value 0 0 Bit 15, 14 Bit Name IRQ15SR IRQ15SF R/W R/W R/W Description IRQ15 Sense Control Rise IRQ15 Sense Control Fall 00: Interrupt request generated by low level of IRQ15 01: Interrupt request generated at falling edge of IRQ15 10: Interrupt request generated at rising edge of IRQ15 11: Interrupt request generated at both falling and rising edges of IRQ15 13 12 IRQ14SR IRQ14SF 0 0 R/W R/W IRQ14 Sense Control Rise IRQ14 Sense Control Fall 00: Interrupt request generated by low level of IRQ14 01: Interrupt request generated at falling edge of IRQ14 10: Interrupt request generated at rising edge of IRQ14 11: Interrupt request generated at both falling and rising edges of IRQ14 11 10 IRQ13SR IRQ13SF 0 0 R/W R/W IRQ13 Sense Control Rise IRQ13 Sense Control Fall 00: Interrupt request generated by low level of IRQ13 01: Interrupt request generated at falling edge of IRQ13 10: Interrupt request generated at rising edge of IRQ13 11: Interrupt request generated at both falling and rising edges of IRQ13 9 8 IRQ12SR IRQ12SF 0 0 R/W R/W IRQ12 Sense Control Rise IRQ12 Sense Control Fall 00: Interrupt request generated by low level of IRQ12 01: Interrupt request generated at falling edge of IRQ12 10: Interrupt request generated at rising edge of IRQ12 11: Interrupt request generated at both falling and rising edges of IRQ12 7 6 IRQ11SR IRQ11SF 0 0 R/W R/W IRQ11 Sense Control Rise IRQ11 Sense Control Fall 00: Interrupt request generated by low level of IRQ11 01: Interrupt request generated at falling edge of IRQ11 10: Interrupt request generated at rising edge of IRQ11 11: Interrupt request generated at both falling and rising edges of IRQ11 Rev. 2.00 Mar. 15, 2006 Page 94 of 754 REJ09B0199-0200 Section 5 Interrupt Controller Bit 5 4 Bit Name IRQ10SR IRQ10SF Initial Value 0 0 R/W R/W R/W Description IRQ10 Sense Control Rise IRQ10 Sense Control Fall 00: Interrupt request generated by low level of IRQ10 01: Interrupt request generated at falling edge of IRQ10 10: Interrupt request generated at rising edge of IRQ10 11: Interrupt request generated at both falling and rising edges of IRQ10 3 2 IRQ9SR IRQ9SF 0 0 R/W R/W IRQ9 Sense Control Rise IRQ9 Sense Control Fall 00: Interrupt request generated by low level of IRQ9 01: Interrupt request generated at falling edge of IRQ9 10: Interrupt request generated at rising edge of IRQ9 11: Interrupt request generated at both falling and rising edges of IRQ9 1 0 IRQ8SR IRQ8SF 0 0 R/W R/W IRQ8 Sense Control Rise IRQ8 Sense Control Fall 00: Interrupt request generated by low level of IRQ8 01: Interrupt request generated at falling edge of IRQ8 10: Interrupt request generated at rising edge of IRQ8 11: Interrupt request generated at both falling and rising edges of IRQ8 Rev. 2.00 Mar. 15, 2006 Page 95 of 754 REJ09B0199-0200 Section 5 Interrupt Controller * ISCRL Initial Value 0 0 Bit 15 14 Bit Name IRQ7SR IRQ7SF R/W R/W R/W Description IRQ7 Sense Control Rise IRQ7 Sense Control Fall 00: Interrupt request generated by low level of IRQ7 01: Interrupt request generated at falling edge of IRQ7 10: Interrupt request generated at rising edge of IRQ7 11: Interrupt request generated at both falling and rising edges of IRQ7 13 12 IRQ6SR IRQ6SF 0 0 R/W R/W IRQ6 Sense Control Rise IRQ6 Sense Control Fall 00: Interrupt request generated by low level of IRQ6 01: Interrupt request generated at falling edge of IRQ6 10: Interrupt request generated at rising edge of IRQ6 11: Interrupt request generated at both falling and rising edges of IRQ6 11 10 IRQ5SR IRQ5SF 0 0 R/W R/W IRQ5 Sense Control Rise IRQ5 Sense Control Fall 00: Interrupt request generated by low level of IRQ5 01: Interrupt request generated at falling edge of IRQ5 10: Interrupt request generated at rising edge of IRQ5 11: Interrupt request generated at both falling and rising edges of IRQ5 9 8 IRQ4SR IRQ4SF 0 0 R/W R/W IRQ4 Sense Control Rise IRQ4 Sense Control Fall 00: Interrupt request generated by low level of IRQ4 01: Interrupt request generated at falling edge of IRQ4 10: Interrupt request generated at rising edge of IRQ4 11: Interrupt request generated at both falling and rising edges of IRQ4 Rev. 2.00 Mar. 15, 2006 Page 96 of 754 REJ09B0199-0200 Section 5 Interrupt Controller Bit 7 6 Bit Name IRQ3SR IRQ3SF Initial Value 0 0 R/W R/W R/W Description IRQ3 Sense Control Rise IRQ3 Sense Control Fall 00: Interrupt request generated by low level of IRQ3 01: Interrupt request generated at falling edge of IRQ3 10: Interrupt request generated at rising edge of IRQ3 11: Interrupt request generated at both falling and rising edges of IRQ3 5 4 IRQ2SR IRQ2SF 0 0 R/W R/W IRQ2 Sense Control Rise IRQ2 Sense Control Fall 00: Interrupt request generated by low level of IRQ2 01: Interrupt request generated at falling edge of IRQ2 10: Interrupt request generated at rising edge of IRQ2 11: Interrupt request generated at both falling and rising edges of IRQ2 3 2 IRQ1SR IRQ1SF 0 0 R/W R/W IRQ1 Sense Control Rise IRQ1 Sense Control Fall 00: Interrupt request generated by low level of IRQ1 01: Interrupt request generated at falling edge of IRQ1 10: Interrupt request generated at rising edge of IRQ1 11: Interrupt request generated at both falling and rising edges of IRQ1 1 0 IRQ0SR IRQ0SF 0 0 R/W R/W IRQ0 Sense Control Rise IRQ0 Sense Control Fall 00: Interrupt request generated by low level of IRQ0 01: Interrupt request generated at falling edge of IRQ0 10: Interrupt request generated at rising edge of IRQ0 11: Interrupt request generated at both falling and rising edges of IRQ0 Rev. 2.00 Mar. 15, 2006 Page 97 of 754 REJ09B0199-0200 Section 5 Interrupt Controller 5.3.6 IRQ Status Register (ISR) ISR is an IRQ15 to IRQ0 interrupt request register. Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W Note: * 15 IRQ15F 0 R/(W)* 7 IRQ7F 0 R/(W)* 14 IRQ14F 0 R/(W)* 6 IRQ6F 0 R/(W)* 13 IRQ13F 0 R/(W)* 5 IRQ5F 0 R/(W)* 12 IRQ12F 0 R/(W)* 4 IRQ4F 0 R/(W)* 11 IRQ11F 0 R/(W)* 3 IRQ3F 0 R/(W)* 10 IRQ10F 0 R/(W)* 2 IRQ2F 0 R/(W)* 9 IRQ9F 0 R/(W)* 1 IRQ1F 0 R/(W)* 8 IRQ8F 0 R/(W)* 0 IRQ0F 0 R/(W)* Only 0 can be written, to clear the flag. The bit manipulation instructions or memory operation instructions should be used to clear the flag. Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Note: * Bit Name IRQ15F IRQ14F IRQ13F IRQ12F IRQ11F IRQ10F IRQ9F IRQ8F IRQ7F IRQ6F IRQ5F IRQ4F IRQ3F IRQ2F IRQ1F IRQ0F Initial Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* Description [Setting condition] * * * * When the interrupt selected by ISCR occurs Writing 0 after reading IRQnF = 1 When interrupt exception handling is executed when low-level sensing is selected and IRQn input is high When IRQn interrupt exception handling is executed when falling-, rising-, or both-edge sensing is selected When the DTC is activated by an IRQn interrupt, and the DISEL bit in MRB of the DTC is cleared to 0 [Clearing conditions] * Only 0 can be written, to clear the flag. The bit manipulation instructions or memory operation instructions should be used to clear the flag. Rev. 2.00 Mar. 15, 2006 Page 98 of 754 REJ09B0199-0200 Section 5 Interrupt Controller 5.3.7 Software Standby Release IRQ Enable Register (SSIER) SSIER selects pins used to leave software standby mode from pins IRQ15 to IRQ0. The IRQ interrupt used to leave software standby mode should not be set as the DTC activation source. Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W 15 SSI15 0 R/W 7 SSI7 0 R/W 14 SSI14 0 R/W 6 SSI6 0 R/W 13 SSI13 0 R/W 5 SSI5 0 R/W 12 SSI12 0 R/W 4 SSI4 0 R/W 11 SSI11 0 R/W 3 SSI3 0 R/W 10 SSI10 0 R/W 2 SSI2 0 R/W 9 SSI9 0 R/W 1 SSI1 0 R/W 8 SSI8 0 R/W 0 SSI0 0 R/W Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Name SSI15 SSI14 SSI13 SSI12 SSI11 SSI10 SSI9 SSI8 SSI7 SSI6 SSI5 SSI4 SSI3 SSI2 SSI1 SSI0 Initial Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Software Standby Release IRQ Setting These bits select the IRQn pins used to leave software standby mode (n = 15 to 0). 0: IRQn requests are not sampled in software standby mode 1: When an IRQn request occurs in software standby mode, this LSI leaves software standby mode after the oscillation settling time has elapsed Rev. 2.00 Mar. 15, 2006 Page 99 of 754 REJ09B0199-0200 Section 5 Interrupt Controller 5.4 5.4.1 Interrupt Sources External Interrupts There are seventeen external interrupts: NMI and IRQ15 to IRQ0. These interrupts can be used to leave software standby mode. (1) NMI Interrupts Nonmaskable interrupt request (NMI) is the highest-priority interrupt, and is always accepted by the CPU regardless of the interrupt control mode or the settings of the CPU interrupt mask bits. The NMIEG bit in INTCR selects whether an interrupt is requested at the rising or falling edge on the NMI pin. When an NMI interrupt is generated, the interrupt controller determines that an error has occurred, and performs the following procedure. * Sets the ERR bit in DTCCR of the DTC to 1. * Sets the ERRF bit in DMDR_0 to 1. * Clears the DTE bits for all the channels of the DMAC and forcibly halts transfer. (2) IRQn Interrupts An IRQn interrupt is requested by a signal input on pins IRQ15 to IRQ0. IRQn (n = 15 to 0) have the following features: * Using ISCR, it is possible to select whether an interrupt is generated by a low level, falling edge, rising edge, or both edges, on pins IRQn. * Enabling or disabling of interrupt requests IRQn can be selected by IER. * The interrupt priority can be set by IPR. * The status of interrupt requests IRQn is indicated in ISR. ISR flags can be cleared to 0 by software. The bit manipulation instructions or memory operation instructions should be used to clear the flag in ISR. Detection of IRQn interrupts is enabled through the P1ICR, P2ICR, P5ICR, and P6ICR register settings, and does not change regardless of the output setting. However, when a pin is used as an external interrupt input pin, the pin must not be used as an I/O pin for another function by clearing the corresponding DDR bit to 0. Rev. 2.00 Mar. 15, 2006 Page 100 of 754 REJ09B0199-0200 Section 5 Interrupt Controller A block diagram of interrupts IRQn is shown in figure 5.2. IRQnE Corresponding bit in ICR IRQnSF, IRQnSR IRQnF Input buffer IRQn input Edge/level detection circuit IRQn interrupt request S R Q [Legend] n = 15 to 0 Clear signal Figure 5.2 Block Diagram of Interrupts IRQn When the IRQ sensing control in ISCR is set to a low level of signal IRQn, the level of IRQn should be held low until an interrupt handling starts. Then set the corresponding input signal IRQn to high in the interrupt handling routine and clear the IRQnF to 0. Interrupts may not be executed when the corresponding input signal IRQn is set to high before the interrupt handling begins. 5.4.2 Internal Interrupts The sources for internal interrupts from on-chip peripheral modules have the following features: * For each on-chip peripheral module there are flags that indicate the interrupt request status, and enable bits that enable or disable these interrupts. They can be controlled independently. When the enable bit is set to 1, an interrupt request is issued to the interrupt controller. * The interrupt priority can be set by means of IPR. * The DTC and DMAC can be activated by a TPU, SCI, SSU, or other interrupt request. * DTC and DMAC activations can be controlled by the CPU priority control function over the DTC and DMAC. Rev. 2.00 Mar. 15, 2006 Page 101 of 754 REJ09B0199-0200 Section 5 Interrupt Controller 5.5 Interrupt Exception Handling Vector Table Table 5.2 lists interrupt exception handling sources, vector address offsets, and interrupt priority. In the default priority order, a lower vector number corresponds to a higher priority. When interrupt control mode 2 is set, priority levels can be changed by setting the IPR contents. The priority for interrupt sources allocated to the same level in IPR follows the default priority, that is, they are fixed. Table 5.2 Interrupt Sources, Vector Address Offsets, and Interrupt Priority Vector Interrupt Classification Source Vector Number Address Offset* IPR Priority DTC DMAC Activation Activation External pin NMI IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 IRQ8 IRQ9 IRQ10 IRQ11 IRQ12 IRQ13 IRQ14 IRQ15 7 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 H'001C H'0100 H'0104 H'0108 H'010C H'0110 H'0114 H'0118 H'011C H'0120 H'0124 H'0128 H'012C H'0130 H'0134 H'0138 H'013C H'0140 -- IPRA14 to IPRA12 IPRA10 to IPRA8 IPRA6 to IPRA4 IPRA2 to IPRA0 IPRB14 to IPRB12 IPRB10 to IPRB8 IPRB6 to IPRB4 IPRB2 to IPRB0 IPRC14 to IPRC12 IPRC10 to IPRC8 IPRC6 to IPRC4 IPRC2 to IPRC0 IPRD14 to IPRD12 IPRD10 to IPRD8 IPRD6 to IPRD4 IPRD2 to IPRD0 -- High -- O O O O O O O O O O O O O O O O -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Reserved for system use Low Rev. 2.00 Mar. 15, 2006 Page 102 of 754 REJ09B0199-0200 Section 5 Interrupt Controller Vector Interrupt Classification Source Vector Number Address Offset* IPR Priority DTC DMAC Activation Activation WDT -- WOVI Reserved for system use 81 82 83 84 85 H'0144 H'0148 H'014C H'0150 H'0154 H'0158 H'015C H'0160 H'0164 H'0168 H'016C H'0170 H'0174 H'0178 H'017C H'0180 H'0184 H'0188 H'018C H'0190 H'0194 H'0198 H'019C H'01A0 H'01A4 H'01A8 H'01AC H'01B0 H'01B4 IPRE10 to IPRE8 -- High -- -- -- -- -- -- -- -- -- -- O O O -- -- -- -- O -- -- -- O -- -- -- O -- -- -- -- -- -- -- -- A/D_0 A/D_1 TPU_0 ADI0 ADI1 TGI0A TGI0B TGI0C TGI0D TCI0V 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 IPRF10 to IPRF8 O O IPRF6 to IPRF4 O O O O -- TPU_1 TGI1A TGI1B TCI1V TCI1U IPRF2 to IPRF0 O O -- -- TPU_2 TGI2A TGI2B TCI2V TCI2U IPRG14 to IPRG12 O O -- -- TPU_3 TGI3A TGI3B TGI3C TGI3D TCI3V IPRG10 to IPRG8 O O O O -- TPU_4 TGI4A TGI4B TCI4V TCI4U IPRG6 to IPRG4 O O -- Low -- Rev. 2.00 Mar. 15, 2006 Page 103 of 754 REJ09B0199-0200 Section 5 Interrupt Controller Vector Interrupt Classification Source Vector Number Address Offset* IPR Priority DTC DMAC Activation Activation TPU_5 TGI5A TGI5B TCI5V TCI5U 110 111 112 113 114 115 116 117 118 119 120 121 H'01B8 H'01BC H'01C0 H'01C4 H'01C8 H'01CC H'01D0 H'01D4 H'01D8 H'01DC H'01E0 H'01E4 H'01E8 H'01EC H'01F0 H'01F4 H'01F8 H'01FC H'0200 H'0204 H'0208 H'020C H'0210 H'0214 H'0218 H'021C H'0220 H'0224 H'0228 H'022C IPRG2 to IPRG0 High O O -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Reserved for system use -- -- -- -- -- -- -- -- -- -- Reserved for system use 122 123 124 125 126 127 -- -- -- -- -- -- -- DMAC DMTEND0 DMTEND1 DMTEND2 DMTEND3 128 129 130 131 132 133 134 135 IPRI14 to IPRI12 IPRI10 to IPRI8 IPRI6 to IPRI4 IPRI2 to IPRI0 -- O O O O -- -- -- -- -- Reserved for system use DMAC DMEEND0 DMEEND1 DMEEND2 DMEEND3 136 137 138 139 IPRK14 to IPRK12 O O O Low O Rev. 2.00 Mar. 15, 2006 Page 104 of 754 REJ09B0199-0200 Section 5 Interrupt Controller Vector Address Offset* Classification Interrupt Source Vector Number IPR Priority DTC DMAC Activation Activation -- Reserved for system use 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 H'0230 H'0234 H'0238 H'023C H'0240 H'0244 H'0248 H'024C H'0250 H'0254 H'0258 H'025C H'0260 H'0264 H'0268 H'026C H'0270 H'0274 H'0278 H'027C H'0280 H'0284 H'0288 H'028C H'0290 H'0294 H'0298 H'029C H'02A0 -- High -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- O O -- -- O O -- O -- -- -- -- SCI_3 ERI3 RXI3 TXI3 TEI3 156 157 158 159 160 161 162 163 164 165 166 167 168 IPRL10 to IPRL8 -- O O -- SCI_4 ERI4 RXI4 TXI4 TEI4 IPRL6 to IPRL4 -- O O -- TPU_6 TGI6A TGI6B TGI6C TGI6D TCI6V IPRL2 to IPRL0 O O O O IPRM14 to IPRM12 Low -- Rev. 2.00 Mar. 15, 2006 Page 105 of 754 REJ09B0199-0200 Section 5 Interrupt Controller Vector Interrupt Classification Source Vector Number Address Offset* IPR Priority DTC DMAC Activation Activation TPU_7 TGI7A TGI7B TCI7V TCI7U 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 H'02A4 H'02A8 H'02AC H'02B0 H'02B4 H'02B8 H'02BC H'02C0 H'02C4 H'02C8 H'02CC H'02D0 H'02D4 H'02D8 H'02DC H'02E0 H'02E4 H'02E8 H'02EC H'02F0 H'02F4 H'02F8 H'02FC H'0300 H'0304 H'0308 H'030C IPRM10 to IPRM8 High O O O -- -- -- O -- -- -- O -- -- -- -- O -- -- -- -- -- O -- -- -- -- -- -- -- IPRM6 to IPRM4 -- -- TPU_8 TGI8A TGI8B TCI8V TCI8U IPRM2 to IPRM0 O O IPRN14 to IPRN12 -- -- TPU_9 TGI9A TGI9B TGI9C TGI9D TCI9V IPRN10 to IPRN8 O O O O IPRN6 to IPRN4 IPRN2 to IPRN0 -- O O -- -- TPU_10 TGI10A TGI10B Reserved for system use Reserved for system use TCI10V TCI10U IPRO14 to IPRO12 O -- TPU_11 TGI11A TGI11B TCI11V TCI11U IPRO10 to IPRO8 O O IPRO6 to IPRO4 -- -- -- Reserved for system use -- -- -- -- Low -- Rev. 2.00 Mar. 15, 2006 Page 106 of 754 REJ09B0199-0200 Section 5 Interrupt Controller Vector Address Offset* Classification Interrupt Source Vector Number IPR Priority DTC DMAC Activation Activation -- Reserved for system use 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 H'0310 H'0314 H'0318 H'031C H'0320 H'0324 H'0328 H'032C H'0330 H'0334 H'0338 H'033C H'0340 H'0344 H'0348 H'034C H'0350 H'0354 H'0358 H'035C H'0360 H'0364 H'0368 H'036C H'0380 H'0384 H'0388 H'038C H'0390 H'0394 IPRR10 to IPRR8 IPRR14 to IPRR12 High -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- O O SSU_0 Reserved for system use 224 225 226 SSERI0 SSRXI0 SSTXI0 227 228 229 Low -- Rev. 2.00 Mar. 15, 2006 Page 107 of 754 REJ09B0199-0200 Section 5 Interrupt Controller Vector Address Offset* Classification Interrupt Source Vector Number IPR Priority DTC DMAC Activation Activation SSU_1 Reserved for system use SSERI1 SSRXI1 SSTXI1 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 H'0398 H'039C H'03A0 H'03A4 H'03A8 H'03AC H'03B0 H'03B4 H'03B8 H'03BC H'03C0 H'03C4 H'03C8 H'03CC H'03D0 H'03D4 H'03D8 H'03DC H'03E0 H'03E4 H'03E8 H'03EC H'03F0 H'03F4 H'03F8 H'03FC -- IPRR2 to IPRR0 IPRR6 to IPRR4 High -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- O O -- -- O O -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- SSU_2 Reserved for system use SSERI2 SSRXI2 SSTXI2 Reserved for system use -- Reserved for system use Low -- Note: * Lower 16 bits of the start address in advanced mode. Rev. 2.00 Mar. 15, 2006 Page 108 of 754 REJ09B0199-0200 Section 5 Interrupt Controller 5.6 Interrupt Control Modes and Interrupt Operation The interrupt controller has two interrupt control modes: interrupt control mode 0 and interrupt control mode 2. Interrupt operations differ depending on the interrupt control mode. The interrupt control mode is selected by INTCR. Table 5.3 shows the differences between interrupt control mode 0 and interrupt control mode 2. Table 5.3 Interrupt Control Modes Interrupt Mask Bit I Interrupt Priority Setting Control Mode Register 0 Default Description The priority levels of the interrupt sources are fixed default settings. The interrupts except for NMI is masked by the I bit. Eight priority levels can be set for interrupt sources except for NMI with IPR. 8-level interrupt mask control is performed by bits I2 to I0. 2 IPR I2 to I0 5.6.1 Interrupt Control Mode 0 In interrupt control mode 0, interrupt requests except for NMI are masked by the I bit in CCR of the CPU. Figure 5.3 shows a flowchart of the interrupt acceptance operation in this case. 1. If an interrupt request occurs when the corresponding interrupt enable bit is set to 1, the interrupt request is sent to the interrupt controller. 2. If the I bit in CCR is set to 1, only an NMI interrupt is accepted, and other interrupt requests are held pending. If the I bit is cleared to 0, an interrupt request is accepted. 3. For multiple interrupt requests, the interrupt controller selects the interrupt request with the highest priority, sends the request to the CPU, and holds other interrupt requests pending. 4. When the CPU accepts the interrupt request, it starts interrupt exception handling after execution of the current instruction has been completed. 5. The PC and CCR contents are saved to the stack area during the interrupt exception handling. The PC contents saved on the stack is the address of the first instruction to be executed after returning from the interrupt handling routine. 6. Next, the I bit in CCR is set to 1. This masks all interrupts except NMI. Rev. 2.00 Mar. 15, 2006 Page 109 of 754 REJ09B0199-0200 Section 5 Interrupt Controller 7. The CPU generates a vector address for the accepted interrupt and starts execution of the interrupt handling routine at the address indicated by the contents of the vector address in the vector table. Program execution state Interrupt generated? Yes Yes No NMI No I=0 Yes No Pending IRQ0 Yes No IRQ1 Yes No SSTXI2 Yes Save PC and CCR I1 Read vector address Branch to interrupt handling routine Figure 5.3 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 0 Rev. 2.00 Mar. 15, 2006 Page 110 of 754 REJ09B0199-0200 Section 5 Interrupt Controller 5.6.2 Interrupt Control Mode 2 In interrupt control mode 2, interrupt requests except for NMI are masked by comparing the interrupt mask level (I2 to I0 bits) in EXR of the CPU and the IPR setting. There are eight levels in mask control. Figure 5.4 shows a flowchart of the interrupt acceptance operation in this case. 1. If an interrupt request occurs when the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller. 2. For multiple interrupt requests, the interrupt controller selects the interrupt request with the highest priority according to the IPR setting, and holds other interrupt requests pending. If multiple interrupt requests has the same priority, an interrupt request is selected according to the default setting shown in table 5.2. 3. Next, the priority of the selected interrupt request is compared with the interrupt mask level set in EXR. When the interrupt request does not have priority over the mask level set, it is held pending, and only an interrupt request with a priority over the interrupt mask level is accepted. 4. When the CPU accepts an interrupt request, it starts interrupt exception handling after execution of the current instruction has been completed. 5. The PC, CCR, and EXR contents are saved to the stack area during interrupt exception handling. The PC saved on the stack is the address of the first instruction to be executed after returning from the interrupt handling routine. 6. The T bit in EXR is cleared to 0. The interrupt mask level is rewritten with the priority of the accepted interrupt. If the accepted interrupt is NMI, the interrupt mask level is set to H'7. 7. The CPU generates a vector address for the accepted interrupt and starts execution of the interrupt handling routine at the address indicated by the contents of the vector address in the vector table. Rev. 2.00 Mar. 15, 2006 Page 111 of 754 REJ09B0199-0200 Section 5 Interrupt Controller Program execution state Interrupt generated? No Yes Yes NMI No No Level 7 interrupt? Yes Mask level 6 or below? Yes Level 6 interrupt? No Yes No Level 1 interrupt? Mask level 5 or below? Yes Mask level 0? Yes No Yes No No Save PC, CCR, and EXR Pending Clear T bit to 0 Update mask level Read vector address Branch to interrupt handling routine Figure 5.4 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 2 Rev. 2.00 Mar. 15, 2006 Page 112 of 754 REJ09B0199-0200 5.6.3 Interrupt acceptance Instruction prefetch Internal operation Stack Vector fetch Instruction prefetch Internal in interrupt handling operation routine Interrupt level determination Wait for end of instruction I Interrupt request signal Internal address bus (1) (3) (5) (7) (9) (11) Interrupt Exception Handling Sequence Internal read signal Internal write signal (2) (4) (6) (8) (10) (12) Figure 5.5 shows the interrupt exception handling sequence. The example is for the case where interrupt control mode 0 is set in maximum mode, and the program area and stack area are in onchip memory. Figure 5.5 Interrupt Exception Handling (6) (8) (9) (10) (11) (12) Saved PC and saved CCR Vector address Start address of interrupt handling routine (vector address contents) Start address of Interrupt handling routine ((11) = (10)) First instruction of interrupt handling routine Internal data bus (1) Rev. 2.00 Mar. 15, 2006 Page 113 of 754 Instruction prefetch address (Not executed. This is the contents of the saved PC, the return address.) (2) (4) Instruction code (Not executed.) (3) Instruction prefetch address (Not executed.) (5) SP - 2 (7) SP - 4 Section 5 Interrupt Controller REJ09B0199-0200 Section 5 Interrupt Controller 5.6.4 Interrupt Response Times Table 5.4 shows interrupt response times - the interval between generation of an interrupt request and execution of the first instruction in the interrupt handling routine. The symbols for execution states used in table 5.4 are explained in table 5.5. This LSI is capable of fast word transfer to on-chip memory, so allocating the program area in onchip ROM and the stack area in on-chip RAM enables high-speed processing. Table 5.4 Interrupt Response Times Normal Mode* Interrupt Control Mode 0 1 5 Advanced Mode Interrupt Control Mode 0 3 1 to 19 + 2*SI Interrupt Control Mode 2 Maximum Mode Interrupt Control Mode 0 5 Execution State Interrupt priority decision* Interrupt Control Mode 2 Interrupt Control Mode 2 Number of states until executing 2 instruction ends* PC, CCR, EXR stacking Vector fetch Instruction fetch* 3 SK to 2*SK* 6 2*SK SK to 2*SK* 6 2*SK 2*SK 2*SK Sh 2*SI 4 Internal processing* 2 10 to 31 11 to 31 10 to 31 11 to 31 11 to 31 11 to 31 Total (using on-chip memory) Notes: 1. 2. 3. 4. 5. 6. Two states for an internal interrupt. In the case of the MULXS or DIVXS instruction Prefetch after interrupt acceptance or for an instruction in the interrupt handling routine. Internal operation after interrupt acceptance or after vector fetch Not available in this LSI. When setting the SP value to 4n, the interrupt response time is SK; when setting to 4n + 2, the interrupt response time is 2*SK. Rev. 2.00 Mar. 15, 2006 Page 114 of 754 REJ09B0199-0200 Section 5 Interrupt Controller Table 5.5 Number of Execution States in Interrupt Handling Routine Object of Access External Device 8-Bit Bus 16-Bit Bus 2-State Access 4 2 4 3-State Access 6 + 2m 3+m 6 + 2m 32-Bit Bus 2-State Access 2 2 2 3-State Access 3+m 3+m 3+m Symbol Vector fetch Sh Instruction fetch SI Stack manipulation SK On-Chip 2-State Memory Access 1 1 2 8 4 8 3-State Access 12 + 4m 6 + 2m 12 + 4m [Legend] m: Number of wait cycles in an external device access. 5.6.5 DTC and DMAC Activation by Interrupt The DTC and DMAC can be activated by an interrupt. In this case, the following options are available: * * * * Interrupt request to the CPU Interrupt request to the DTC Activation request to the DMAC Combination of the above For details on interrupt requests that can be used to activate the DMAC, see table 5.2 and section 7, DMA Controller (DMAC), and section 8, Data Transfer Controller (DTC). Figure 5.6 shows a block diagram of the DTC, DMAC, and interrupt controller. Rev. 2.00 Mar. 15, 2006 Page 115 of 754 REJ09B0199-0200 Section 5 Interrupt Controller Interrupt request On-chip peripheral Interrupt request clear signal module DMAC select circuit Select signal DMRSR0 TO DMRSR3 Control signal DMAC activation request signal DMAC request clear signal DMAC Interrupt request IRQ interrupt Interrupt request clear signal CPU select circuit CPU interrupt request vector number Priority decision I, I2 to I0 CPU Interrupt controller Figure 5.6 Block Diagram of DMAC and Interrupt Controller (1) Selection of Interrupt Sources The activation source for each DMAC channel is selected by DMRSR. The selected activation source is input to the DMAC through the select circuit. When transfer by an on-chip module interrupt is enabled (DTF1 = 1, DTF0 = 0, and DTE = 1 in DMDR) and the DTA bit in DMDR is set to 1, the interrupt source selected for the DMAC activation source is controlled by the DMAC and cannot be used as a DTC activation source or CPU interrupt source. Interrupt sources that are not controlled by the DMAC are set for DTC activation sources or CPU interrupt sources by the DTCE bit in DTCERA to DTCERH of the DTC. Specifying the DISEL bit in MRB of the DTC generates an interrupt request to the CPU by clearing the DTCE bit to 0 after the individual DTC data transfer. Note that when the DTC performs a predetermined number of data transfers and the transfer counter indicates 0, an interrupt request is made to the CPU by clearing the DTCE bit to 0 after the DTC and DMAC data transfer. When the same interrupt source is set as both the DTC and DMAC activation source and CPU interrupt source, the DTC and DMAC must be given priority over the CPU. If the IPSETE bit in CPUPCR is set to 1, the priority is determined according to the IPR setting. Therefore, the CPUP setting or the IPR setting corresponding to the interrupt source must be set to lower than or equal to the DTCP and DMAP settings. If the CPU is given priority, the DTC and DMAC may not be activated and the data transfer may be performed. Rev. 2.00 Mar. 15, 2006 Page 116 of 754 REJ09B0199-0200 Section 5 Interrupt Controller (2) Priority Determination The DTC activation source is selected according to the default priority, and the selection is not affected by its mask level or priority level. For respective priority levels, see table 8.1, Interrupt Sources, DTC Vector Addresses, and Corresponding DTCEs. (3) Operation Order If the same interrupt is selected as both the DTC activation source and CPU interrupt source, the CPU interrupt exception handling is performed after the DTC data transfer. If the same interrupt is selected as the DTC or DMAC activation source or CPU interrupt source, respective operations are performed independently. Table 5.6 lists the selection of DMAC activation sources and the selection of interrupt sources and interrupt source clear control by means of the setting of the DTA bit in DMDR of the DMAC, the DTCE bit in DTCERA to DTCERH of the DTC, and the DISEL bit in MRB of the DTC. Table 5.6 Interrupt Source Selection and Clear Control DTC Setting DTCE 0 1 DISEL * 0 1 1 * * Interrupt Source Selection/Clear Control DMAC O O O DTC X O X CPU X X DMAC Setting DTA 0 [Legend] : The corresponding interrupt is used. The interrupt source is cleared. (The interrupt source flag must be cleared in the CPU interrupt handling routine.) O: The corresponding interrupt is used. The interrupt source is not cleared. X: The corresponding interrupt is not available. *: Don't care. (4) Usage Note The interrupt sources of the SCI, A/D converter, and SSU are cleared according to the setting shown in table 5.6, when the DTC or DMAC reads/writes the prescribed register. To initiate multiple channels for the DTC and DMAC with the same interrupt, the same priority (DTCP = DMAP) should be assigned. Rev. 2.00 Mar. 15, 2006 Page 117 of 754 REJ09B0199-0200 Section 5 Interrupt Controller 5.7 CPU Priority Control Function Over DTC and DMAC The interrupt controller has a function to control the priority among the DTC, DMAC, and the CPU by assigning priority levels to the DTC, DMAC, and CPU. Since the priority level can automatically be assigned to the CPU on an interrupt occurrence, it is possible to execute the CPU interrupt exception handling prior to the DTC or DMAC transfer. The priority level of the CPU is assigned by bits CPUP2 to CPUP0 in CPUPCR. The priority level of the DMAC is assigned to each channel by bits DMAP2 to DMAP0 in the DMA mode control registers 0 to 3 (DMDR_0 to DMDR_3). The priority control function over the DTC and DMAC is enabled by setting the CPUPCE bit in CPUPCR to 1. When the CPUPCE bit is 1, the DTC and DMAC activation source is controlled according to the respective priority level. The DTC activation source is controlled according to the priority level of the CPU indicated by bits CPUP2 to CPUP0 and the priority level of the DTC indicated by bits DTCP2 to DTCP0. If the CPU has priority, the DTC activation source is held. The DTC is activated when the condition by which the activation source is held is cancelled (CPUCPCE = 1 and value of bits CPUP2 to CPUP0 is greater than that of bits DTCP2 to DTCP0). The priority level of the DTC is assigned by the DTCP2 to DTCP0 bits regardless of the activation source. The priority level of the DMAC can be specified for each channel. The DMAC activation source is controlled according to the priority level of the CPU and the priority level of the DMAC indicated by bits DMAP2 to DMAP0. If the CPU has priority, the DMAC activation source is held. The DMAC is activated when the condition by which the activation source is held is cancelled (CPUCPCE = 1 and value of bits CPUP2 to CPUP0 is greater than that of bits DMAP2 to DMAP0). When the different priority levels of the DMAC are assigned for the channels, the channel having higher priority continues to transfer while the channel having lower priority than the CPU is held. There are two methods for assigning the priority level to the CPU by the IPSETE bit in CPUPCR. Setting the IPSETE bit to 1 enables a function to automatically assign the value of the interrupt mask bit of the CPU to the CPU priority level. Clearing the IPSETE bit to 0 disables the function to automatically assign the priority level. Therefore, the priority level is assigned directly by software rewriting bits CPUP2 to CPUP0. Even if the IPSETE bit is 1, the priority level of the CPU is software assignable by rewriting the interrupt mask bit of the CPU (I bit in CCR or I2 to I0 bits in EXR). The priority level which is automatically assigned when the IPSETE bit is 1 differs according to the interrupt control mode. Rev. 2.00 Mar. 15, 2006 Page 118 of 754 REJ09B0199-0200 Section 5 Interrupt Controller In interrupt control mode 0, the I bit in CCR of the CPU is reflected in bit CPUP2. Bits CPUP1 and CPUP0 are fixed 0. In interrupt control mode 2, the values of bits I2 to I0 in EXR of the CPU are reflected in bits CPUP2 to CPUP0. Table 5.7 shows the CPU priority control. Table 5.7 CPU Priority Control Control Status Interrupt Mask Bit I = any I=0 I=1 2 IPR setting I2 to I0 0 1 IPSETE in CPUPCR CPUP2 to CPUP0 0 1 B'111 to B'000 B'000 B'100 B'111 to B'000 I2 to I0 Enabled Disabled Updating of CPUP2 to CPUP0 Enabled Disabled Interrupt Control Interrupt Mode Priority 0 Default Table 5.8 shows a setting example of the priority control function over the DTC and DMAC and the transfer request control state. Although the DMAC priority levels can be assigned for each channel, table 5.8 gives a single channel description. Thus, transfer for each channel can be performed independently by assigning the different priority levels. Rev. 2.00 Mar. 15, 2006 Page 119 of 754 REJ09B0199-0200 Section 5 Interrupt Controller Table 5.8 Example of Priority Control Function Setting and Control State Transfer Request Control State DTC DMAC Interrupt CPUPCE in Control Mode CPUPCR CPUP2 to CPUP0 DTCP2 to DTCP0 DMAP2 to DMAP0 0 0 1 Any B'000 B'100 B'100 B'100 B'000 Any B'000 B'000 B'000 B'111 B'111 Any B'000 B'011 B'011 B'011 B'011 B'011 B'011 B'011 B'110 Any B'000 B'000 B'011 B'101 B'101 Any B'000 B'101 B'101 B'101 B'101 B'101 B'101 B'101 B'101 Enabled Enabled Masked Masked Enabled Enabled Enabled Enabled Enabled Enabled Masked Masked Masked Masked Masked Enabled Enabled Enabled Masked Masked Enabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled Masked Masked Enabled Enabled 2 0 1 Any B'000 B'000 B'011 B'100 B'101 B'110 B'111 B'101 B'101 Rev. 2.00 Mar. 15, 2006 Page 120 of 754 REJ09B0199-0200 Section 5 Interrupt Controller 5.8 5.8.1 Usage Notes Conflict between Interrupt Generation and Disabling When an interrupt enable bit is cleared to 0 to mask the interrupt, the masking becomes effective after execution of the instruction. When an interrupt enable bit is cleared to 0 by an instruction such as BCLR or MOV, if an interrupt is generated during execution of the instruction, the interrupt concerned will still be enabled on completion of the instruction, and so interrupt exception handling for that interrupt will be executed on completion of the instruction. However, if there is an interrupt request with priority over that interrupt, interrupt exception handling will be executed for the interrupt with priority, and another interrupt will be ignored. The same also applies when an interrupt source flag is cleared to 0. Figure 5.7 shows an example in which the TCIEV bit in TIER of the TPU is cleared to 0. The above conflict will not occur if an enable bit or interrupt source flag is cleared to 0 while the interrupt is masked. TIER_0 write cycle by CPU TCIV exception handling Internal address bus TIER_0 address Internal write signal TCIEV TCFV TCIV interrupt signal Figure 5.7 Conflict between Interrupt Generation and Disabling Rev. 2.00 Mar. 15, 2006 Page 121 of 754 REJ09B0199-0200 Section 5 Interrupt Controller Similarly, when an interrupt is requested immediately before the DTC enable bit is changed to activate the DTC, DTC activation and the interrupt exception handling by the CPU are both executed. When changing the DTC enable bit, make sure that an interrupt is not requested. 5.8.2 Instructions that Disable Interrupts Instructions that disable interrupts immediately after execution are LDC, ANDC, ORC, and XORC. After any of these instructions is executed, all interrupts including NMI are disabled and the next instruction is always executed. When the I bit is set by one of these instructions, the new value becomes valid two states after execution of the instruction ends. 5.8.3 Times when Interrupts are Disabled There are times when interrupt acceptance is disabled by the interrupt controller. The interrupt controller disables interrupt acceptance for a 3-state period after the CPU has updated the mask level with an LDC, ANDC, ORC, or XORC instruction, and for a period of writing to the registers of the interrupt controller. 5.8.4 Interrupts during Execution of EEPMOV Instruction Interrupt operation differs between the EEPMOV.B and the EEPMOV.W instructions. With the EEPMOV.B instruction, an interrupt request (including NMI) issued during the transfer is not accepted until the transfer is completed. With the EEPMOV.W instruction, if an interrupt request is issued during the transfer, interrupt exception handling starts at the end of the individual transfer cycle. The PC value saved on the stack in this case is the address of the next instruction. Therefore, if an interrupt is generated during execution of an EEPMOV.W instruction, the following coding should be used. L1: EEPMOV.W MOV.W BNE R4,R4 L1 Rev. 2.00 Mar. 15, 2006 Page 122 of 754 REJ09B0199-0200 Section 5 Interrupt Controller 5.8.5 Interrupts during Execution of MOVMD and MOVSD Instructions With the MOVMD and MOVSD instructions, if an interrupt request is issued during the transfer, interrupt exception handling starts at the end of the individual transfer cycle. The PC value saved on the stack in this case is the address of the MOVMD or MOVSD instruction. The transfer of the remaining data is resumed after returning from the interrupt handling routine. 5.8.6 Interrupt Flags of Peripheral Modules To clear an interrupt request flag of a peripheral module by the CPU, the flag must be read from after being cleared within the interrupt handling routine even if the peripheral module clock is not generated by dividing the system clock. This makes the request signal synchronized with the system clock. Rev. 2.00 Mar. 15, 2006 Page 123 of 754 REJ09B0199-0200 Section 5 Interrupt Controller Rev. 2.00 Mar. 15, 2006 Page 124 of 754 REJ09B0199-0200 Section 6 Bus Controller (BSC) Section 6 Bus Controller (BSC) This LSI has an on-chip bus controller (BSC) that has a bus arbitration function and controls the operation of the internal bus masters; CPU, DMAC, and DTC. 6.1 Features * Write data buffer function Write access to an on-chip peripheral module and access to the on-chip memory can be performed in parallel. * Bus arbitration function Includes a bus arbiter that arbitrates bus mastership between the CPU and DMAC. Bus mastership can be shared between the CPU, DMAC, and DTC when a conflict occurs. * Multi-clock function On-chip peripheral functions can be synchronized with the on-chip peripheral module clock (P). A block diagram of the bus controller is shown in figure 6.1. Internal bus control signals CPU bus mastership acknowledge signal DTC bus mastership acknowledge signal DMAC bus mastership acknowledge signal CPU bus mastership request signal DTC bus mastership request signal DMAC bus mastership request signal Internal bus control unit Internal bus arbiter Control register Internal data bus BCR2 [Legend] BCR2: Bus control register 2 Figure 6.1 Block Diagram of Bus Controller Rev. 2.00 Mar. 15, 2006 Page 125 of 754 REJ09B0199-0200 Section 6 Bus Controller (BSC) 6.2 Register Descriptions The bus controller has the following registers. * Bus control register 2 (BCR2) 6.2.1 Bus Control Register 2 (BCR2) BCR2 is used for bus arbitration control of the CPU, DMAC, and DTC, and enabling/disabling of the write data buffer function to the peripheral device. Bit Bit Name Initial Value R/W 7 -- 0 R 6 -- 0 R 5 -- 0 R/W 4 IBCCS 0 R/W 3 -- 0 R 2 -- 0 R 1 -- 1 R/W 0 PWDBE 0 R/W Bit 7, 6 5 Bit Name Initial Value All 0 0 R/W R R/W Description Reserved These are read-only bits and cannot be modified. Reserved This bit is always read as 0. The write value should always be 0. 4 IBCCS 0 R/W Internal Bus Cycle Control Select Selects the internal bus arbiter function. 0: Releases the bus mastership according to the priority 1: Executes the bus cycles alternatively when a CPU bus mastership request conflicts with a DMAC or DTC bus mastership request 3, 2 1 All 0 1 R R/W Reserved These are read-only bits and cannot be modified. Reserved This bit is always read as 1. The write value should always be 1. Rev. 2.00 Mar. 15, 2006 Page 126 of 754 REJ09B0199-0200 Section 6 Bus Controller (BSC) Bit 0 Bit Name PWDBE Initial Value 0 R/W R/W Description Peripheral Module Write Data Buffer Enable Specifies whether or not to use the write data buffer function for the peripheral module write cycles. 0: Write data buffer function not used 1: Write data buffer function used 6.3 Bus Configuration Figure 6.2 shows the internal bus configuration of this LSI. The internal bus of this LSI consists of the following two types. * Internal system bus 1 A bus that connects the CPU, DTC, DMAC, on-chip ROM, on-chip RAM, and internal peripheral bus. * Internal peripheral bus A bus that accesses registers in the DMAC, bus controller and interrupt controller and registers of peripheral modules such as SCI and timer. I synchronization CPU DTC On-chip RAM On-chip ROM Internal system bus 1 Write data buffer Bus controller, interrupt controller, power-down controller DMAC Internal peripheral bus P synchronization Peripheral functions Figure 6.2 Internal Bus Configuration Rev. 2.00 Mar. 15, 2006 Page 127 of 754 REJ09B0199-0200 Section 6 Bus Controller (BSC) 6.4 Multi-Clock Function The internal functions of this LSI operate synchronously with the system clock (I) or the peripheral module clock (P). Table 6.1 shows the synchronization clock and their corresponding functions. Table 6.1 Synchronization Clocks and Their Corresponding Functions Function Name MCU operating mode Interrupt controller Bus controller CPU DTC DMAC Internal memory Clock pulse generator Power down control I/O ports TPU PPG WDT SCI SSU A/D Synchronization Clock I P The frequency of each synchronization clock (I and P) is specified by the system clock control register (SCKCR) independently. For further details, see section 18, Clock Pulse Generator. Rev. 2.00 Mar. 15, 2006 Page 128 of 754 REJ09B0199-0200 Section 6 Bus Controller (BSC) 6.5 6.5.1 Internal Bus Access to Internal Address Space The internal address spaces of this LSI are the on-chip ROM space, on-chip RAM space and register space for the on-chip peripheral modules. The number of cycles necessary for access differs according the space. Table 6.2 shows the number of access cycles for each on-chip memory space. Table 6.2 Number of Access Cycles for On-Chip Memory Spaces Access Read Read Write Number of Access Cycles One I cycle One I cycle Two I cycles Access Space On-chip ROM space On-chip RAM space In access to the registers for on-chip peripheral modules, the number of access cycles differs according to the register to be accessed. When the dividing ratio of the operating clock of a bus master and that of a peripheral module is 1 : n, synchronization cycles using a clock divided by 0 to n-1 are inserted for register access. Table 6.3 Number of Access Cycles for Registers of On-Chip Peripheral Modules Number of Cycles Module to be Accessed DMAC registers MCU operating mode, clock pulse generator, power-down control, interrupt controller, and bus controller registers I/O port PFCR registers and WDT registers TPU, PPG, SCI, and A/D registers and I/O port registers other than PFCR SSU registers 2I Read Write 2I 3I Write Data Buffer Function Disabled Disabled 2P 3P 2P 3P Disabled Enabled Enabled Rev. 2.00 Mar. 15, 2006 Page 129 of 754 REJ09B0199-0200 Section 6 Bus Controller (BSC) 6.6 6.6.1 Write Data Buffer Function Write Data Buffer Function for Peripheral Module This LSI has a write data buffer function for the peripheral module. Using the write data buffer function enables external writes and on-chip memory accesses in parallel. The write data buffer function is made available by setting the PWDBE bit in BCR2 to 1. Figure 6.3 shows an example of the timing when the write data buffer function is used. When this function is used, if a peripheral module write continues for two cycles or longer, and there is an internal access next, only the peripheral modulewrite is executed in the first two cycles. However, from the next cycle onward, on-chip memory accesses and the external address space write rather than waiting until it ends are executed in parallel. On-chip memory read Peripheral module write I Internal address bus P Internal peripheral address bus Internal peripheral data bus Peripheral module address Figure 6.3 Example of Timing when Write Data Buffer Function is Used Rev. 2.00 Mar. 15, 2006 Page 130 of 754 REJ09B0199-0200 Section 6 Bus Controller (BSC) 6.7 Bus Arbitration This LSI has bus arbiters that arbitrate bus mastership operations (bus arbitration). The internal bus arbiter handles the CPU, DTC, and DMAC accesses. The bus arbiters decide priority at the prescribed timing, and permit use of the bus by means of the bus request acknowledge signal. 6.7.1 Operation The bus arbiter detects the bus masters' bus request signals, and if the bus is requested, sends a bus request acknowledge signal to the bus master. If there are bus requests from more than one bus master, the bus request acknowledge signal is sent to the one with the highest priority. When a bus master receives the bus request acknowledge signal, it takes possession of the bus until that signal is canceled. The priority of the internal bus arbitration: (High) DMAC > DTC > CPU (Low) If the DMAC or DTC accesses continue, the CPU can be given priority over the DMAC and DTC to execute the bus cycles alternatively between DMAC or DTC by setting the IBCCS bit in BCR2. In this case, the priority between the DMAC and DTC does not change. 6.7.2 Bus Transfer Timing Even if a bus request is received from a bus master with a higher priority over that of the bus master that has taken control of the bus and is currently operating, the bus is not necessarily transferred immediately. There are specific timings at which each bus master can release the bus. (1) CPU The CPU is the lowest-priority bus master, and if a bus request is received from the DMAC or DTC, the bus arbiter transfers the bus to the bus master that issued the request. The timing for transfer of the bus is at the end of the bus cycle. In sleep mode, the bus is transferred synchronously with the clock. Rev. 2.00 Mar. 15, 2006 Page 131 of 754 REJ09B0199-0200 Section 6 Bus Controller (BSC) Note, however, that the bus cannot be transferred in the following cases. * The word or longword access is performed in some divisions. * Stack handling is performed in multiple bus cycles. * Transfer data read or write by memory transfer instructions, block transfer instructions, or TAS instruction. (In the block transfer instructions, the bus can be transferred in the write cycle and the following transfer data read cycle.) * From the target read to write in the bit manipulation instructions or memory operation instructions. (In an instruction that performs no write operation according to the instruction condition, up to a cycle corresponding the write cycle) (2) DTC The DTC sends the internal bus arbiter a request for the bus when an activation request is generated. When the DTC accesses an external bus space, the DTC first takes control of the bus from the internal bus arbiter and then requests a bus to the external bus arbiter. Once the DTC takes control of the bus, the DTC continues the transfer processing cycles. If a bus master whose priority is higher than the DTC requests the bus, the DTC transfers the bus to the higher priority bus master. If the IBCSS bit in BCR2 is set to 1, the DTC transfers the bus to the CPU. Note, however, that the bus cannot be transferred in the following cases. * During transfer information read * During the first data transfer * During transfer information write back The DTC releases the bus when the consecutive transfer cycles completed. Rev. 2.00 Mar. 15, 2006 Page 132 of 754 REJ09B0199-0200 Section 6 Bus Controller (BSC) (3) DMAC The DMAC sends the internal bus arbiter a request for the bus when an activation request is generated. Once the DMAC takes control of the bus, it continues the transfer processing cycles, or releases the bus every transfer cycle. The bus cannot be transferred in the following cases. * Between a read cycle and the corresponding write cycle in dual address mode While the IBCCS bit in BCR2 is cleared to 0, the bus cannot be transferred in the following cases. * During 1-block data transfer in block transfer mode * During burst access transfer The DMAC releases the bus when the consecutive transfer cycles completed except the above cycles. 6.8 Bus Controller Operation in Reset In a reset, this LSI, including the bus controller, enters the reset state immediately, and any executing bus cycle is aborted. 6.9 (1) Usage Notes All-Module-Clock-Stop Mode In this LSI, if the ACSE bit in MSTPCR is set to 1 with the setting for all peripheral module clocks to be stopped (MSTPCR = H'FFFFFFFF), a transition is made to the all-module-clock-stop mode. For details, see section 19, Power-Down Modes. Rev. 2.00 Mar. 15, 2006 Page 133 of 754 REJ09B0199-0200 Section 6 Bus Controller (BSC) Rev. 2.00 Mar. 15, 2006 Page 134 of 754 REJ09B0199-0200 Section 7 DMA Controller (DMAC) Section 7 DMA Controller (DMAC) This LSI includes a 4-channel DMA controller (DMAC). 7.1 Features * Maximum of 4-G byte address space can be accessed * Byte, word, or longword can be set as data transfer unit * Maximum of 4-G bytes (4,294,967,295 bytes) can be set as total transfer size Supports free-running mode in which total transfer size setting is not needed * DMAC activation methods are auto-request, on-chip module interrupt, and external request. Auto request: CPU activates (cycle stealing or burst access can be selected) On-chip module interrupt: Interrupt requests from on-chip peripheral modules can be selected as an activation source External request*: Low level or falling edge detection of the DREQ signal can be selected (external request is available for all four channels) * Dual or single address mode can be selected as address mode Dual address mode: Both source and destination are specified by addresses Single address mode*: Either source or destination is specified by the DREQ signal and the other is specified by address * Normal, repeat, or block transfer can be selected as transfer mode Normal transfer mode: One byte, one word, or one longword data is transferred at a single transfer request Repeat transfer mode: One byte, one word, or one longword data is transferred at a single transfer request Repeat size of data is transferred and then a transfer address returns to the transfer start address Up to 65536 transfers (65,536 bytes/words/longwords) can be set as repeat size Block transfer mode: One block data is transferred at a single transfer request Up to 65,536 bytes/words/longwords can be set as block size * Extended repeat area function which repeats the addressees within a specified area using the transfer address with the fixed upper bits (ring buffer transfer can be performed, as an example) is available One bit (two bytes) to 27 bits (128 Mbytes) for transfer source and destination can be set as extended repeat areas Rev. 2.00 Mar. 15, 2006 Page 135 of 754 REJ09B0199-0200 Section 7 DMA Controller (DMAC) * Address update can be selected from fixed address, offset addition, and increment or decrement by 1, 2, or 4 Address update by offset addition enables to transfer data at addresses which are not placed continuously * Word or longword data can be transferred to an address which is not aligned with the respective boundary Data is divided according to its address (byte or word) when it is transferred * Two types of interrupts can be requested to the CPU A transfer end interrupt is generated after the number of data specified by the transfer counter is transferred. A transfer escape end interrupt is generated when the remaining total transfer size is less than the transfer data size at a single transfer request, when the repeat size of data transfer is completed, or when the extended repeat area overflows. Note: * An external request and single address mode are not supported by the H8SX/1582. Rev. 2.00 Mar. 15, 2006 Page 136 of 754 REJ09B0199-0200 Section 7 DMA Controller (DMAC) A block diagram of the DMAC is shown in figure 7.1. Internal address bus External pins DREQn* DACKn* TENDn* Interrupt signals requested to the CPU by each channel Internal activation sources ... Controller Address buffer Operation unit Operation unit DOFR_n DSAR_n Internal activation source detector DMDR_n DMRSR_n DACR_n DDAR_n DTCR_n DBSR_n Internal data bus Data buffer Module data bus [Legend] DSAR_n: DMA source address register DREQn: DMA transfer request DDAR_n: DMA destination address register DACKn: DMA transfer acknowledge DOFR_n: DMA offset register TENDn: DMA transfer end DTCR_n: DMA transfer count register n = 0 to 3 DBSR_n: DMA block size register DMDR_n: DMA mode control register DACR_n: DMA address control register DMRSR_n: DMA module request select register Note: * Auto request activation and single address mode are not supported by the H8SX/1582. Figure 7.1 Block Diagram of DMAC Rev. 2.00 Mar. 15, 2006 Page 137 of 754 REJ09B0199-0200 Section 7 DMA Controller (DMAC) 7.2 Register Descriptions The DMAC has the following registers. Channel 0: * * * * * * * * DMA source address register_0 (DSAR_0) DMA destination address register_0 (DDAR_0) DMA offset register_0 (DOFR_0) DMA transfer count register_0 (DTCR_0) DMA block size register_0 (DBSR_0) DMA mode control register_0 (DMDR_0) DMA address control register_0 (DACR_0) DMA module request select register_0 (DMRSR_0) Channel 1: * * * * * * * * DMA source address register_1 (DSAR_1) DMA destination address register_1 (DDAR_1) DMA offset register_1 (DOFR_1) DMA transfer count register_1 (DTCR_1) DMA block size register_1 (DBSR_1) DMA mode control register_1 (DMDR_1) DMA address control register_1 (DACR_1) DMA module request select register_1 (DMRSR_1) Channel 2: * * * * * * * * DMA source address register_2 (DSAR_2) DMA destination address register_2 (DDAR_2) DMA offset register_2 (DOFR_2) DMA transfer count register_2 (DTCR_2) DMA block size register_2 (DBSR_2) DMA mode control register_2 (DMDR_2) DMA address control register_2 (DACR_2) DMA module request select register_2 (DMRSR_2) Rev. 2.00 Mar. 15, 2006 Page 138 of 754 REJ09B0199-0200 Section 7 DMA Controller (DMAC) Channel 3: * * * * * * * * DMA source address register_3 (DSAR_3) DMA destination address register_3 (DDAR_3) DMA offset register_3 (DOFR_3) DMA transfer count register_3 (DTCR_3) DMA block size register_3 (DBSR_3) DMA mode control register_3 (DMDR_3) DMA address control register_3 (DACR_3) DMA module request select register_3 (DMRSR_3) DMA Source Address Register (DSAR) 7.2.1 DSAR is a 32-bit readable/writable register that specifies the transfer source address. DSAR updates the transfer source address every time data is transferred. When DDAR is specified as the destination address (the DIRS bit in DACR is 1) in single address mode, DSAR is ignored. Although DSAR can always be read from by the CPU, it must be read from in longwords and must not be written to while data for the channel is being transferred. Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W 15 0 R/W 14 0 R/W 13 0 R/W 12 0 R/W 11 0 R/W 10 0 R/W 9 0 R/W 8 0 R/W 23 0 R/W 22 0 R/W 21 0 R/W 20 0 R/W 19 0 R/W 18 0 R/W 17 0 R/W 16 31 30 29 28 27 26 25 24 Rev. 2.00 Mar. 15, 2006 Page 139 of 754 REJ09B0199-0200 Section 7 DMA Controller (DMAC) 7.2.2 DMA Destination Address Register (DDAR) DDAR is a 32-bit readable/writable register that specifies the transfer destination address. DDAR updates the transfer destination address every time data is transferred. When DSAR is specified as the source address (the DIRS bit in DACR is 0) in single address mode, DDAR is ignored. Although DDAR can always be read from by the CPU, it must be read from in longwords and must not be written to while data for the channel is being transferred. Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W 15 0 R/W 14 0 R/W 13 0 R/W 12 0 R/W 11 0 R/W 10 0 R/W 9 0 R/W 8 0 R/W 23 0 R/W 22 0 R/W 21 0 R/W 20 0 R/W 19 0 R/W 18 0 R/W 17 0 R/W 16 31 30 29 28 27 26 25 24 Rev. 2.00 Mar. 15, 2006 Page 140 of 754 REJ09B0199-0200 Section 7 DMA Controller (DMAC) 7.2.3 DMA Offset Register (DOFR) DOFR is a 32-bit readable/writable register that specifies the offset to update the source and destination addresses. Although different values are specified for individual channels, the same values must be specified for the source and destination sides of a single channel. Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W 15 0 R/W 14 0 R/W 13 0 R/W 12 0 R/W 11 0 R/W 10 0 R/W 9 0 R/W 8 0 R/W 23 0 R/W 22 0 R/W 21 0 R/W 20 0 R/W 19 0 R/W 18 0 R/W 17 0 R/W 16 31 30 29 28 27 26 25 24 Rev. 2.00 Mar. 15, 2006 Page 141 of 754 REJ09B0199-0200 Section 7 DMA Controller (DMAC) 7.2.4 DMA Transfer Count Register (DTCR) DTCR is a 32-bit readable/writable register that specifies the size of data to be transferred (total transfer size). To transfer 1-byte data in total, set H'00000001 in DTCR. When H'00000000 is set in this register, it means that the total transfer size is not specified and data is transferred with the transfer counter stopped (free running mode). When H'FFFFFFFF is set, the total transfer size is 4 Gbytes (4,294,967,295), which is the maximum size. While data is being transferred, this register indicates the remaining transfer size. The value corresponding to its data access size is subtracted every time data is transferred (byte: -1, word: -2, and longword: -4). Although DTCR can always be read from by the CPU, it must be read from in longwords and must not be written to while data for the channel is being transferred. Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W 15 0 R/W 14 0 R/W 13 0 R/W 12 0 R/W 11 0 R/W 10 0 R/W 9 0 R/W 8 0 R/W 23 0 R/W 22 0 R/W 21 0 R/W 20 0 R/W 19 0 R/W 18 0 R/W 17 0 R/W 16 31 30 29 28 27 26 25 24 Rev. 2.00 Mar. 15, 2006 Page 142 of 754 REJ09B0199-0200 Section 7 DMA Controller (DMAC) 7.2.5 DMA Block Size Register (DBSR) DBSR specifies the repeat size or block size. DBSR is enabled in repeat transfer mode and block transfer mode and is disabled in normal transfer mode. Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W 31 BKSZH31 0 R/W 23 BKSZH23 0 R/W 15 BKSZ15 0 R/W 7 BKSZ7 0 R/W 30 BKSZH30 0 R/W 22 BKSZH22 0 R/W 14 BKSZ14 0 R/W 6 BKSZ6 0 R/W 29 BKSZH29 0 R/W 21 BKSZH21 0 R/W 13 BKSZ13 0 R/W 5 BKSZ5 0 R/W 28 BKSZH28 0 R/W 20 BKSZH20 0 R/W 12 BKSZ12 0 R/W 4 BKSZ4 0 R/W 27 BKSZH27 0 R/W 19 BKSZH19 0 R/W 11 BKSZ11 0 R/W 3 BKSZ3 0 R/W 26 BKSZH26 0 R/W 18 BKSZH18 0 R/W 10 BKSZ10 0 R/W 2 BKSZ2 0 R/W 25 BKSZH25 0 R/W 17 BKSZH17 0 R/W 9 BKSZ9 0 R/W 1 BKSZ1 0 R/W 24 BKSZH24 0 R/W 16 BKSZH16 0 R/W 8 BKSZ8 0 R/W 0 BKSZ0 0 R/W Bit Initial Bit Name Value R/W Description Specify the repeat size or block size. When H'0001 is set, the repeat or block size is one byte, one word, or one longword. When H'0000 is set, it means the maximum value (refer to table 7.1). While the DMA is in operation, the setting is fixed. Indicate the remaining repeat or block size while the DMA is in operation. The value is decremented by 1 every time data is transferred. When the remaining size becomes 0, the value of the BKSZH bits is loaded. Set the same value as the BKSZH bits. 31 to 16 BKSZH31 Undefined R/W to BKSZH16 15 to 0 BKSZ15 Undefined R/W to BKSZ0 Rev. 2.00 Mar. 15, 2006 Page 143 of 754 REJ09B0199-0200 Section 7 DMA Controller (DMAC) Table 7.1 Mode Data Access Size, Valid Bits, and Settable Size Data Access Size BKSZH Valid Bits BKSZ Valid Bits 31 to 16 15 to 0 Settable Size (Byte) 1 to 65,536 2 to 131,072 4 to 262,144 Byte Repeat transfer and block transfer Word Longword 7.2.6 DMA Mode Control Register (DMDR) DMDR controls the DMAC operation. * DMDR_0 Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W Note: * 31 DTE 0 R/W 23 ACT 0 R 15 DTSZ1 0 R/W 7 DTF1 0 R/W 30 DACKE 0 R/W 22 -- 0 R 14 DTSZ0 0 R/W 6 DTF0 0 R/W 29 TENDE 0 R/W 21 -- 0 R 13 MDS1 0 R/W 5 DTA 0 R/W 28 -- 0 R/W 20 -- 0 R 12 MDS0 0 R/W 4 -- 0 R 27 DREQS 0 R/W 19 ERRF 0 R/(W)* 11 TSEIE 0 R/W 3 -- 0 R 26 NRD 0 R/W 18 -- 0 R 10 -- 0 R 2 DMAP2 0 R/W 25 -- 0 R 17 ESIF 0 R/(W)* 9 ESIE 0 R/W 1 DMAP1 0 R/W 24 -- 0 R 16 DTIF 0 R/(W)* 8 DTIE 0 R/W 0 DMAP0 0 R/W Only 0 can be written to this bit after having been read as 1, to clear the flag. Rev. 2.00 Mar. 15, 2006 Page 144 of 754 REJ09B0199-0200 Section 7 DMA Controller (DMAC) * DMDR_1 to DMDR_3 Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W Note: * 31 DTE 0 R/W 23 ACT 0 R 15 DTSZ1 0 R/W 7 DTF1 0 R/W 30 DACKE 0 R/W 22 -- 0 R 14 DTSZ0 0 R/W 6 DTF0 0 R/W 29 TENDE 0 R/W 21 -- 0 R 13 MDS1 0 R/W 5 DTA 0 R/W 28 -- 0 R/W 20 -- 0 R 12 MDS0 0 R/W 4 -- 0 R 27 DREQS 0 R/W 19 -- 0 R 11 TSEIE 0 R/W 3 -- 0 R 26 NRD 0 R/W 18 -- 0 R 10 -- 0 R 2 DMAP2 0 R/W 25 -- 0 R 17 ESIF 0 R/(W)* 9 ESIE 0 R/W 1 DMAP1 0 R/W 24 -- 0 R 16 DTIF 0 R/(W)* 8 DTIE 0 R/W 0 DMAP0 0 R/W Only 0 can be written to this bit after having been read as 1, to clear the flag. Rev. 2.00 Mar. 15, 2006 Page 145 of 754 REJ09B0199-0200 Section 7 DMA Controller (DMAC) Bit 31 Initial Bit Name Value DTE 0 R/W R/W Description Data Transfer Enable Enables/disables a data transfer for the corresponding channel. When this bit is set to 1, it indicates that the DMAC is in operation. Setting this bit to 1 starts a transfer when the autorequest is selected. When the on-chip module interrupt or external request is selected, a transfer request after setting this bit to 1 starts the transfer. While data is being transferred, clearing this bit to 0 stops the transfer. In block transfer mode, if writing 0 to this bit while data is being transferred, this bit is cleared to 0 after the current 1-block size data transfer. If an event which stops (sustains) a transfer occurs externally, this bit is automatically cleared to 0 to stop the transfer. Operating modes and transfer methods must not be changed while this bit is set to 1. 0: Disables a data transfer 1: Enables a data transfer (DMA is in operation) [Clearing conditions] * * * * * When the specified total transfer size of transfers is completed When a transfer is stopped by an overflow interrupt by a repeat size end When a transfer is stopped by an overflow interrupt by an extended repeat size end When a transfer is stopped by a transfer size error interrupt When clearing this bit to 0 to stop a transfer In block transfer mode, this bit changes after the current block transfer. * * When an address error or an NMI interrupt is requested In the reset state or hardware standby mode Rev. 2.00 Mar. 15, 2006 Page 146 of 754 REJ09B0199-0200 Section 7 DMA Controller (DMAC) Bit 30 Initial Bit Name Value DACKE 0 R/W R/W Description DACK Signal Output Enable Enables/disables the DACK signal output in single address mode. This bit is ignored in dual address mode. 0: Enables DACK signal output 1: Disables DACK signal output 29 TENDE 0 R/W TEND Signal Output Enable Enables/disables the TEND signal output. 0: Enables TEND signal output 1: Disables TEND signal output 28 0 R/W Reserved This bit is always read as 0. The write value should always be 0. 27 DREQS 0 R/W DREQ Select Selects whether a low level or the falling edge of the DREQ signal used in external request mode is detected. When a block transfer is performed in external request mode, clear this bit to 0 to select the low level detection. 0: Low level detection 1: Falling edge detection (the first transfer after a transfer enabled is detected on a low level) 26 NRD 0 R/W Next Request Delay Selects the accepting timing of the next transfer request. 0: Starts accepting the next transfer request after completion of the current transfer 1: Starts accepting the next transfer request one cycle after completion of the current transfer 25, 24 23 ACT All 0 0 R R Reserved These are read-only bits and cannot be modified. Active State Indicates the operating state for the channel. 0: Waiting for a transfer request or a transfer disabled state by clearing the DTE bit to 0 1: Active state 22 to 20 All 0 R Reserved These are read-only bits and cannot be modified. Rev. 2.00 Mar. 15, 2006 Page 147 of 754 REJ09B0199-0200 Section 7 DMA Controller (DMAC) Bit 19 Initial Bit Name Value ERRF 0 R/W R/(W)* Description System Error Flag Indicates that an address error or an NMI interrupt has been generated. This bit is available only in DMDR_0. Setting this bit to 1 prohibits writing to the DTE bit for all the channels. This bit is reserved in DMDR_1 to DMDR_3. It is always read as 0 and cannot be modified. 0: An address error or an NMI interrupt has not been generated 1: An address error or an NMI interrupt has been generated [Clearing condition] * * When clearing to 0 after reading ERRF = 1 When an address error or an NMI interrupt has been generated [Setting condition] However, when an address error or an NMI interrupt has been generated in module stop mode, this bit is not set. 18 17 ESIF 0 0 R R/(W)* Reserved This is a read-only bit and cannot be modified. Transfer Escape Interrupt Flag Indicates that a transfer escape end interrupt has been requested. A transfer escape end means that a transfer is terminated before the transfer counter reaches 0. 0: A transfer escape end interrupt has not been requested 1: A transfer escape end interrupt has been requested [Clearing conditions] * * * * * When setting the DTE bit to 1 When clearing to 0 before reading ESIF = 1 When a transfer size error interrupt is requested When a repeat size end interrupt is requested When a transfer end interrupt by an extended repeat area overflow is requested [Setting conditions] Rev. 2.00 Mar. 15, 2006 Page 148 of 754 REJ09B0199-0200 Section 7 DMA Controller (DMAC) Bit 16 Initial Bit Name Value DTIF 0 R/W R/(W)* Description Data Transfer Interrupt Flag Indicates that a transfer end interrupt by the transfer counter has been requested. 0: A transfer end interrupt by the transfer counter has not been requested 1: A transfer end interrupt by the transfer counter has been requested [Clearing conditions] * * * When setting the DTE bit to 1 When clearing to 0 after reading DTIF = 1 When DTCR reaches 0 and the transfer is completed [Setting condition] 15 14 DTSZ1 DTSZ0 0 0 R/W R/W Data Access Size 1 and 0 Select the data access size for a transfer. 00: Byte size (eight bits) 01: Word size (16 bits) 10: Longword size (32 bits) 11: Setting prohibited 13 12 MDS1 MDS0 0 0 R/W R/W Transfer Mode Select 1 and 0 Select the transfer mode. 00: Normal transfer mode 01: Block transfer mode 10: Repeat transfer mode 11: Setting prohibited Rev. 2.00 Mar. 15, 2006 Page 149 of 754 REJ09B0199-0200 Section 7 DMA Controller (DMAC) Bit 11 Initial Bit Name Value TSEIE 0 R/W R/W Description Transfer Size Error Interrupt Enable Enables/disables a transfer size error interrupt. When the next transfer is requested while this bit is set to 1 and the contents of the transfer counter is less than the size of data to be transferred at a single transfer request, the DTE bit is cleared to 0. At this time, the ESIF bit is set to 1 to indicate that a transfer size error interrupt has been requested. The sources of a transfer size error are as follows: * * In normal or repeat transfer mode, the total transfer size set in DTCR is less than the data access size In block transfer mode, the total transfer size set in DTCR is less than the block size 0: Disables a transfer size error interrupt request 1: Enables a transfer size error interrupt request 10 9 ESIE 0 0 R R/W Reserved This is a read-only bit and cannot be modified. Transfer Escape Interrupt Enable Enables/disables a transfer escape end interrupt request. When the ESIF bit is set to 1 with this bit set to 1, a transfer escape end interrupt is requested to the CPU. The transfer end interrupt request is cleared by clearing this bit or the ESIF bit to 0. 0: Disables a transfer escape end interrupt 1: Enables a transfer escape end interrupt 8 DTIE 0 R/W Data Transfer End Interrupt Enable Enables/disables a transfer end interrupt request by the transfer counter. When the DTIF bit is set to 1 with this bit set to 1, a transfer end interrupt is requested to the CPU. The transfer end interrupt request is cleared by clearing this bit or the DTIF bit to 0. 0: Disables a transfer end interrupt 1: Enables a transfer end interrupt Rev. 2.00 Mar. 15, 2006 Page 150 of 754 REJ09B0199-0200 Section 7 DMA Controller (DMAC) Bit 7 6 Initial Bit Name Value DTF1 DTF0 0 0 R/W R/W R/W Description Data Transfer Factor 1 and 0 Selects a DMAC activation source. When the on-chip peripheral module setting is selected, the interrupt source should be selected by DMRSR. When the external request setting is selected, the sampling method should be selected by the DREQS bit. 00: Auto request (cycle stealing) 01: Auto request (burst access) 10: On-chip module interrupt 11: External request 5 DTA 0 R/W Data Transfer Acknowledge This bit is valid while the DMA transfer is performed by the on-chip module interrupt. This bit decides whether the source flag selected by DMRSR is cleared or not. 0: The source flag is not cleared while the DMA transfer is performed by the on-chip module interrupt. Since the source flag is not cleared by the DMA transfer, it should be cleared by the CPU. 1: The source flag is cleared while the DMA transfer is performed by the on-chip module interrupt. Since the source flag is cleared by the DMA transfer, there is no need to request an interrupt to the CPU. 4, 3 All 0 R Reserved These are read-only bits and cannot be modified. Rev. 2.00 Mar. 15, 2006 Page 151 of 754 REJ09B0199-0200 Section 7 DMA Controller (DMAC) Bit 2 1 0 Initial Bit Name Value DMAP2 DMAP1 DMAP0 0 0 0 R/W R/W R/W R/W Description DMA Priority Level 2 to 0 Selects the priority level of the DTC and DMAC. When the CPU has priority over the DMAC, the DMAC masks a transfer request and waits for the timing when the CPU priority becomes lower than the DMAC priority. The priority levels can be set to the individual channels. This bit is valid when the CPUPCE bit in CPUPCR is set to 1. 000: Priority level 0 (low) 001: Priority level 1 010: Priority level 2 011: Priority level 3 100: Priority level 4 101: Priority level 5 110: Priority level 6 111: Priority level 7 (high) Note: * Only 0 can be written to, to clear the flag. Rev. 2.00 Mar. 15, 2006 Page 152 of 754 REJ09B0199-0200 Section 7 DMA Controller (DMAC) 7.2.7 DMA Address Control Register (DACR) DACR specifies the operating mode and transfer method. Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W 31 AMS 0 R/W 23 -- 0 R 15 SARIE 0 R/W 7 DARIE 0 R/W 30 DIRS 0 R/W 22 -- 0 R 14 -- 0 R 6 -- 0 R 29 -- 0 R 21 SAT1 0 R/W 13 -- 0 R 5 -- 0 R 28 -- 0 R 20 SAT0 0 R/W 12 SARA4 0 R/W 4 DARA4 0 R/W 27 -- 0 R 19 -- 0 R 11 SARA3 0 R/W 3 DARA3 0 R/W 26 RPTIE 0 R/W 18 -- 0 R 10 SARA2 0 R/W 2 DARA2 0 R/W 25 ARS1 0 R/W 17 DAT1 0 R/W 9 SARA1 0 R/W 1 DARA1 0 R/W 24 ARS0 0 R/W 16 DAT0 0 R/W 8 SARA0 0 R/W 0 DARA0 0 R/W Bit 31 Initial Bit Name Value AMS 0 R/W R/W Description Address Mode Select Selects address mode from single or dual address mode. In single address mode, the DACK pin is enabled according to the DACKE bit. 0: Dual address mode 1: Single address mode 30 DIRS 0 R/W Single Address Direction Select Specifies the data transfer direction in single address mode. This bit s ignored in dual address mode. 0: Specifies DSAR as source address 1: Specifies DDAR as destination address 29 to 27 0 R/W Reserved These are read-only bits and cannot be modified. Rev. 2.00 Mar. 15, 2006 Page 153 of 754 REJ09B0199-0200 Section 7 DMA Controller (DMAC) Bit 26 Initial Bit Name Value RPTIE 0 R/W R/W Description Repeat Size End Interrupt Enable Enables/disables a repeat size end interrupt request. In repeat transfer mode, when the next transfer is requested after completion of a 1-repeat-size data transfer while this bit is set to 1, the DTE bit in DMDR is cleared to 0. At this time, the ESIF bit in DMDR is set to 1 to indicate that a repeat size end interrupt is requested. Even when the repeat area is not specified (ARS1 = 1 and ARS0 = 0), a repeat size end interrupt after a 1-block data transfer can be requested. In addition, in block transfer mode, when the next transfer is requested after 1-block data transfer while this bit is set to 1, the DTE bit in DMDR is cleared to 0. At this time, the ESIF bit in DMDR is set to 1 to indicate that a repeat size end interrupt is requested. 0: Disables a repeat size end interrupt 1: Enables a repeat size end interrupt 25 24 ARS1 ARS0 0 0 R/W R/W Area Select 1 and 0 Specify the block area or repeat area in block or repeat transfer mode. 00: Specify the block area or repeat area on the source address 01: Specify the block area or repeat area on the destination address 10: Do not specify the block area or repeat area 11: Setting prohibited 23, 22 All 0 R Reserved These are read-only bits and cannot be modified. Rev. 2.00 Mar. 15, 2006 Page 154 of 754 REJ09B0199-0200 Section 7 DMA Controller (DMAC) Bit 21 20 Initial Bit Name Value SAT1 SAT0 0 0 R/W R/W R/W Description Source Address Update Mode 1 and 0 Select the update method of the source address (DSAR). When DSAR is not specified as the transfer source in single address mode, this bit is ignored. 00: Source address is fixed 01: Source address is updated by adding the offset 10: Source address is updated by adding 1, 2, or 4 according to the data access size 11: Source address is updated by subtracting 1, 2, or 4 according to the data access size 19, 18 17 16 DAT1 DAT0 All 0 0 0 R R/W R/W Reserved These are read-only bits and cannot be modified. Destination Address Update Mode 1 and 0 Select the update method of the destination address (DDAR). When DDAR is not specified as the transfer destination in single address mode, this bit is ignored. 00: Destination address is fixed 01: Destination address is updated by adding the offset 10: Destination address is updated by adding 1, 2, or 4 according to the data access size 11: Destination address is updated by subtracting 1, 2, or 4 according to the data access size Rev. 2.00 Mar. 15, 2006 Page 155 of 754 REJ09B0199-0200 Section 7 DMA Controller (DMAC) Bit 15 Initial Bit Name Value SARIE 0 R/W R/W Description Interrupt Enable for Source Address Extended Area Overflow Enables/disables an interrupt request for an extended area overflow on the source address. When an extended repeat area overflow on the source address occurs while this bit is set to 1, the DTE bit in DMDR is cleared to 0. At this time, the ESIF bit in DMDR is set to 1 to indicate an interrupt by an extended repeat area overflow on the source address is requested. When block transfer mode is used with the extended repeat area function, an interrupt is requested after completion of a 1-block size transfer. When setting the DTE bit in DMDR of the channel for which a transfer has been stopped to 1, the transfer is resumed from the state when the transfer is stopped. When the extended repeat area is not specified, this bit is ignored. 0: Disables an interrupt request for an extended area overflow on the source address 1: Enables an interrupt request for an extended area overflow on the source address 14, 13 All 0 R Reserved These are read-only bits and cannot be modified. Rev. 2.00 Mar. 15, 2006 Page 156 of 754 REJ09B0199-0200 Section 7 DMA Controller (DMAC) Bit 12 11 10 9 8 Initial Bit Name Value SARA4 SARA3 SARA2 SARA1 SARA0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W Description Source Address Extended Repeat Area Specify the extended repeat area on the source address (DSAR). With the extended repeat area, the specified lower address bits are updated and the remaining upper address bits are fixed. The extended repeat area size is specified from four bytes to 128 Mbytes in units of byte and a power of 2. When the lower address is overflowed from the extended repeat area by address update, the address becomes the start address and the end address of the area for address addition and subtraction, respectively. When an overflow in the extended repeat area occurs with the SARIE bit set to 1, an interrupt can be requested. Table 7.2 shows the settings and areas of the extended repeat area. 7 DARIE 0 R/W Destination Address Extended Repeat Area Overflow Interrupt Enable Enables/disables an interrupt request for an extended area overflow on the destination address. When an extended repeat area overflow on the destination address occurs while this bit is set to 1, the DTE bit in DMDR is cleared to 0. At this time, the ESIF bit in DMDR is set to 1 to indicate an interrupt by an extended repeat area overflow on the destination address is requested. When block transfer mode is used with the extended repeat area function, an interrupt is requested after completion of a 1-block size transfer. When setting the DTE bit in DMDR of the channel for which the transfer has been stopped to 1, the transfer is resumed from the state when the transfer is stopped. When the extended repeat area is not specified, this bit is ignored. 0: Disables an interrupt request for an extended area overflow on the destination address 1: Enables an interrupt request for an extended area overflow on the destination address 6, 5 All 0 R Reserved These are read-only bits and cannot be modified. Rev. 2.00 Mar. 15, 2006 Page 157 of 754 REJ09B0199-0200 Section 7 DMA Controller (DMAC) Bit 4 3 2 1 0 Initial Bit Name Value DARA4 DARA3 DARA2 DARA1 DARA0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W Description Destination Address Extended Repeat Area Specify the extended repeat area on the destination address (DDAR). With the extended repeat area, the specified lower address bits are updated and the remaining upper address bits are fixed. The extended repeat area size is specified from four bytes to 128 Mbytes in units of byte and a power of 2. When the lower address is overflowed from the extended repeat area by address update, the address becomes the start address and the end address of the area for address addition and subtraction, respectively. When an overflow in the extended repeat area occurs with the DARIE bit set to 1, an interrupt can be requested. Table 7.2 shows the settings and areas of the extended repeat area. Rev. 2.00 Mar. 15, 2006 Page 158 of 754 REJ09B0199-0200 Section 7 DMA Controller (DMAC) Table 7.2 Settings and Areas of Extended Repeat Area SARA4 to SARA0 or DARA4 to DARA0 Extended Repeat Area 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 111xx [Legend] x: Don't care Not specified 2 bytes specified as extended repeat area by the lower 1 bit of the address 4 bytes specified as extended repeat area by the lower 2 bits of the address 8 bytes specified as extended repeat area by the lower 3 bits of the address 16 bytes specified as extended repeat area by the lower 4 bits of the address 32 bytes specified as extended repeat area by the lower 5 bits of the address 64 bytes specified as extended repeat area by the lower 6 bits of the address 128 bytes specified as extended repeat area by the lower 7 bits of the address 256 bytes specified as extended repeat area by the lower 8 bits of the address 512 bytes specified as extended repeat area by the lower 9 bits of the address 1 kbyte specified as extended repeat area by the lower 10 bits of the address 2 kbytes specified as extended repeat area by the lower 11 bits of the address 4 kbytes specified as extended repeat area by the lower 12 bits of the address 8 kbytes specified as extended repeat area by the lower 13 bits of the address 16 kbytes specified as extended repeat area by the lower 14 bits of the address 32 kbytes specified as extended repeat area by the lower 15 bits of the address 64 kbytes specified as extended repeat area by the lower 16 bits of the address 128 kbytes specified as extended repeat area by the lower 17 bits of the address 256 kbytes specified as extended repeat area by the lower 18 bits of the address 512 kbytes specified as extended repeat area by the lower 19 bits of the address 1 Mbyte specified as extended repeat area by the lower 20 bits of the address 2 Mbytes specified as extended repeat area by the lower 21 bits of the address 4 Mbytes specified as extended repeat area by the lower 22 bits of the address 8 Mbytes specified as extended repeat area by the lower 23 bits of the address 16 Mbytes specified as extended repeat area by the lower 24 bits of the address 32 Mbytes specified as extended repeat area by the lower 25 bits of the address 64 Mbytes specified as extended repeat area by the lower 26 bits of the address 128 Mbytes specified as extended repeat area by the lower 27 bits of the address Setting prohibited Rev. 2.00 Mar. 15, 2006 Page 159 of 754 REJ09B0199-0200 Section 7 DMA Controller (DMAC) 7.2.8 DMA Module Request Select Register (DMRSR) DMRSR is an 8-bit readable/writable register that specifies the on-chip module interrupt source. The vector number of the interrupt source is specified in eight bits. However, 0 is regarded as no interrupt source. For the vector numbers of the interrupt sources, refer to table 7.4. Bit Bit Name Initial Value R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 7 6 5 4 3 2 1 0 7.3 Transfer Modes Table 7.3 shows the DMAC transfer modes. The transfer modes can be specified to the individual channels. Table 7.3 Transfer Modes Address Register Address Mode Transfer mode Dual address * * * Normal transfer Repeat transfer Block transfer Activation Source * Auto request (activated by CPU) On-chip module interrupt External request Common Function * Total transfer size: 1 to 4 Gbytes or not specified Offset addition Extended repeat area function DSAR/ DACK DACK/ DDAR Source DSAR Destination DDAR Repeat or block size * = 1 to 65,536 bytes, 1 to 65,536 words, or * 1 to 65,536 longwords Single address * * * Instead of specifying the source or destination address registers, data is directly transferred from/to the external device using the DACK pin The same settings as above are available other than address register setting (e.g., above transfer modes can be specified) One transfer can be performed in one bus cycle (the types of transfer modes are the same as those of dual address modes) * * Rev. 2.00 Mar. 15, 2006 Page 160 of 754 REJ09B0199-0200 Section 7 DMA Controller (DMAC) When the auto request setting is selected as the activation source, the cycle stealing or burst access can be selected. When the total transfer size is not specified (DTCR = H'00000000), the transfer counter is stopped and the transfer is continued without the limitation of the transfer count. 7.4 7.4.1 (1) Operations Address Modes Dual Address Mode In dual address mode, the transfer source address is specified in DSAR and the transfer destination address is specified in DDAR. A transfer at a time is performed in two bus cycles (when the data bus width is less than the data access size or the access address is not aligned with the boundary of the data access size, the number of bus cycles are needed more than two because one bus cycle is divided into multiple bus cycles). In the first bus cycle, data at the transfer source address is read and in the next cycle, the read data is written to the transfer destination address. The read and write cycles are not separated. Other bus cycles (bus cycle by other bus masters, refresh cycle, and external bus release cycle) are not generated between read and write cycles. The TEND signal output is enabled or disabled by the TENDE bit in DMDR. The TEND signal is output in two bus cycles. When an idle cycle is inserted before the bus cycle, the TEND signal is also output in the idle cycle. The DACK signal is not output. Figure 7.2 shows an example of the signal timing in dual address mode and figure 7.3 shows the operation in dual address mode. Rev. 2.00 Mar. 15, 2006 Page 161 of 754 REJ09B0199-0200 Section 7 DMA Controller (DMAC) DMA read cycle B Address bus RD WR TEND DSAR DMA write cycle DDAR Figure 7.2 Example of Signal Timing in Dual Address Mode Address TA Transfer Address TB Address BA Address update setting is as follows: Source address increment Fixed destination address Figure 7.3 Operations in Dual Address Mode Rev. 2.00 Mar. 15, 2006 Page 162 of 754 REJ09B0199-0200 Section 7 DMA Controller (DMAC) (2) Single Address Mode In single address mode, data between an external device and an external memory is directly transferred using the DACK pin instead of DSAR or DDAR. A transfer at a time is performed in one bus cycle. In this mode, the data bus width must be the same as the data access size. For details on the data bus width, see section 6, Bus Controller (BSC). The DMAC accesses an external device as the transfer source or destination by outputting the strobe signal to the external device (DACK) and accesses the other transfer target by outputting the address. Accordingly, the DMA transfer is performed in one bus cycle. Figure 7.4 shows an example of a transfer between an external memory and an external device with the DACK pin. In this example, the external device outputs data on the data bus and the data is written to the external memory in the same bus cycle. The transfer direction is decided by the DIRS bit in DACR which specifies an external device with the DACK pin as the transfer source or destination. When DIRS = 0, data is transferred from an external memory (DSAR) to an external device with the DACK pin. When DIRS = 1, data is transferred from an external device with the DACK pin to an external memory (DDAR). The settings of registers which are not used as the transfer source or destination are ignored. The DACK signal output is enabled in single address mode by the DACKE bit in DMDR. The DACK signal is low active. The TEND signal output is enabled or disabled by the TENDE bit in DMDR. The TEND signal is output in one bus cycle. When an idle cycle is inserted before the bus cycle, the TEND signal is also output in the idle cycle. Figure 7.5 shows an example of timing charts in single address mode and figure 7.6 shows an example of operation in single address mode. External address bus LSI External memory DMAC DACK DREQ External device with DACK External data bus Data flow Figure 7.4 Data Flow in Single Address Mode Rev. 2.00 Mar. 15, 2006 Page 163 of 754 REJ09B0199-0200 Section 7 DMA Controller (DMAC) Transfer from external memory to external device with DACK DMA cycle B Address bus RD WR DACK Data bus TEND Data output by external memory DSAR Address for external memory space RD signal for external memory space Transfer from external device with DACK to external memory DMA cycle B Address bus RD WR DACK Data bus TEND Data output by external device with DACK WR signal for external memory space DDAR Address for external memory space Figure 7.5 Example of Signal Timing in Single Address Mode Address T Transfer DACK Address B Figure 7.6 Operations in Single Address Mode Rev. 2.00 Mar. 15, 2006 Page 164 of 754 REJ09B0199-0200 Section 7 DMA Controller (DMAC) 7.4.2 (1) Transfer Modes Normal Transfer Mode In normal transfer mode, one data access size of data is transferred at a single transfer request. Up to 4 Gbytes can be specified as a total transfer size by DTCR. DBSR is ignored in normal transfer mode. The TEND signal is output only in the last DMA transfer. Figure 7.7 shows an example of the signal timing in normal transfer mode and figure 7.8 shows the operation in normal transfer mode. Auto request transfer in dual address mode: DMA transfer cycle Bus cycle TEND External request transfer in single address mode: DREQ Bus cycle DMA DMA Read Write Last DMA transfer cycle Read Write DACK Figure 7.7 Example of Signal Timing in Normal Transfer Mode Address TA Transfer Total transfer size (DTCR) Address TB Address BA Address BB Figure 7.8 Operations in Normal Transfer Mode Rev. 2.00 Mar. 15, 2006 Page 165 of 754 REJ09B0199-0200 Section 7 DMA Controller (DMAC) (2) Repeat Transfer Mode In repeat transfer mode, one data access size of data is transferred at a single transfer request. Up to 4 Gbytes can be specified as a total transfer size by DTCR. The repeat size can be specified in DBSR up to 65536 x data access size. The repeat area can be specified for the source or destination address side by bits ARS1 and ARS0 in DACR. The address specified as the repeat area returns to the transfer start address when the repeat size of transfers is completed. This operation is repeated until the total transfer size specified in DTCR is completed. When H'00000000 is specified in DTCR, it is regarded as the free running mode and repeat transfer is continued until the DTE bit in DMDR is cleared to 0. In addition, a DMA transfer can be stopped and a repeat size end interrupt can be requested to the CPU or DTC when the repeat size of transfers is completed. When the next transfer is requested after completion of a 1-repeat size data transfer while the RPTIE bit is set to 1, the DTE bit in DMDR is cleared to 0 and the ESIF bit in DMDR is set to 1 to complete the transfer. At this time, an interrupt is requested to the CPU or DTC when the ESIE bit in DMDR is set to 1. The timing of the TEND signal is the same as in normal transfer mode. Figure 7.9 shows the operation in repeat transfer mode while dual address mode is set. When the repeat area is specified as neither source nor destination address side, the operation is the same as the normal transfer mode operation shown in figure 7.8. In this case, a repeat size end interrupt can also be requested to the CPU when the repeat size of transfers is completed. Address TA Transfer Repeat size = BKSZH x data access size Address TB Address BA Total transfer size (DTCR) Operation when the repeat area is specified to the source side Address BB Figure 7.9 Operations in Repeat Transfer Mode Rev. 2.00 Mar. 15, 2006 Page 166 of 754 REJ09B0199-0200 Section 7 DMA Controller (DMAC) (3) Block Transfer Mode In block transfer mode, one block size of data is transferred at a single transfer request. Up to 4 Gbytes can be specified as total transfer size by DTCR. The block size can be specified in DBSR up to 65536 x data access size. While one block of data is being transferred, transfer requests from other channels are suspended. When the transfer is completed, the bus is released to the other bus master. The block area can be specified for the source or destination address side by bits ARS1 and ARS0 in DACR. The address specified as the block area returns to the transfer start address when the block size of data is completed. When the block area is specified as neither source nor destination address side, the operation continues without returning the address to the transfer start address. A repeat size end interrupt can be requested. The TEND signal is output every time 1-block data is transferred in the last DMA transfer cycle. When the external request is selected as an activation source, the low level detection of the DREQ signal (DREQS = 0) should be selected. When an interrupt request by an extended repeat area overflow is used in block transfer mode, settings should be selected carefully. For details, see section 7.4.5, Extended Repeat Area Function. Figure 7.10 shows an example of the DMA transfer timing in block transfer mode. The transfer conditions are as follows: * Address mode: single address mode * Data access size: byte * 1-block size: three bytes The block transfer mode operations in single address mode and in dual address mode are shown in figures 7.11 and 7.12, respectively. DREQ Transfer cycles for one block Bus cycle CPU CPU DMAC DMAC DMAC CPU No CPU cycle generated TEND Figure 7.10 Operations in Block Transfer Mode Rev. 2.00 Mar. 15, 2006 Page 167 of 754 REJ09B0199-0200 Section 7 DMA Controller (DMAC) Address T BKSZH x data access size Transfer Block DACK Address B Figure 7.11 Operation in Single Address Mode in Block Transfer Mode (Block Area Specified) Address TA First block BKSZH x data access size Transfer First block Address TB Second block Second block Total transfer size (DTCR) Nth block Address BA Nth block Address BB Figure 7.12 Operation in Dual Address Mode in Block Transfer Mode (Block Area Not Specified) Rev. 2.00 Mar. 15, 2006 Page 168 of 754 REJ09B0199-0200 Section 7 DMA Controller (DMAC) 7.4.3 Activation Sources The DMAC is activated by an auto request, an on-chip module interrupt, and an external request. The activation source is specified by bits DTF1 and DTF0 in DMDR. (1) Activation by Auto Request The auto request activation is used when a transfer request from an external device or an on-chip peripheral module is not generated such as a transfer between memory and memory or between memory and an on-chip peripheral module which does not request a transfer. A transfer request is automatically generated inside the DMAC. In auto request activation, setting the DTE bit in DMDR starts a transfer. The bus mode can be selected from cycle stealing and burst modes. (2) Activation by On-Chip Module Interrupt An interrupt request from an on-chip peripheral module (on-chip peripheral module interrupt) is used as a transfer request. When a DMA transfer is enabled (DTE = 1), the DMA transfer is started by an on-chip module interrupt. The activation source of the on-chip module interrupt is selected by the DMA module request select register (DMRSR). The activation sources are specified to the individual channels. Table 7.4 is a list of on-chip module interrupts for the DMAC. The interrupt request selected as an activation source can simultaneously generate interrupt requests to the CPU. For details, see section 5, Interrupt Controller. The DMAC receives interrupt requests by on-chip peripheral modules independent of the interrupt controller. Therefore, the DMAC is not affected by priority given in the interrupt controller. When the DMAC is activated with DTA = 1, the interrupt request flag is automatically cleared by a DMA transfer. If multiple channels use a single transfer request as an activation source, when the channel having priority is activated, the interrupt request flag is cleared. In this case, other channels may not be activated because the transfer request is not held in the DMAC. When the DMAC is activated with DTA = 0, the interrupt request flag is not cleared by the DMAC. Thus it should be cleared by the CPU or a DTC transfer. When an activation source is selected while DTE = 0, the activation source does not request a transfer to the DMAC. It requests an interrupt to the CPU or DTC. In addition, make sure that an interrupt request flag as an on-chip module interrupt source is cleared to 0 before writing 1 to the DTE bit. Rev. 2.00 Mar. 15, 2006 Page 169 of 754 REJ09B0199-0200 Section 7 DMA Controller (DMAC) Table 7.4 List of On-chip module interrupts to DMAC On-Chip Module A/D_0 A/D_1 TPU_0 TPU_1 TPU_2 TPU_3 SCI_3 SCI_3 SCI_4 SCI_4 TPU_6 TPU_7 TPU_8 TPU_9 TPU_10 TPU_11 SSU_0 DMRSR (Vector Number) 86 87 88 93 97 101 157 158 161 162 164 169 173 177 182 188 228 229 232 233 236 237 On-Chip Module Interrupt Source ADI0 (A/D conversion end interrupt) ADI1 (A/D conversion end interrupt) TGI0A (TGI0A input capture/compare match) TGI1A (TGI1A input capture/compare match) TGI2A (TGI2A input capture/compare match) TGI3A (TGI3A input capture/compare match) RXI3 (receive data full interrupt for SCI channel 3) TXI3 (transmit data empty interrupt for SCI channel 3) RXI4 (receive data full interrupt for SCI channel 4) TXI4 (transmit data empty interrupt for SCI channel 4) TGI6A (TGI6A input capture/compare match) TGI7A (TGI7A input capture/compare match) TGI8A (TGI8A input capture/compare match) TGI9A (TGI9A input capture/compare match) TGI10A (TGI10A input capture/compare match) TGI11A (TGI11A input capture/compare match) SSRXI0 (receive data full interrupt for SSU channel 0) SSTXI0 (transmit data empty interrupt or transmit end for SSU channel 0) SSU_0 SSRXI1 (receive data full interrupt for SSU channel 1) SSU_1 SSTXI1 (transmit data empty interrupt or transmit end for SSU channel 1) SSU_1 SSRXI2 (receive data full interrupt for SSU channel 2) SSU_2 SSTXI2 (transmit data empty interrupt or transmit end for SSU channel 2) SSU_2 Rev. 2.00 Mar. 15, 2006 Page 170 of 754 REJ09B0199-0200 Section 7 DMA Controller (DMAC) (3) Activation by External Request A transfer is started by a transfer request signal (DREQ) from an external device. When a DMA transfer is enabled (DTE = 1), the DMA transfer is started by the DREQ assertion. A transfer request signal is input to the DREQ pin. The DREQ signal is detected on the falling edge or low level. Whether the falling edge or low level detection is used is selected by the DREQS bit in DMDR. To perform a block transfer, select the low level detection. When an external request is selected as an activation source, clear the DDR bit to 0 and set the ICR bit to 1 for the corresponding pin. For details, see section 9, I/O Ports. When a DMA transfer between on-chip peripheral modules is performed, select an activation source form the auto request and on-chip module interrupt (the external request cannot be used). 7.4.4 Bus Access Modes There are two types of bus access modes: cycle stealing and burst. When an activation source is the auto request, the cycle stealing or burst mode is selected by bit DTF0 in DMDR. When an activation source is the on-chip module interrupt or external request, the cycle stealing mode is selected. (1) Cycle Stealing Mode In cycle stealing mode, the DMAC releases the bus every time one unit of transfers (byte, word, longword, or 1-block size) is completed. After that, when a transfer is requested, the DMAC obtains the bus to transfer 1-unit data and then releases the bus on completion of the transfer. This operation is continued until the transfer end condition is satisfied. When a transfer is requested to another channel during a DMA transfer, the DMAC releases the bus and then transfers data for the requested channel. For details on operations when a transfer is requested to multiple channels, see section 7.4.8, Priority of Channels. Figure 7.13 shows an example of timing in cycle stealing mode. The transfer conditions are as follows: * Address mode: Single address mode * Sampling method of the DREQ signal: Low level detection Rev. 2.00 Mar. 15, 2006 Page 171 of 754 REJ09B0199-0200 Section 7 DMA Controller (DMAC) DREQ Bus cycle CPU CPU DMAC CPU DMAC CPU Bus released temporarily for the CPU Figure 7.13 Example of Timing in Cycle Stealing Mode (2) Burst Access Mode In burst mode, once it takes the bus, the DMAC continues a transfer without releasing the bus until the transfer end condition is satisfied. Even if a transfer is requested from another channel having priority, the transfer is not stopped once it is started. The DMAC releases the bus in the next cycle after the transfer for the channel in burst mode is completed. This is similarly to operation in cycle stealing mode. However, setting the IBCCS bit in IBCR of the bus controller makes the DMAC release the bus to pass the bus to another bus master. In block transfer mode, the burst mode setting is ignored (operation is the same as that in burst mode during one block of transfers). The DMAC is always operated in cycle stealing mode. Clearing the DTE bit in DMDR stops a DMA transfer. A transfer requested before the DTE bit is cleared to 0 by the DMAC is executed. When an interrupt by a transfer size error, a repeat size end, or an extended repeat area overflow occurs, the DTE bit is cleared to 0 and the transfer ends. Figure 7.14 shows an example of timing in burst mode. Bus cycle CPU CPU DMAC DMAC DMAC CPU CPU No CPU cycle generated Figure 7.14 Example of Timing in Burst Mode 7.4.5 Extended Repeat Area Function The source and destination address sides can be specified as the extended repeat area. The contents of the address register repeat addresses within the area specified as the extended repeat area. For example, to use a ring buffer as the transfer target, the contents of the address register should return to the start address of the buffer every time the contents reach the end address of the buffer (overflow on the ring buffer address). This operation can automatically be performed using the extended repeat area function of the DMAC. Rev. 2.00 Mar. 15, 2006 Page 172 of 754 REJ09B0199-0200 Section 7 DMA Controller (DMAC) The extended repeat areas can be specified independently to the source address register (DSAR) and destination address register (DDAR). The extended repeat area on the source address is specified by bits SARA4 to SARA0 in DACR. The extended repeat area on the destination address is specified by bits DARA4 to DARA0 in DACR. The extended repeat area sizes for each side can be specified independently. A DMA transfer is stopped and an interrupt by an extended repeat area overflow can be requested to the CPU when the contents of the address register reach the end address of the extended repeat area. When an overflow on the extended repeat area set in DSAR occurs while the SARIE bit in DACR is set to 1, the ESIF bit in DMDR is set to 1 and the DTE bit in DMDR is cleared to 0 to stop the transfer. At this time, if the ESIE bit in DMDR is set to 1, an interrupt by an extended repeat area overflow is requested to the CPU. When the DARIE bit in DACR is set to 1, an overflow on the extended repeat area set in DDAR occurs, meaning that the destination side is a target. During the interrupt handling, setting the DTE bit in DMDR resumes the transfer. Figure 7.15 shows an example of the extended repeat area operation. When the area represented by the lower three bits of DSAR (eight bytes) is specified as the extended repeat area (SARA4 to SARA0 = B'00011) External memory Area specified by DSAR H'23FFFE H'23FFFF H'240000 H'240001 H'240002 H'240003 H'240004 H'240005 H'240006 H'240007 H'240008 H'240009 H'240000 H'240001 H'240002 H'240003 H'240004 H'240005 H'240006 H'240007 An interrupt request by extended repeat area overflow can be generated. Repeat Figure 7.15 Example of Extended Repeat Area Operation ... ... Rev. 2.00 Mar. 15, 2006 Page 173 of 754 REJ09B0199-0200 Section 7 DMA Controller (DMAC) When an interrupt by an extended repeat area overflow is used in block transfer mode, the following should be taken into consideration. When a transfer is stopped by an interrupt by an extended repeat area overflow, the address register must be set so that the block size is a power of 2 or the block size boundary is aligned with the extended repeat area boundary. When an overflow on the extended repeat area occurs during a transfer of one block, the interrupt by the overflow is suspended and the transfer overruns. Figure 7.16 shows examples when the extended repeat area function is used in block transfer mode. When the are represented by the lower three bits (eight bytes) of DSAR are specified as the extended repeat area (SARA4 to SARA0 = 3) and the block size in block transfer mode is specified to 5 (bits 23 to 16 in DTCR = 5). External memory Area specified 1st block 2nd block by DSAR transfer transfer H'23FFFE H'23FFFF H'240000 H'240001 H'240002 H'240003 H'240004 H'240005 H'240006 H'240007 H'240008 H'240009 H'240000 H'240001 H'240002 H'240003 H'240004 H'240005 H'240006 H'240007 H'240000 H'240001 H'240002 H'240003 H'240004 H'240005 H'240006 H'240007 Block transfer continued H'240000 H'240001 Interrupt request generated Figure 7.16 Example of Extended Repeat Area Function in Block Transfer Mode Rev. 2.00 Mar. 15, 2006 Page 174 of 754 REJ09B0199-0200 ... ... Section 7 DMA Controller (DMAC) 7.4.6 Address Update Function using Offset The source and destination addresses are updated by fixing, increment/decrement by 1, 2, or 4, or offset addition. When the offset addition is selected, the offset specified by the offset register (DOFR) is added to the address every time the DMAC transfers the data access size of data. This function realizes a data transfer where addresses are allocated to separated areas. Figure 7.17 shows the address update method. 0 1, 2, or 4 + offset Address not updated Data access size added to or subtracted from address (addresses are continuous) (b) Increment or decrement by 1, 2, or 4 Offset is added to address (addresses are not continuous) (c) Offset addition (a) Address fixed Figure 7.17 Address Update Method In item (a), Address fixed, the transfer source or destination address is not updated indicating the same address. In item (b), Increment or decrement by 1, 2, or 4, the transfer source or destination address is incremented or decremented by the value according to the data access size at each transfer. Byte, word, or longword can be specified as the data access size. The value of 1 for byte, 2 for word, and 4 for longword is used for updating the address. This operation realizes the data transfer placed in consecutive areas. Rev. 2.00 Mar. 15, 2006 Page 175 of 754 REJ09B0199-0200 Section 7 DMA Controller (DMAC) In item (c), Offset addition, the address update does not depend on the data access size. The offset specified by DOFR is added to the address every time the DMAC transfers data of the data access size. The address is calculated by the offset set in DOFR and the contents of DSAR and DDAR. Although the DMAC calculates only addition, an offset subtraction can be realized by setting the negative value in DOFR. In this case, the negative value must be 2's complement. (1) Basic Transfer Using Offset Figure 7.18 shows a basic operation of a transfer using the offset addition. Data 1 Address A1 Transfer Offset Data 1 Data 2 Data 3 Data 4 Data 5 : Address B1 Address B2 = Address B1 + 4 Address B3 = Address B2 + 4 Address B4 = Address B3 + 4 Address B5 = Address B4 + 4 Data 2 Address A2 = Address A1 + Offset Offset : : : Data 3 Address A3 = Address A2 + Offset Offset Transfer source: Offset addition Transfer destination: Increment by 4 (longword) Address A4 = Address A3 + Offset Data 4 Offset Data 5 Address A5 = Address A4 + Offset Figure 7.18 Operation of Offset Addition Rev. 2.00 Mar. 15, 2006 Page 176 of 754 REJ09B0199-0200 Section 7 DMA Controller (DMAC) In figure 7.18, the offset addition is selected as the transfer source address update and increment or decrement by 1, 2, or 4 is selected as the transfer destination address. The address update means that data at the address which is away from the previous transfer source address by the offset is read from. The data read from the address away from the previous address is written to the consecutive area in the destination side. (2) XY Conversion Using Offset Figure 7.19 shows the XY conversion using the offset addition in repeat transfer mode. Data 1 Data 5 Data 9 Data 13 Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 7 Data 8 Data 9 Data 10 Data 11 Data 12 Data 13 Data 14 Data 15 Data 16 1st transfer 2nd transfer Transfer 3rd transfer 4th transfer Data 2 Data 6 Data 10 Data 14 Data 3 Data 7 Data 11 Data 15 Data 4 Data 8 Data 12 Data 16 1st transfer Offset Offset Offset Data 1 Data 5 Data 9 Data 13 Data 2 Data 6 Data 10 Data 14 Data 3 Data 7 Data 11 Data 15 Data 4 Data 8 Data 12 Data 16 2nd transfer Transfer source 3rd transfer addresses changed by CPU Data 1 Data 1 Data 5 Data 5 Address initialized Data 9 Data 9 Address initialized Data 13 Data 13 Data 2 Data 2 Data 6 Data 6 Data 10 Data 10 Data 14 Data 14 Data 3 Data 3 Data 7 Data 7 Data 11 Data 11 Data 15 Data 15 Data 4 Data 4 Data 8 Data 8 Interrupt request Data 12 Data 12 Interrupt generated request Data 16 Data 16 generated Transfer Transfer source addresses changed by CPU Interrupt request generated Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 7 Data 8 Data 9 Data 10 Data 11 Data 12 Data 13 Data 14 Data 15 Data 16 1st transfer 2nd transfer 3rd transfer 4th transfer Figure 7.19 XY Conversion Operation Using Offset Addition in Repeat Transfer Mode In figure 7.19, the source address side is specified to the repeat area by DACR and the offset addition is selected. The offset value is set to 4 x data access size (when the data access size is longword, H'00000010 is set in DOFR, as an example). The repeat size is set to 4 x data access size (when the data access size is longword, the repeat size is set to 4 x 4 = 16 bytes, as an example). The increment or decrement by 1, 2, or 4 is specified as the transfer destination address. A repeat size end interrupt is requested when the repeat size of transfers is completed. Rev. 2.00 Mar. 15, 2006 Page 177 of 754 REJ09B0199-0200 Section 7 DMA Controller (DMAC) When a transfer starts, the transfer source address is added to the offset every time data is transferred. The transfer data is written to the destination continuous addresses. When data 4 is transferred meaning that the repeat size of transfers is completed, the transfer source address returns to the transfer start address (address of data 1 on the transfer source) and a repeat size end interrupt is requested. While this interrupt stops the transfer temporarily, the contents of DSAR are written to the address of data 5 by the CPU (when the data access size is longword, write the data 1 address + 4). When the DTE bit in DMDR is set to 1, the transfer is resumed from the state when the transfer is stopped. Accordingly, operations are repeated and the transfer source data is transposed to the destination area (XY conversion). Figure 7.20 shows a flowchart of the XY conversion. Start Set address and transfer count Set repeat transfer mode Enable repeat escape interrupt Set DTE bit to 1 Receives transfer request Transfers data Decrements transfer count and repeat size No Transfer count = 0? Yes No Repeat size = 0? Yes Initializes transfer source address Generates repeat size end interrupt request Set transfer source address + 4 (Longword transfer) End : User operation : DMAC operation Figure 7.20 XY Conversion Flowchart Using Offset Addition in Repeat Transfer Mode Rev. 2.00 Mar. 15, 2006 Page 178 of 754 REJ09B0199-0200 Section 7 DMA Controller (DMAC) (3) Offset Subtraction When setting the negative value in DOFR, the offset value must be 2's complement. The 2's complement is obtained by the following formula. 2's complement of offset = 1 + ~offset (~: bit inversion) Example: 2's complement of H'0001FFFF = H'FFFE0000 + H'00000001 = H'FFFE0001 The value of 2's complement can be obtained by the NEG.L instruction. 7.4.7 Register during DMA Transfer The DMAC registers are updated by a DMA transfer. The value to be updated differs according to the other settings and transfer state. The registers to be updated are DSAR, DDAR, DTCR, bits BKSZH and BKSZ in DBSR, and the DTE, ACT, ERRF, ESIF, and DTIF bits in DMDR. (1) DMA Source Address Register When the transfer source address set in DSAR is accessed, the contents of DSAR are output and then are updated to the next address. The increment or decrement can be specified by bits SAT1 and SAT0 in DACR. When SAT1 and SAT0 = B'00, the address is fixed. When SAT1 and SAT0 = B'01, the address is added with the offset. When SAT1 and SAT0 = B'10, the address is incremented. When SAT1 and SAT0 = B'11, the address is decremented. The size of increment or decrement depends on the data access size. The data access size is specified by bits DTSZ1 and DTSZ0 in DMDR. When DTSZ1 and DTSZ0 = B'00, the data access size is byte and the address is incremented or decremented by 1. When DTSZ1 and DTSZ0 = B'01, the data access size is word and the address is incremented or decremented by 2. When DTSZ1 and DTSZ0 = B'10, the data access size is longword and the address is incremented or decremented by 4. Even if the access data size of the source address is word or longword, when the source address is not aligned with the word or longword boundary, the read bus cycle is divided into byte or word cycles. While data of one word or one longword is being read, the size of increment or decrement is changing according to the actual data access size, for example, +1 or +2 for byte or word data. After one word or one longword of data is read, the address when the read cycle is started is incremented or decremented by the value according to bits SAT1 and SAT0. Rev. 2.00 Mar. 15, 2006 Page 179 of 754 REJ09B0199-0200 Section 7 DMA Controller (DMAC) In block or repeat transfer mode, when the block or repeat size of data transfers is completed while the block or repeat area is specified to the source address side, the source address returns to the transfer start address and is not affected by the address update. When the extended repeat area is specified to the source address side, operation follows the setting. The upper address bits are fixed and is not affected by the address update. While data is being transferred, DSAR must be accessed in longwords. If the upper word and lower word are read separately, incorrect data may be read from since the contents of DSAR during the transfer may be updated regardless of the access by the CPU. Moreover, DSAR for the channel being transferred must not be written to. (2) DMA Destination Address Register When the transfer destination address set in DDAR is accessed, the contents of DDAR are output and then are updated to the next address. The increment or decrement can be specified by bits DAT1 and DAT0 in DACR. When DAT1 and DAT0 = B'00, the address is fixed. When DAT1 and DAT0 = B'01, the address is added with the offset. When DAT1 and DAT0 = B'10, the address is incremented. When DAT1 and DAT0 = B'11, the address is decremented. The incrementing or decrementing size depends on the data access size. The data access size is specified by bits DTSZ1 and DTSZ0 in DMDR. When DTSZ1 and DTSZ0 = B'00, the data access size is byte and the address is incremented or decremented by 1. When DTSZ1 and DTSZ0 = B'01, the data access size is word and the address is incremented or decremented by 2. When DTSZ1 and DTSZ0 = B'10, the data access size is longword and the address is incremented or decremented by 4. Even if the access data size of the destination address is word or longword, when the destination address is not aligned with the word or longword boundary, the write bus cycle is divided into byte and word cycles. While one word or one longword of data is being written, the incrementing or decrementing size is changing according to the actual data access size, for example, +1 or +2 for byte or word data. After the one word or one longword of data is written, the address when the write cycle is started is incremented or decremented by the value according to bits SAT1 and SAT0. In block or repeat transfer mode, when the block or repeat size of data transfers is completed while the block or repeat area is specified to the destination address side, the destination address returns to the transfer start address and is not affected by the address update. When the extended repeat area is specified to the destination address side, operation follows the setting. The upper address bits are fixed and is not affected by the address update. Rev. 2.00 Mar. 15, 2006 Page 180 of 754 REJ09B0199-0200 Section 7 DMA Controller (DMAC) While data is being transferred, DDAR must be accessed in longwords. If the upper word and lower word are read separately, incorrect data may be read from since the contents of DDAR during the transfer may be updated regardless of the access by the CPU. Moreover, DDAR for the channel being transferred must not be written to. (3) DMA Transfer Count Register (DTCR) A DMA transfer decrements the contents of DTCR by the transferred bytes. When byte data is transferred, DTCR is decremented by 1. When word data is transferred, DTCR is decremented by 2. When longword data is transferred, DTCR is decremented by 4. However, when DTCR = 0, the contents of DTCR are not changed since the number of transfers is not counted. While data is being transferred, all the bits of DTCR may be changed. DTCR must be accessed in longwords. If the upper word and lower word are read separately, incorrect data may be read from since the contents of DTCR during the transfer may be updated regardless of the access by the CPU. Moreover, DTCR for the channel being transferred must not be written to. When a conflict occurs between the address update by DMA transfer and write access by the CPU, the CPU has priority. When a conflict occurs between change from 1, 2, or 4 to 0 in DTCR and write access by the CPU (other than 0), the CPU has priority in writing to DTCR. However, the transfer is stopped. (4) DMA Block Size Register (DBSR) DBSR is enabled in block or repeat transfer mode. Bits 31 to 16 in DBSR function as BKSZH and bits 15 to 0 in DBSR function as BKSZ. The BKSZH bits (16 bits) store the block size and repeat size and its value is not changed. The BKSZ bits (16 bits) function as a counter for the block size and repeat size and its value is decremented every transfer by 1. When the BKSZ value is to change from 1 to 0 by a DMA transfer, 0 is not stored but the BKSZH value is loaded into the BKSZ bits. Since the upper 16 bits of DBSR are not updated, DBSR can be accessed in words. DBSR for the channel being transferred must not be written to. Rev. 2.00 Mar. 15, 2006 Page 181 of 754 REJ09B0199-0200 Section 7 DMA Controller (DMAC) (5) DTE Bit in DMDR Although the DTE bit in DMDR enables or disables data transfer by the CPU write access, it is automatically cleared to 0 according to the DMA transfer state by the DMAC. The conditions for clearing the DTE bit by the DMAC are as follows: * * * * * * * * * When the total size of transfers is completed When a transfer is completed by a transfer size error interrupt When a transfer is completed by a repeat size end interrupt When a transfer is completed by an extended repeat area overflow interrupt When a transfer is stopped by an NMI interrupt When a transfer is stopped by and address error Reset state Hardware standby mode When a transfer is stopped by writing 0 to the DTE bit Writing to the registers for the channels when the corresponding DTE bit is set to 1 is prohibited (except for the DTE bit). When changing the register settings after writing 0 to the DTE bit, confirm that the DTE bit has been cleared to 0. Figure 7.21 show the procedure for changing the register settings for the channel being transferred. Changing register settings of channel during operation Write 0 to DTE bit [1] [1] Write 0 to the DTE bit in DMDR. [2] Read the DTE bit. [3] Confirm that DTE = 0. DTE = 1 indicates that DMA is transferring. [4] Write the desired values to the registers. Read DTE bit [2] [3] No DTE = 0? Yes Change register settings End of changing register settings [4] Figure 7.21 Procedure for Changing Register Setting For Channel being Transferred Rev. 2.00 Mar. 15, 2006 Page 182 of 754 REJ09B0199-0200 Section 7 DMA Controller (DMAC) (6) ACT Bit in DMDR The ACT bit in DMDR indicates whether the DMAC is in the idle or active state. When DTE = 0 or DTE = 1 and the DMAC is waiting for a transfer request, the ACT bit is 0. Otherwise (the DMAC is in the active state), the ACT bit is 1. When individual transfers are stopped by writing 0 and the transfer is not completed, the ACT bit retains 1. In block transfer mode, even if individual transfers are stopped by writing 0 to the DTE bit, the 1block size of transfers is not stopped. The ACT bit retains 1 from writing 0 to the DTE bit to completion of a 1-block size transfer. In burst mode, up to three times of DMA transfer are performed from the cycle in which the DTE bit is written to 0. The ACT bit retains 1 from writing 0 to the DTE bit to completion of DMA transfer. (7) ERRF Bit in DMDR When an address error or an NMI interrupt occur, the DMAC clears the DTE bits for all the channels to stop a transfer. In addition, it sets the ERRF bit in DMDR_0 to 1 to indicate that an address error or an NMI interrupt has occurred regardless of whether or not the DMAC is in operation. (8) ESIF Bit in DMDR When an interrupt by an transfer size error, a repeat size end, or an extended repeat area overflow is requested, the ESIF bit in DMDR is set to 1. When both the ESIF and ESIE bits are set to 1, a transfer escape interrupt is requested to the CPU or DTC. The ESIF bit is set to 1 when the ACT bit in DMDR is cleared to 0 to stop a transfer after the bus cycle of the interrupt source is completed. The ESIF bit is automatically cleared to 0 and a transfer request is cleared if the transfer is resumed by setting the DTE bit to 1 during interrupt handling. For details on interrupts, see section 7.7, Interrupt Sources. Rev. 2.00 Mar. 15, 2006 Page 183 of 754 REJ09B0199-0200 Section 7 DMA Controller (DMAC) (9) DTIF Bit in DMDR The DTIF bit in DMDR is set to 1 after the total transfer size of transfers is completed. When both the DTIF and DTIE bits in DMDR are set to 1, a transfer end interrupt by the transfer counter is requested to the CPU or DTC. The DTIF bit is set to 1 when the ACT bit in DMDR is cleared to 0 to stop a transfer after the bus cycle is completed. The DTIF bit is automatically cleared to 0 and a transfer request is cleared if the transfer is resumed by setting the DTE bit to 1 during interrupt handling. For details on interrupts, see section 7.7, Interrupt Sources. 7.4.8 Priority of Channels The channels of the DMAC are given following priority levels: channel 0 > channel 1 > channel 2 > channel3. Table 7.5 shows the priority levels among the DMAC channels. Table 7.5 Channel Channel 0 Channel 1 Channel 2 Channel 3 Low Priority among DMAC Channels Priority High The channel having highest priority other than the channel being transferred is selected when a transfer is requested from other channels. The selected channel starts the transfer after the channel being transferred releases the bus. At this time, when a bus master other than the DMAC requests the bus, the cycle for the bus master is inserted. In a burst transfer or a block transfer, channels are not switched. Rev. 2.00 Mar. 15, 2006 Page 184 of 754 REJ09B0199-0200 Section 7 DMA Controller (DMAC) Figure 7.22 shows a transfer example when multiple transfer requests from channels 0 to 2. Channel 0 transfer B Address bus DMAC operation Channel 0 Channel 1 Channel 2 Wait Channel 0 Request cleared Channel 1 transfer Channel 2 transfer Channel 0 Bus released Channel 1 Bus released Channel 2 Wait Channel 1 Channel 2 Request cleared Request Selected retained Request Not Request retained selected retained Selected Request cleared Figure 7.22 Example of Timing for Channel Priority 7.4.9 DMA Basic Bus Cycle Figure 7.23 shows an examples of signal timing of a basic bus cycle. In figure 7.23, data is transferred in words from the 16-bit 2-state access space to the 8-bit 3-state access space. When the bus mastership is passed from the DMAC to the CPU, data is read from the source address and it is written to the destination address. The bus is not released between the read and write cycles by other bus requests. DMAC bus cycles follows the bus controller settings. CPU cycle T1 B Source address Address bus Destination address T2 T1 DMAC cycle (one word transfer) T2 T3 T1 T2 T3 CPU cycle RD HHWR, HLWR, LHWR LLWR High Figure 7.23 Example of Bus Timing of DMA Transfer Rev. 2.00 Mar. 15, 2006 Page 185 of 754 REJ09B0199-0200 Section 7 DMA Controller (DMAC) 7.4.10 (1) Bus Cycles in Dual Address Mode Normal Transfer Mode (Cycle Stealing Mode) In cycle stealing mode, the bus is released every time one transfer size of data (one byte, one word, or one longword) is completed. One bus cycle or more by the CPU or DTC are executed in the bus released cycles. In figure 7.24, the TEND signal output is enabled and data is transferred in words from the external 16-bit 2-state access space to the external 16-bit 2-state access space in normal transfer mode by cycle stealing. DMA read cycle DMA write cycle DMA read cycle DMA write cycle DMA read cycle DMA write cycle B Address bus RD LHWR, LLWR TEND Bus released Bus released Bus released Last transfer cycle Bus released Figure 7.24 Example of Transfer in Normal Transfer Mode by Cycle Stealing In figures 7.25 and 7.26, the TEND signal output is enabled and data is transferred in longwords from the external 16-bit 2-state access space to the external 16-bit 2-state access space in normal transfer mode by cycle stealing. In figure 7.25, the transfer source (DSAR) is not aligned with a longword boundary and the transfer destination (DDAR) is aligned with a longword boundary. In figure 7.26, the transfer source (DSAR) is aligned with a longword boundary and the transfer destination (DDAR) is not aligned with a longword boundary. Rev. 2.00 Mar. 15, 2006 Page 186 of 754 REJ09B0199-0200 Section 7 DMA Controller (DMAC) DMA byte read cycle DMA word read cycle DMA byte read cycle DMA word write cycle DMA word write cycle DMA byte read cycle DMA word read cycle DMA byte read cycle DMA word write cycle DMA word write cycle B Address bus RD LHWR LLWR TEND 4m + 1 4m + 2 4m + 4 4n 4n +2 4m + 5 4m + 6 4m + 8 4n + 4 4n + 6 Bus released Bus released Last transfer cycle Bus released m and n are integers. Figure 7.25 Example of Transfer in Normal Transfer Mode by Cycle Stealing (Transfer Source DSAR = Odd Address and Source Address Increment) DMA word read cycle DMA word read cycle DMA byte write cycle DMA word write cycle DMA byte write cycle DMA word read cycle DMA word read cycle DMA byte write cycle DMA word write cycle DMA byte write cycle B Address bus RD LHWR LLWR TEND 4m 4m + 2 4n + 5 4n + 6 4n + 8 4m + 4 4m + 6 4n + 1 4n + 2 4n + 4 Bus released Bus released Last transfer cycle Bus released m and n are integers. Figure 7.26 Example of Transfer in Normal Transfer Mode by Cycle Stealing (Transfer Destination DDAR = Odd Address and Destination Address Decrement) Rev. 2.00 Mar. 15, 2006 Page 187 of 754 REJ09B0199-0200 Section 7 DMA Controller (DMAC) (2) Normal Transfer Mode (Burst Mode) In burst mode, one byte, one word, or one longword of data continues to be transferred until the transfer end condition is satisfied. When a burst transfer starts, a transfer request from a channel having priority is suspended until the burst transfer is completed. In figure 7.27, the TEND signal output is enabled and data is transferred in words from the external 16-bit 2-state access space to the external 16-bit 2-state access space in normal transfer mode by burst access. DMA read cycle DMA write cycle DMA read cycle DMA write cycle DMA read cycle DMA write cycle B Address bus RD HHWR, HLWR LHWR, LLWR TEND Bus released Burst transfer Last transfer cycle Bus released High Figure 7.27 Example of Transfer in Normal Transfer Mode by Burst Access Rev. 2.00 Mar. 15, 2006 Page 188 of 754 REJ09B0199-0200 Section 7 DMA Controller (DMAC) (3) Block Transfer Mode In block transfer mode, the bus is released every time a 1-block size of transfers at a single transfer request is completed. In figure 7.28, the TEND signal output is enabled and data is transferred in words from the external 16-bit 2-state access space to the external 16-bit 2-state access space in block transfer mode. DMA read cycle B Address bus RD LHWR, LLWR TEND Bus released Block transfer Bus released Last block transfer cycle Bus released DMA write cycle DMA read cycle DMA write cycle DMA read cycle DMA write cycle DMA read cycle DMA write cycle Figure 7.28 Example of Transfer in Block Transfer Mode Rev. 2.00 Mar. 15, 2006 Page 189 of 754 REJ09B0199-0200 Section 7 DMA Controller (DMAC) (4) Activation Timing by DREQ Falling Edge Figure 7.29 shows an example of normal transfer mode activated by the DREQ signal falling edge. The DREQ signal is sampled every cycle from the next rising edge of the B signal immediately after the DTE bit write cycle. When a low level of the DREQ signal is detected while a transfer request by the DREQ signal is enabled, a transfer request is held in the DMAC. When the DMAC is activated, the transfer request is cleared and starts detecting a high level of the DREQ signal for falling edge detection. If a high level of the DREQ signal has been detected until completion of the DMA write cycle, receiving the next transfer request resumes and then a low level of the DREQ signal is detected. This operation is repeated until the transfer is completed. DMA read cycle DMA write cycle DMA read cycle DMA write cycle Bus released Bus released Bus released B DREQ Address bus DMA operation Wait Transfer source Transfer destination Transfer source Transfer destination Read Write Wait Read Write Wait Channel Request Duration of transfer request disabled Request Duration of transfer request disabled Min. of 3 cycles Min. of 3 cycles [1] [2] [3] [4] [5] [6] [7] Transfer request enable resumed [1] Transfer request enable resumed After DMA transfer request is enabled, a low level of the DREQ signal is detected at the rising edge of the B signal and a transfer request is held. [2][5] The DMAC is activated and the transfer request is cleared. [3][6] A DMA cycle is started and sampling the DREQ signal at the rising edge of the B signal is started to detect a high level of the DREQ signal. [4][7] When a high level of the DREQ signal has been detected, transfer request enable is resumed after completion of the write cycle. (A low level of the DREQ signal is detected at the rising edge of the B signal and a transfer request is held. This is the same as [1].) Figure 7.29 Example of Transfer in Normal Transfer Mode Activated by DREQ Falling Edge Rev. 2.00 Mar. 15, 2006 Page 190 of 754 REJ09B0199-0200 Section 7 DMA Controller (DMAC) (5) Activation Timing by DREQ Low Level Figure 7.30 shows an example of normal transfer mode activated by the DREQ signal low level. The DREQ signal is sampled every cycle from the next rising edge of the B signal immediately after the DTE bit write cycle. When a low level of the DREQ signal is detected while a transfer request by the DREQ signal is enabled, a transfer request is held in the DMAC. When the DMAC is activated, the transfer request is cleared. Receiving the next transfer request resumes after completion of the write cycle and then a low level of the DREQ signal is detected. This operation is repeated until the transfer is completed. DMA read cycle DMA write cycle DMA read cycle DMA write cycle Bus released B Bus released Bus released DREQ Address bus DMA operation Wait Read Transfer source Transfer destination Transfer source Transfer destination Write Wait Read Write Wait Channel Request Duration of transfer request disabled Request Duration of transfer request disabled Min. of 3 cycles Min. of 3 cycles [1] [2] [3] [4] [5] [6] [7] Transfer request enable resumed [1] Transfer request enable resumed After DMA transfer request is enabled, a low level of the DREQ signal is detected at the rising edge of the B signal and a transfer request is held. [2][5] The DMAC is activated and the transfer request is cleared. [3][6] A DMA cycle is started. [4][7] Transfer request enable is resumed after completion of the write cycle. (A low level of the DREQ signal is detected at the rising edge of the B signal and a transfer request is held. This is the same as [1].) Figure 7.30 Example of Transfer in Normal Transfer Mode Activated by DREQ Low Level Rev. 2.00 Mar. 15, 2006 Page 191 of 754 REJ09B0199-0200 Section 7 DMA Controller (DMAC) Figure 7.31 shows an example of block transfer mode activated by the DREQ signal low level. The DREQ signal is sampled every cycle from the next rising edge of the B signal immediately after the DTE bit write cycle. When a low level of the DREQ signal is detected while a transfer request by the DREQ signal is enabled, a transfer request is held in the DMAC. When the DMAC is activated, the transfer request is cleared. Receiving the next transfer request resumes after completion of the write cycle and then a low level of the DREQ signal is detected. This operation is repeated until the transfer is completed. 1-block transfer Bus released B DMA read cycle DMA write cycle Bus released 1-block transfer DMA read cycle DMA write cycle Bus released DREQ Address bus DMA operation Wait Read Transfer source Transfer destination Transfer source Transfer destination Write Wait Read Write Wait Channel Request Duration of transfer request disabled Request Duration of transfer request disabled Min. of 3 cycles Min. of 3 cycles [1] [2] [3] [4] [5] [6] [7] Transfer request enable resumed [1] Transfer request enable resumed After DMA transfer request is enabled, a low level of the DREQ signal is detected at the rising edge of the B signal and a transfer request is held. [2][5] The DMAC is activated and the transfer request is cleared. [3][6] A DMA cycle is started. [4][7] Transfer request enable is resumed after completion of the write cycle. (A low level of the DREQ signal is detected at the rising edge of the B signal and a transfer request is held. This is the same as [1].) Figure 7.31 Example of Transfer in Block Transfer Mode Activated by DREQ Low Level Rev. 2.00 Mar. 15, 2006 Page 192 of 754 REJ09B0199-0200 Section 7 DMA Controller (DMAC) (6) Activation Timing by DREQ Low Level with NRD = 1 When the NRD bit in DMDR is set to 1, the timing of receiving the next transfer request is delayed for one cycle. Figure 7.32 shows an example of normal transfer mode activated by the DREQ signal low level with NRD = 1. The DREQ signal is sampled every cycle from the next rising edge of the B signal immediately after the DTE bit write cycle. When a low level of the DREQ signal is detected while a transfer request by the DREQ signal is enabled, a transfer request is held in the DMAC. When the DMAC is activated, the transfer request is cleared. Receiving the next transfer request resumes after completion of the write cycle and then a low level of the DREQ signal is detected. This operation is repeated until the transfer is completed. DMA read cycle DMA read cycle DMA read cycle DMA read cycle Bus released Bus released Bus released B DREQ Transfer source Transfer destination Transfer source Transfer destination Address bus Channel Request Duration of transfer request disabled Duration of transfer request disabled which is extended by NRD Request Duration of transfer request disabled Duration of transfer request disabled which is extended by NRD Min. of 3 cycles Min. of 3 cycles [1] [2] [3] [4] [5] [6] [7] Transfer request enable resumed Transfer request enable resumed [1] After DMA transfer request is enabled, a low level of the DREQ signal is detected at the rising edge of the B signal and a transfer request is held. [2][5] The DMAC is activated and the transfer request is cleared. [3][6] A DMA cycle is started. [4][7] Transfer request enable is resumed one cycle after completion of the write cycle. (A low level of the DREQ signal is detected at the rising edge of the B signal and a transfer request is held. This is the same as [1].) Figure 7.32 Example of Transfer in Normal Transfer Mode Activated by DREQ Low Level with NRD = 1 Rev. 2.00 Mar. 15, 2006 Page 193 of 754 REJ09B0199-0200 Section 7 DMA Controller (DMAC) 7.4.11 (1) Bus Cycles in Single Address Mode Single Address Mode (Read and Cycle Stealing) In single address mode, one byte, one word, or one longword of data is transferred at a single transfer request and after the transfer the bus is released temporarily. One bus cycle or more by the CPU or DTC are executed in the bus released cycles. In figure 7.33, the TEND signal output is enabled and data is transferred in bytes from the external 8-bit 2-state access space to the external device in single address mode (read). DMA read cycle B Address bus RD DACK TEND Bus released Bus released Bus released Bus Last transfer Bus released released cycle DMA read cycle DMA read cycle DMA read cycle Figure 7.33 Example of Transfer in Single Address Mode (Byte Read) Rev. 2.00 Mar. 15, 2006 Page 194 of 754 REJ09B0199-0200 Section 7 DMA Controller (DMAC) (2) Single Address Mode (Write and Cycle Stealing) In single address mode, data of one byte, one word, or one longword is transferred at a single transfer request and after the transfer the bus is released temporarily. One bus cycle or more by the CPU are executed in the bus released cycles. In figure 7.34, the TEND signal output is enabled and data is transferred in bytes from the external 8-bit 2-state access space to the external device in single address mode (write). DMA write cycle B DMA write cycle DMA write cycle DMA write cycle Address bus HHWR, HLWR LLWR DACK TEND Bus released Bus released Bus released Last transfer Bus Bus cycle released released Figure 7.34 Example of Transfer in Single Address Mode (Byte Write) Rev. 2.00 Mar. 15, 2006 Page 195 of 754 REJ09B0199-0200 Section 7 DMA Controller (DMAC) (3) Activation Timing by DREQ Falling Edge Figure 7.35 shows an example of single address mode activated by the DREQ signal falling edge. The DREQ signal is sampled every cycle from the next rising edge of the B signal immediately after the DTE bit write cycle. When a low level of the DREQ signal is detected while a transfer request by the DREQ signal is enabled, a transfer request is held in the DMAC. When the DMAC is activated, the transfer request is cleared and starts detecting a high level of the DREQ signal for falling edge detection. If a high level of the DREQ signal has been detected until completion of the single cycle, receiving the next transfer request resumes and then a low level of the DREQ signal is detected. This operation is repeated until the transfer is completed. Bus released B DMA single cycle Bus released DMA single cycle Bus released DREQ Address bus Transfer source/ Transfer destination Transfer source/ Transfer destination DACK DMA operation Wait Single Wait Single Wait Channel Request Duration of transfer request disabled Request Duration of transfer request disabled Min. of 3 cycles [1] [2] [3] [4] Min. of 3 cycles [5] [6] [7] Transfer request enable resumed [1] Transfer request enable resumed After DMA transfer request is enabled, a low level of the DREQ signal is detected at the rising edge of the B signal and a transfer request is held. [2][5] The DMAC is activated and the transfer request is cleared. [3][6] A DMA cycle is started and sampling the DREQ signal at the rising edge of the B signal is started to detect a high level of the DREQ signal. [4][7] When a high level of the DREQ signal has been detected, transfer enable is resumed after completion of the write cycle. (A low level of the DREQ signal is detected at the rising edge of the B signal and a transfer request is held. This is the same as [1].) Figure 7.35 Example of Transfer in Single Address Mode Activated by DREQ Falling Edge Rev. 2.00 Mar. 15, 2006 Page 196 of 754 REJ09B0199-0200 Section 7 DMA Controller (DMAC) (4) Activation Timing by DREQ Low Level Figure 7.36 shows an example of normal transfer mode activated by the DREQ signal low level. The DREQ signal is sampled every cycle from the next rising edge of the B signal immediately after the DTE bit write cycle. When a low level of the DREQ signal is detected while a transfer request by the DREQ signal is enabled, a transfer request is held in the DMAC. When the DMAC is activated, the transfer request is cleared. Receiving the next transfer request resumes after completion of the single cycle and then a low level of the DREQ signal is detected. This operation is repeated until the transfer is completed. Bus released B DMA single cycle Bus released DMA single cycle Bus released DREQ Address bus DACK DMA operation Transfer source/ Transfer destination Transfer source/ Transfer destination Wait Single Wait Single Wait Channel Request Duration of transfer request disabled Request Duration of transfer request disabled Min. of 3 cycles Min. of 3 cycles [1] [2] [3] [4] [5] [6] [7] Transfer request enable resumed [1] Transfer request enable resumed After DMA transfer request is enabled, a low level of the DREQ signal is detected at the rising edge of the B signal and a transfer request is held. [2][5] The DMAC is activated and the transfer request is cleared. [3][6] A DMA cycle is started. [4][7] Transfer request enable is resumed after completion of the single cycle. (A low level of the DREQ signal is detected at the rising edge of the B signal and a transfer request is held. This is the same as [1].) Figure 7.36 Example of Transfer in Single Address Mode Activated by DREQ Low Level Rev. 2.00 Mar. 15, 2006 Page 197 of 754 REJ09B0199-0200 Section 7 DMA Controller (DMAC) (5) Activation Timing by DREQ Low Level with NRD = 1 When the NRD bit in DMDR is set to 1, the timing of receiving the next transfer request is delayed for one cycle. Figure 7.37 shows an example of single address mode activated by the DREQ signal low level with NRD = 1. The DREQ signal is sampled every cycle from the next rising edge of the B signal immediately after the DTE bit write cycle. When a low level of the DREQ signal is detected while a transfer request by the DREQ signal is enabled, a transfer request is held in the DMAC. When the DMAC is activated, the transfer request is cleared. Receiving the next transfer request resumes after one cycle of the transfer request duration inserted by NRD = 1 on completion of the single cycle and then a low level of the DREQ signal is detected. This operation is repeated until the transfer is completed. Bus released B DMA single cycle Bus released DMA single cycle Bus released DREQ Address bus Transfer source/ Transfer destination Transfer source/ Transfer destination Channel Request Duration of transfer request disabled which is extended by NRD Duration of transfer Request request disabled Min. of 3 cycles Duration of transfer request disabled which is extended by NRD Duration of transfer request disabled Min. of 3 cycles [1] [2] [3] [4] [5] [6] [7] Transfer request enable resumed [1] Transfer request enable resumed After DMA transfer request is enabled, a low level of the DREQ signal is detected at the rising edge of the B signal and a transfer request is held. [2][5] The DMAC is activated and the transfer request is cleared. [3][6] A DMA cycle is started. [4][7] Transfer request enable is resumed one cycle after completion of the single cycle. (A low level of the DREQ signal is detected at the rising edge of the B signal and a transfer request is held. This is the same as [1].) Figure 7.37 Example of Transfer in Single Address Mode Activated by DREQ Low Level with NRD = 1 Rev. 2.00 Mar. 15, 2006 Page 198 of 754 REJ09B0199-0200 Section 7 DMA Controller (DMAC) 7.5 DMA Transfer End Operations on completion of a transfer differ according to the transfer end condition. DMA transfer completion is indicated that the DTE and ACT bits in DMDR are changed from 1 to 0. (1) Transfer End by DTCR Change from 1, 2, or 4, to 0 When DTCR is changed from 1, 2, or 4 to 0, a DMA transfer for the channel is completed. The DTE bit in DMDR is cleared to 0 and the DTIF bit in DMDR is set to 1. At this time, when the DTIE bit in DMDR is set to 1, a transfer end interrupt by the transfer counter is requested. When the DTCR value is 0 before the transfer, the transfer is not stopped. (2) Transfer End by Transfer Size Error Interrupt When the following conditions are satisfied while the TSEIE bit in DMDR is set to 1, a transfer size error occurs and a DMA transfer is terminated. At this time, the DTE bit in DMR is cleared to 0 and the ESIF bit in DMDR is set to 1. * In normal transfer mode and repeat transfer mode, when the next transfer is requested while a transfer is disabled due to the DTCR value less than the data access size * In block transfer mode, when the next transfer is requested while a transfer is disabled due to the DTCR value less than the block size When the TSEIE bit in DMDR is cleared to 0, data is transferred until the DTCR value reaches 0. A transfer size error is not generated. Operation in each transfer mode is shown below. * In normal transfer mode and repeat transfer mode, when the DTCR value is less than the data access size, data is transferred in bytes * In block transfer mode, when the DTCR value is less than the block size, the specified size of data in DTCR is transferred instead of transferring the block size of data. The transfer is performed in bytes. (3) Transfer End by Repeat Size End Interrupt In repeat transfer mode, when the next transfer is requested after completion of a 1-repeat size data transfer while the RPTIE bit in DACR is set to 1, a repeat size end interrupt is requested. When the interrupt is requested to complete DMA transfer, the DTE bit in DMDR is cleared to 0 and the ESIF bit in DMDR is set to 1. Under this condition, setting the DTE bit to 1 resumes the transfer. In block transfer mode, when the next transfer is requested after completion of a 1-block size data transfer, a repeat size end interrupt can be requested. Rev. 2.00 Mar. 15, 2006 Page 199 of 754 REJ09B0199-0200 Section 7 DMA Controller (DMAC) (4) Transfer End by Interrupt on Extended Repeat Area Overflow When an overflow on the extended repeat area occurs while the extended repeat area is specified and the SARIE or DARIE bit in DACR is set to 1, an interrupt by an extended repeat area overflow is requested. When the interrupt is requested, the DMA transfer is terminated, the DTE bit in DMDR is cleared to 0, and the ESIF bit in DMDR is set to 1. In dual address mode, even if an interrupt by an extended repeat area overflow occurs during a read cycle, the following write cycle is performed. In block transfer mode, even if an interrupt by an extended repeat area overflow occurs during a 1block transfer, the remaining data is transferred. The transfer is not terminated by an extended repeat area overflow interrupt unless the current transfer is complete. (5) Transfer End by Clearing DTE Bit in DMDR When the DTE bit in DMDR is cleared to 0 by the CPU, a transfer is completed after the current DMA cycle and a DMA cycle in which the transfer request is accepted are completed. In block transfer mode, a DMA transfer is completed after 1-block data is transferred. (6) Transfer End by NMI Interrupt When an NMI interrupt is requested, the DTE bits for all the channels are cleared to 0 and the ERRF bit in DMDR_0 is set to 1. When an NMI interrupt is requested during a DMA transfer, the transfer is forced to stop. To perform DMA transfer after an NMI interrupt is requested, clear the ERRF bit to 0 and then set the DTE bits for the channels to 1. The transfer end timings after an NMI interrupt is requested are shown below. (a) Normal Transfer Mode and Repeat Transfer Mode In dual address mode, a DMA transfer is completed after completion of the write cycle for one transfer unit. In single address mode, a DMA transfer is completed after completion of the bus cycle for one transfer unit. (b) Block Transfer Mode A DMA transfer is forced to stop. Since a 1-block size of transfers is not completed, operation is not guaranteed. In dual address mode, the write cycle corresponding to the read cycle is performed. This is similar to (a) in normal transfer mode. Rev. 2.00 Mar. 15, 2006 Page 200 of 754 REJ09B0199-0200 Section 7 DMA Controller (DMAC) (7) Transfer End by Address Error When an address error occurs, the DTE bits for all the channels are cleared to 0 and the ERRF bit in DMDR_0 is set to 1. When an address error occurs during a DMA transfer, the transfer is forced to stop. To perform a DMA transfer after an address error occurs, clear the ERRF bit to 0 and then set the DTE bits for the channels. The transfer end timing after an address error is the same as that after an NMI interrupt. (8) Transfer End by Hardware Standby Mode or Reset The DMAC is initialized by a reset and a transition to the hardware standby mode. A DMA transfer is not guaranteed. 7.6 7.6.1 Relationship among DMAC and Other Bus Masters CPU Priority Control Function Over DMAC The CPU priority control function over DMAC can be used according to the CPU priority control register (CPUPCR) setting. For details, see section 5.7, CPU Priority Control Function Over DTC and DMAC. The priority level of the DMAC is specified by bits DMAP2 to DMAP0 and can be specified for each channel. The priority level of the CPU is specified by bits CPUP2 to CPUP0. The value of bits CPUP2 to CPUP0 is updated according to the exception handling priority. If the CPU priority control is enabled by the CPUPCE bit in CPUPCR, when the CPU has priority over the DMAC, a transfer request for the corresponding channel is masked and the transfer is not activated. When another channel has priority over or the same as the CPU, a transfer request is received regardless of the priority between channels and the transfer is activated. If the priority level of the transfer request masked by the CPU priority control function is changed or the CPU priority is changed, the transfer request may be received and the transfer is started. When the CPUPCE bit is cleared to 0, it is regarded as the lowest priority. Transfer requests masked are suspended. If a transfer request is suspended, it is cleared by clearing the DTE bit to 0. Rev. 2.00 Mar. 15, 2006 Page 201 of 754 REJ09B0199-0200 Section 7 DMA Controller (DMAC) 7.6.2 Bus Arbitration among DMAC and Other Bus Masters When DMA transfer cycles are consecutively performed, bus cycles of other bus masters may be inserted between the transfer cycles. The DMAC can release the bus temporarily to pass the bus to other bus masters. The consecutive DMA transfer cycles may not be divided according to the transfer mode settings to achieve high-speed access. The read and write cycles of a DMA transfer are not separated. Refreshing, external bus release, and on-chip bus master (CPU and DTC) cycles are not inserted between the read and write cycles of a DMA transfer. In block transfer mode and an auto request transfer by burst access, bus cycles of the DMA transfer are consecutively performed. For this duration, since the DMAC has priority over the CPU and DTC, accesses to the external space is suspended (the IBCCS bit in the bus control register 2 (BCR2) is cleared to 0). When the bus is passed to another channel or an auto request transfer by cycle stealing, bus cycles of the DMAC and on-chip bus master are performed alternatively. When the arbitration function among the DMAC and on-chip bus masters is enabled by setting the IBCCS bit in BCR2, the bus is used alternatively except the bus cycles which are not separated. For details, see section 6, Bus Controller (BSC). A conflict may occur between external space access of the DMAC and a refresh cycle or an external bus release cycle. Even if a burst or block transfer is performed by the DMAC, the transfer is stopped temporarily and a cycle of refresh or external bus release is inserted by the BSC (when the DTC and CPU external access does not have priority over a DMAC transfer, the transfer is not operated until the DMAC releases the bus). In dual address mode, the DMAC releases the external bus after the external space write cycle. Since the read and write cycles are not separated, the bus is not released. An internal space (on-chip memory and internal I/O registers) access of the DMAC and an external bus release cycle may be performed at the same time. Rev. 2.00 Mar. 15, 2006 Page 202 of 754 REJ09B0199-0200 Section 7 DMA Controller (DMAC) 7.7 Interrupt Sources The DMAC interrupt sources are a transfer end interrupt by the transfer counter and a transfer escape end interrupt which is generated when a transfer is terminated before the transfer counter reaches 0. Table 7.6 shows interrupt sources and priority. Table 7.6 Abbr. DMTEND0 DMTEND1 DMTEND2 DMTEND3 DMEEND0 Interrupt Sources and Priority Interrupt Sources Transfer end interrupt by channel 0 transfer counter Transfer end interrupt by channel 1 transfer counter Transfer end interrupt by channel 2 transfer counter Transfer end interrupt by channel 3 transfer counter Interrupt by channel 0 transfer size error Interrupt by channel 0 repeat size end Interrupt by channel 0 extended repeat area overflow on source address Interrupt by channel 0 extended repeat area overflow on destination address Priority High DMEEND1 Interrupt by channel 1 transfer size error Interrupt by channel 1 repeat size end Interrupt by channel 1 extended repeat area overflow on source address Interrupt by channel 1 extended repeat area overflow on destination address DMEEND2 Interrupt by channel 2 transfer size error Interrupt by channel 2 repeat size end Interrupt by channel 2 extended repeat area overflow on source address Interrupt by channel 2 extended repeat area overflow on destination address DMEEND3 Interrupt by channel 3 transfer size error Interrupt by channel 3 repeat size end Interrupt by channel 3 extended repeat area overflow on source address Interrupt by channel 3 extended repeat area overflow on destination address Low Each interrupt is enabled or disabled by the DTIE and ESIE bits in DMDR for the corresponding channel. A DMTEND interrupt is generated by the combination of the DTIF and DTIE bits in DMDR. A DMEEND interrupt is generated by the combination of the ESIF and ESIE bits in DMDR. The DMEEND interrupt sources are not distinguished. The priority among channels are decided by the interrupt controller and it is shown in table 7.6. For details, see section 5, Interrupt Controller. Rev. 2.00 Mar. 15, 2006 Page 203 of 754 REJ09B0199-0200 Section 7 DMA Controller (DMAC) Each interrupt source is specified by the interrupt enable bit in the register for the corresponding channel. A transfer end interrupt by the transfer counter, a transfer size error interrupt, a repeat size end interrupt, an interrupt by an extended repeat area overflow on the source address, and an interrupt by an extended repeat area overflow on the destination address are enabled or disabled by the DTIE bit in DMDR, the TSEIE bit in DMDR, the RPTIE bit in DACR, SARIE bit in DACR, and the DARIE bit in DACR, respectively. A transfer end interrupt by the transfer counter is generated when the DTIF bit in DMDR is set to 1. The DTIF bit is set to 1 when DTCR becomes 0 by a transfer while the DTIE bit in DMDR is set to 1. An interrupt other than the transfer end interrupt by the transfer counter is generated when the ESIF bit in DMDR is set to 1. The ESIF bit is set to 1 when the conditions are satisfied by a transfer while the enable bit is set to 1. A transfer size error interrupt is generated when the next transfer cannot be performed because the DTCR value is less than the data access size, meaning that the data access size of transfers cannot be performed. In block transfer mode, the block size is compared with the DTCR value for transfer error decision. A repeat size end interrupt is generated when the next transfer is requested after completion of the repeat size of transfers in repeat transfer mode. Even when the repeat area is not specified in the address register, the transfer can be stopped periodically according to the repeat size. At this time, when a transfer end interrupt by the transfer counter is generated, the ESIF bit is set to 1. An interrupt by an extended repeat area overflow on the source and destination addresses is generated when the address exceeds the extended repeat area (overflow). At this time, when a transfer end interrupt by the transfer counter, the ESIF bit is set to 1. Figure 7.38 is a block diagram of interrupts and interrupt flags. To clear an interrupt, clear the DTIF or ESIF bit in DMDR to 0 in the interrupt handling routine or continue the transfer by setting the DTE bit in DMDR after setting the register. Figure 7.39 shows procedure to resume the transfer by clearing a interrupt. Rev. 2.00 Mar. 15, 2006 Page 204 of 754 REJ09B0199-0200 Section 7 DMA Controller (DMAC) TSIE bit DMAC is activated in transfer size error state RPTIE bit DMAC is activated after BKSZ bits are changed from 1 to 0 SARIE bit Extended repeat area overflow occurs in source address DARIE bit Extended repeat area overflow occurs in destination address DTIE bit DTIF bit [Setting condition] When DTCR becomes 0 and transfer ends ESIE bit ESIF bit Transfer escape end interrupt Transfer end interrupt Setting condition is satisfied Figure 7.38 Interrupt and Interrupt Sources Transfer end interrupt handling routine Consecutive transfer processing Registers are specified DTE bit is set to 1 Interrupt handling routine ends (RTE instruction executed) [1] [2] [3] Transfer resumed after interrupt handling routine DTIF and ESIF bits are cleared to 0 Interrupt handling routine ends Registers are specified DTE bit is set to 1 Transfer resume processing end [4] [5] [6] [7] Transfer resume processing end [1] Specify the values in the registers such as transfer counter and address register. [2] Set the DTE bit in DMDR to 1 to resume DMA operation. Setting the DTE bit to 1 automatically clears the DTIF or ESIF bit in DMDR to 0 and an interrupt source is cleared. [3] End the interrupt handling routine by the RTE instruction. [4] Read that the DTIF or the ESIF bit in DMDR = 1 and then write 0 to the bit. [5] Complete the interrupt handling routine and clear the interrupt mask. [6] Specify the values in the registers such as transfer counter and address register. [7] Set the DTE bit to 1 to resume DMA operation. Figure 7.39 Procedure Example of Resuming Transfer by Clearing Interrupt Source Rev. 2.00 Mar. 15, 2006 Page 205 of 754 REJ09B0199-0200 Section 7 DMA Controller (DMAC) 7.8 Notes on Usage 1. DMAC Register Access During Operation Except for clearing the DTE bit in DMDR, the settings for channels being transferred (including waiting state) must not be changed. The register settings must be changed during the transfer prohibited state. 2. Settings of Module Stop Function The DMAC operation can be enabled or disabled by the module stop control register. The DMAC is enabled by the initial value. Setting bit MSTPA13 in MSTPCRA stops the clock supplied to the DMAC and the DMAC enters the module stop state. However, when a transfer for a channel is enabled or when an interrupt is being requested, bit MSTPA13 cannot be set to 1. Clear the DTE bit to 0, clear the DTIF or DTIE bit in DMDR to 0, and then set bit MSTPA13. When the clock is stopped, the DMAC registers cannot be accessed. However, the following register settings are valid in the module stop state. Disable them before entering the module stop state, if necessary. TENDE bit in DMDR is 1 (the TEND signal output enabled) DACKE bit in DMDR is 1 (the DACK signal output enabled) 3. Activation by DREQ Falling Edge The DREQ falling edge detection is synchronized with the DMAC internal operation. A. Activation request waiting state: Waiting for detecting the DREQ low level. A transition to 2. is made. B. Transfer waiting state: Waiting for a DMAC transfer. A transition to 3. is made. C. Transfer prohibited state: Waiting for detecting the DREQ high level. A transition to 1. is made. After a DMAC transfer enabled, a transition to 1. is made. Therefore, the DREQ signal is sampled by low level detection at the first activation after a DMAC transfer enabled. 4. Acceptation of Activation Source At the beginning of an activation source reception, a low level is detected regardless of the setting of DREQ falling edge or low level detection. Therefore, if the DREQ signal is driven low before setting DMDR, the low level is received as a transfer request. When the DMAC is activated, clear the DREQ signal of the previous transfer. Rev. 2.00 Mar. 15, 2006 Page 206 of 754 REJ09B0199-0200 Section 8 Data Transfer Controller (DTC) Section 8 Data Transfer Controller (DTC) This LSI includes a data transfer controller (DTC). The DTC can be activated to transfer data by an interrupt request. 8.1 Features * Transfer possible over any number of channels: transfer for 69 activation sources Multiple data transfer enabled for one activation source (chain transfer) Chain transfer specifiable after data transfer (when the counter is 0) * Three transfer modes Normal/repeat/block transfer modes selectable Transfer source and destination addresses can be selected from increment/decrement/fixed * Short address mode or full address mode selectable Short address mode Transfer information is located on a 3-longword boundary The transfer source and destination addresses can be specified by 24 bits to select a 256Mbyte address space directly Full address mode Transfer information is located on a 4-longword boundary The transfer source and destination addresses can be specified by 32 bits to select a 4Gbyte address space directly * Size of data for data transfer can be specified as byte, word, or longword The bus cycle is divided if an odd address is specified for a word or longword transfer. The bus cycle is divided if address 4n + 2 is specified for a longword transfer. * A CPU interrupt can be requested for the interrupt that activated the DTC A CPU interrupt can be requested after one data transfer completion A CPU interrupt can be requested after the specified data transfer completion * Activation by software is possible Read skip of the transfer information specifiable * Writeback skip executed for the fixed transfer source and destination addresses * Module stop mode specifiable Rev. 2.00 Mar. 15, 2006 Page 207 of 754 REJ09B0199-0200 Section 8 Data Transfer Controller (DTC) Figure 8.1 shows a block diagram of the DTC. The DTC transfer information can be allocated to the data area*. When the transfer information is allocated to the on-chip RAM, a 32-bit bus connects the DTC to the on-chip RAM, enabling 32-bit/1-state reading and writing of the DTC transfer information. Note: * When the transfer information is stored in the on-chip RAM, the RAME bit in SYSCR must be set to 1. Interrupt controller DTCERA to DTCERH DTC On-chip ROM On-chip RAM On-chip peripheral module Peripheral bus MRA Internal bus (32 bits) DTCCR Register control MRB DTC internal bus SAR DAR CRA Activation control CRB DTC activation request vector number CPU interrupt request Interrupt source clear request 8 Interrupt control External device (memory mapped) External bus External memory Bus interface Bus controller DTCVBR [Legend] MRA, MRB: SAR: DAR: CRA, CRB: DTCERA to DTCERH: DTCCR: DTCVBR: DTC mode registers A, B DTC source address register DTC destination address register DTC transfer count registers A, B DTC enable registers A to H DTC control register DTC vector base register REQ ACK Figure 8.1 Block Diagram of DTC Rev. 2.00 Mar. 15, 2006 Page 208 of 754 REJ09B0199-0200 Section 8 Data Transfer Controller (DTC) 8.2 Register Descriptions DTC has the following registers. * * * * * * DTC mode register A (MRA) DTC mode register B (MRB) DTC source address register (SAR) DTC destination address register (DAR) DTC transfer count register A (CRA) DTC transfer count register B (CRB) These six registers MRA, MRB, SAR, DAR, CRA, and CRB cannot be directly accessed by the CPU. The contents of these registers are stored in the data area as transfer information. When a DTC activation request occurs, the DTC reads a start address of transfer information that is stored in the data area according to the vector address, reads the transfer information, and transfers data. After the data transfer, it writes a set of updated transfer information back to the data area. * DTC enable registers A to H (DTCERA to DTCERH) * DTC control register (DTCCR) * DTC vector base register (DTCVBR) Registers DTCERA to DTCERH, DTCCR, and DTCVBR can be accessed directly by the CPU. Rev. 2.00 Mar. 15, 2006 Page 209 of 754 REJ09B0199-0200 Section 8 Data Transfer Controller (DTC) 8.2.1 DTC Mode Register A (MRA) MRA selects DTC operating mode. MRA cannot be accessed directly by the CPU. Bit Bit Name Initial Value R/W 7 MD1 Undefined -- 6 MD0 Undefined -- 5 Sz1 Undefined -- 4 Sz0 Undefined -- 3 SM1 Undefined -- 2 SM0 Undefined -- 1 -- 0 -- 0 -- 0 -- Bit 7 6 Initial Bit Name Value MD1 MD0 Undefined Undefined R/W Description DTC Mode 1 and 0 Specify DTC transfer mode. 00: Normal mode 01: Repeat mode 10: Block transfer mode 11: Setting prohibited 5 4 Sz1 Sz0 Undefined Undefined DTC Data Transfer Size 1 and 0 Specify the size of data to be transferred. 00: Byte-size transfer 01: Word-size transfer 10: Longword-size transfer 11: Setting prohibited 3 2 SM1 SM0 Undefined Undefined Source Address Mode 1 and 0 Specify an SAR operation after a data transfer. 0X: SAR is fixed (SAR writeback is skipped) 10: SAR is incremented after a transfer (by 1 when Sz1 and Sz0 = B'00; by 2 when Sz1 and Sz0 = B'01; by 4 when Sz1 and Sz0 = B'10) 11: SAR is decremented after a transfer (by 1 when Sz1 and Sz0 = B'00; by 2 when Sz1 and Sz0 = B'01; by 4 when Sz1 and Sz0 = B'10) 1, 0 All 0 Reserved The initial value should not be changed. [Legend] X: Don't care Rev. 2.00 Mar. 15, 2006 Page 210 of 754 REJ09B0199-0200 Section 8 Data Transfer Controller (DTC) 8.2.2 DTC Mode Register B (MRB) MRB selects DTC operating mode. MRB cannot be accessed directly by the CPU. Bit Bit Name Initial Value R/W 7 CHNE Undefined -- 6 CHNS Undefined -- 5 DISEL Undefined -- 4 DTS Undefined -- 3 DM1 Undefined -- 2 DM0 Undefined -- 1 -- 0 -- 0 -- 0 -- Bit 7 Bit Name CHNE Initial Value Undefined R/W Description DTC Chain Transfer Enable Specifies the chain transfer. For details, see 8.5.7, Chain Transfer. The chain transfer condition is selected by the CHNS bit. 0: Disables the chain transfer 1: Enables the chain transfer 6 CHNS Undefined DTC Chain Transfer Select Specifies the chain transfer condition. If the following transfer is a chain transfer, the completion check of the specified transfer count is not performed and activation source flag or DTCER is not cleared. 0: Chain transfer every time 1: Chain transfer only when transfer counter = 0 5 DISEL Undefined DTC Interrupt Select When this bit is set to 1, a CPU interrupt request is generated every time after a data transfer ends. When this bit is set to 0, a CPU interrupt request is only generated when the specified number of data transfer end. 4 DTS Undefined DTC Transfer Mode Select Specifies either the source or destination as repeat or block area during repeat or block transfer mode. 0: Specifies the destination as repeat or block area 1: Specifies the source as repeat or block area Rev. 2.00 Mar. 15, 2006 Page 211 of 754 REJ09B0199-0200 Section 8 Data Transfer Controller (DTC) Bit 3 2 Bit Name DM1 DM0 Initial Value Undefined Undefined R/W Description Destination Address Mode 1 and 0 Specify a DAR operation after a data transfer. 0X: DAR is fixed (DAR writeback is skipped) 10: DAR is incremented after a transfer (by 1 when Sz1 and Sz0 = B'00; by 2 when Sz1 and Sz0 = B'01; by 4 when Sz1 and Sz0 = B'10) 11: DAR is decremented after a transfer (by 1 when Sz1 and Sz0 = B'00; by 2 when Sz1 and Sz0 = B'01; by 4 when Sz1 and Sz0 = B'10) 1 0 0 0 Reserved The initial value should not be changed. [Legend] X: Don't care 8.2.3 DTC Source Address Register (SAR) SAR is a 32-bit register that designates the source address of data to be transferred by the DTC. In full address mode, 32 bits of SAR are valid. In short address mode, the lower 24 bits of SAR is valid and bits 31 to 24 are ignored. If a word or longword access is performed while an odd address is specified in SAR or if a longword access is performed while address 4n + 2 is specified in SAR, the bus cycle is divided into multiple cycles to transfer data. For details, see section 8.5.1, Bus Cycle Division. SAR cannot be accessed directly from the CPU. Rev. 2.00 Mar. 15, 2006 Page 212 of 754 REJ09B0199-0200 Section 8 Data Transfer Controller (DTC) 8.2.4 DTC Destination Address Register (DAR) DAR is a 32-bit register that designates the destination address of data to be transferred by the DTC. In full address mode, 32 bits of DAR are valid. In short address mode, the lower 24 bits of DAR is valid and bits 31 to 24 are ignored. If a word or longword access is performed while an odd address is specified in DAR or if a longword access is performed while address 4n + 2 is specified in DAR, the bus cycle is divided into multiple cycles to transfer data. For details, see section 8.5.1, Bus Cycle Division. DAR cannot be accessed directly from the CPU. 8.2.5 DTC Transfer Count Register A (CRA) CRA is a 16-bit register that designates the number of times data is to be transferred by the DTC. In normal transfer mode, CRA functions as a 16-bit transfer counter (1 to 65,536). It is decremented by 1 every time data is transferred, and bit DTCEn (n = 15 to 0) corresponding to the activation source is cleared and then an interrupt is requested to the CPU when the count reaches H'0000. The transfer count is 1 when CRA = H'0001, 65,535 when CRA = H'FFFF, and 65,536 when CRA = H'0000. In repeat transfer mode, CRA is divided into two parts: the upper eight bits (CRAH) and the lower eight bits (CRAL). CRAH holds the number of transfers while CRAL functions as an 8-bit transfer counter (1 to 256). CRAL is decremented by 1 every time data is transferred, and the contents of CRAH are sent to CRAL when the count reaches H'00. The transfer count is 1 when CRAH = CRAL = H'01, 255 when CRAH = CRAL = H'FF, and 256 when CRAH = CRAL = H'00. In block transfer mode, CRA is divided into two parts: the upper eight bits (CRAH) and the lower eight bits (CRAL). CRAH holds the block size while CRAL functions as an 8-bit block-size counter (1 to 256 for byte, word, or longword). CRAL is decremented by 1 every time a byte (word or longword) data is transferred, and the contents of CRAH are sent to CRAL when the count reaches H'00. The block size is 1 byte (word or longword) when CRAH = CRAL =H'01, 255 bytes (words or longwords) when CRAH = CRAL = H'FF, and 256 bytes (words or longwords) when CRAH = CRAL =H'00. CRA cannot be accessed directly from the CPU. Rev. 2.00 Mar. 15, 2006 Page 213 of 754 REJ09B0199-0200 Section 8 Data Transfer Controller (DTC) 8.2.6 DTC Transfer Count Register B (CRB) CRB is a 16-bit register that designates the number of times data is to be transferred by the DTC in block transfer mode. It functions as a 16-bit transfer counter (1 to 65,536) that is decremented by 1 every time data is transferred, and bit DTCEn (n = 15 to 0) corresponding to the activation source is cleared and then an interrupt is requested to the CPU when the count reaches H'0000. The transfer count is 1 when CRB = H'0001, 65,535 when CRB = H'FFFF, and 65,536 when CRB = H'0000. CRB is not available in normal and repeat modes and cannot be accessed directly by the CPU. 8.2.7 DTC Enable Registers A to H (DTCERA to DTCERH) DTCER which is comprised of eight registers, DTCERA to DTCERH, is a register that specifies DTC activation interrupt sources. The correspondence between interrupt sources and DTCE bits is shown in table 8.1. Use bit manipulation instructions such as BSET and BCLR to read or write a DTCE bit. If all interrupts are masked, multiple activation sources can be set at one time (only at the initial setting) by writing data after executing a dummy read on the relevant register. Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W 15 DTCE15 0 R/W 7 DTCE7 0 R/W 14 DTCE14 0 R/W 6 DTCE6 0 R/W 13 DTCE13 0 R/W 5 DTCE5 0 R/W 12 DTCE12 0 R/W 4 DTCE4 0 R/W 11 DTCE11 0 R/W 3 DTCE3 0 R/W 10 DTCE10 0 R/W 2 DTCE2 0 R/W 9 DTCE9 0 R/W 1 DTCE1 0 R/W 8 DTCE8 0 R/W 0 DTCE0 0 R/W Rev. 2.00 Mar. 15, 2006 Page 214 of 754 REJ09B0199-0200 Section 8 Data Transfer Controller (DTC) Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Name DTCE15 DTCE14 DTCE13 DTCE12 DTCE11 DTCE10 DTCE9 DTCE8 DTCE7 DTCE6 DTCE5 DTCE4 DTCE3 DTCE2 DTCE1 DTCE0 Initial Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Description DTC Activation Enable 15 to 0 Setting this bit to 1 specifies a relevant interrupt source to a DTC activation source. [Clearing conditions] * * When writing 0 to the bit to be cleared after reading 1 When the DISEL bit is 1 and one data transfer has ended * When the specified number of transfers have ended These bits are not cleared when the DISEL bit is 0 and the specified number of transfers have not ended Rev. 2.00 Mar. 15, 2006 Page 215 of 754 REJ09B0199-0200 Section 8 Data Transfer Controller (DTC) 8.2.8 DTC Control Register (DTCCR) DTCCR specifies DTC activation by software and transfer information read skip. Bit Bit Name Initial Value R/W 7 -- 0 R 6 -- 0 R 5 -- 0 R 4 RRS 0 R/W 3 RCHNE 0 R/W 2 -- 0 R 1 -- 0 R 0 ERR 0 R/(W)* Note: * Only 0 can be written to clear the flag. Bit 7 to 5 Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 4 RRS 0 R/W 3 RCHNE 0 R/W 2, 1 All 0 R DTC Transfer Information Read Skip Enable Controls the vector address read and transfer information read. A DTC vector number is always compared with the vector number for the previous activation. If the vector numbers match and this bit is set to 1, the DTC data transfer is started without reading a vector address and transfer information. If the previous DTC activation is a chain transfer, the vector address read and transfer information read are always performed. 0: Transfer read skip is not performed. 1: Transfer read skip is performed when the vector numbers match. Chain Transfer Enable After DTC Repeat Transfer Enables/disables the chain transfer while transfer counter (CRAL) is 0 in repeat transfer mode. In repeat transfer mode, the CRAH value is written to CRAL when CRAL is 0. Accordingly, chain transfer may not occur when CRAL is 0. If this bit is set to 1, the chain transfer is enabled when CRAH is written to CRAL. 0: Disables the chain transfer after repeat transfer 1: Enables the chain transfer after repeat transfer Reserved These bits are always read as 0 and cannot be modified. Rev. 2.00 Mar. 15, 2006 Page 216 of 754 REJ09B0199-0200 Section 8 Data Transfer Controller (DTC) Bit 0 Bit Name ERR Initial Value 0 R/W Description Indicates that an address error or an NMI interrupt occurs. If an address error or an NMI interrupt occurs, the DTC stops. 0: No interrupt occurs 1: An interrupt occurs [Clearing condition] * When writing 0 after reading 1 R/(W)* Transfer Stop Flag Note: * Only 0 can be written to clear this flag. 8.2.9 DTC Vector Base Register (DTCVBR) DTCVBR is a 32-bit register that specifies the base address for vector table address calculation. Bits 31 to 28 and bits 11 to 0 are fixed 0 and cannot be written to. The initial value of DTCVBR is H'00000000. Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 15 0 R 14 0 R 13 0 R 12 0 R/W 11 0 R/W 10 0 R/W 9 0 R/W 8 0 R/W 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 8.3 Activation Sources The DTC is activated by an interrupt request. The interrupt source is selected by DTCER. A DTC activation source can be selected by setting the corresponding bit in DTCER; the CPU interrupt source can be selected by clearing the corresponding bit in DTCER. At the end of a data transfer (or the last consecutive transfer in the case of chain transfer), the activation source interrupt flag or corresponding DTCER bit is cleared. Rev. 2.00 Mar. 15, 2006 Page 217 of 754 REJ09B0199-0200 Section 8 Data Transfer Controller (DTC) 8.4 Location of Transfer Information and DTC Vector Table Locate the transfer information in the data area. The start address of transfer information should be located at the address that is a multiple of four (4n). Otherwise, the lower two bits are ignored during access ([1:0] = B'00.) Transfer information can be located in either short address mode (three longwords) or full address mode (four longwords). The DTCMD bit in SYSCR specifies either short address mode (DTCMD = 1) or full address mode (DTCMD = 0). For details, see section 3.2.2, System Control Register (SYSCR). Transfer information located in the data area is shown in figure 8.2 The DTC reads the start address of transfer information from the vector table according to the activation source, and then reads the transfer information from the start address. Figure 8.3 shows correspondences between the DTC vector address and transfer information. Transfer information in short address mode Lower addresses Start address 0 MRA MRB Chain transfer CRA MRA MRB CRA 4 bytes CRA 4 bytes CRB 1 2 SAR DAR CRB SAR DAR CRB Transfer information for one transfer (3 longwords) Transfer information for the 2nd transfer in chain transfer (3 longwords) Chain transfer 3 Start address 0 Transfer information in full address mode Lower addresses 1 2 3 Transfer information for one transfer (4 longwords) Reserved (0 write) MRA MRB SAR DAR CRA MRA MRB CRB Reserved (0 write) SAR DAR Transfer information for the 2nd transfer in chain transfer (4 longwords) Figure 8.2 Transfer Information on Data Area Rev. 2.00 Mar. 15, 2006 Page 218 of 754 REJ09B0199-0200 Section 8 Data Transfer Controller (DTC) Upper: DTCVBR Lower: H'400 + vector number x 4 DTC vector address +4 Vector table Transfer information (1) Transfer information (1) start address Transfer information (2) start address : : : Transfer information (n) start address 4 bytes Transfer information (n) : : : Transfer information (2) +4n Figure 8.3 Correspondence between DTC Vector Address and Transfer Information Rev. 2.00 Mar. 15, 2006 Page 219 of 754 REJ09B0199-0200 Section 8 Data Transfer Controller (DTC) Table 8.1 shows correspondence between the DTC activation source and vector address. Table 8.1 Interrupt Sources, DTC Vector Addresses, and Corresponding DTCEs Activation Source IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 IRQ8 IRQ9 IRQ10 IRQ11 IRQ12 IRQ13 IRQ14 IRQ15 A/D_0 A/D_1 TPU_0 Vector DTC Vector Number Address Offset DTCE*1 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 H'500 H'504 H'508 H'50C H'510 H'514 H'518 H'51C H'520 H'524 H'528 H'52C H'530 H'534 H'538 H'53C H'558 H'55C H'560 H'564 H'568 H'56C H'574 H'578 H'584 H'588 DTCEA15 DTCEA14 DTCEA13 DTCEA12 DTCEA11 DTCEA10 DTCEA9 DTCEA8 DTCEA7 DTCEA6 DTCEA5 DTCEA4 DTCEA3 DTCEA2 DTCEA1 DTCEA0 DTCEB15 DTCEB14 DTCEB13 DTCEB12 DTCEB11 DTCEB10 DTCEB9 DTCEB8 DTCEB7 DTCEB6 Low Priority High Origin of Activation Source External pin ADI0 86 (A/D_0 conversion end) ADI1 87 (A/D_1 conversion end) TGI0A TGI0B TGI0C TGI0D 88 89 90 91 93 94 97 98 TPU_1 TGI1A TGI1B TPU_2 TGI2A TGI2B Rev. 2.00 Mar. 15, 2006 Page 220 of 754 REJ09B0199-0200 Section 8 Data Transfer Controller (DTC) Origin of Activation Source TPU_3 Activation Source TGI3A TGI3B TGI3C TGI3D Vector DTC Vector 1 Number Address Offset DTCE* 101 102 103 104 106 107 110 111 128 129 130 131 136 137 138 139 157 158 161 162 164 165 166 167 169 170 173 174 177 178 179 180 H'594 H'598 H'59C H'5A0 H'5A8 H'5AC H'5B8 H'5BC H'600 H'604 H'608 H'60C H'620 H'624 H'628 H'62C H'674 H'678 H'684 H'688 H'690 H'694 H'698 H'69C H'6A4 H'6A8 H'6B4 H'6B8 H'6C4 H'6C8 H'6CC H'6D0 DTCEB5 DTCEB4 DTCEB3 DTCEB2 DTCEB1 DTCEB0 DTCEC15 DTCEC14 DTCEC5 DTCEC4 DTCEC3 DTCEC2 DTCED13 DTCED12 DTCED11 DTCED10 DTCEE15 DTCEE14 DTCEE13 DTCEE12 DTCEE11 DTCEE10 DTCEE9 DTCEE8 DTCEE7 DTCEE6 DTCEE5 DTCEE4 DTCEE3 DTCEE2 DTCEE1 DTCEE0 Priority High TPU_4 TPU_5 DMAC TGI4A TGI4B TGI5A TGI5B DMTEND0 DMTEND1 DMTEND2 DMTEND3 DMEEND0 DMEEND1 DMEEND2 DMEEND3 SCI_3 SCI_4 TPU_6 RXI3 TXI3 RXI4 TXI4 TGI6A TGI6B TGI6C TGI6D TPU_7 TGI7A TGI7B TPU_8 TGI8A TGI8B TPU_9 TGI9A TGI9B TGI9C TGI9D Low Rev. 2.00 Mar. 15, 2006 Page 221 of 754 REJ09B0199-0200 Section 8 Data Transfer Controller (DTC) Origin of Activation Source TPU_10 Activation Source TGI10A TGI10B Reserved for system use Reserved for system use TCI10V* 2 Vector DTC Vector 1 Number Address Offset DTCE* 182 183 184 185 186 188 189 H'6D8 H'6DC H'6E0 H'6E4 H'6E8 H'6F0 H'6F4 DTCEF15 DTCEF14 DTCEF13 DTCEF12 DTCEF11 DTCEF10 DTCEF9 Priority High TPU_11 TGI11A or reserved for system use TGI11B or reserved for system use Low Notes: 1. The DTCE bits with no corresponding interrupt are reserved, and the write value should always be 0. To leave software standby mode or all-module-clock-stop mode with an interrupt, write 0 to the corresponding DTCE bit. 2. TCI10V does not activate DTC. Rev. 2.00 Mar. 15, 2006 Page 222 of 754 REJ09B0199-0200 Section 8 Data Transfer Controller (DTC) 8.5 Operation The DTC stores transfer information in the data area. When activated, the DTC reads transfer information that is stored in the data area and transfers data on the basis of that transfer information. After the data transfer, it writes updated transfer information back to the data area. Since transfer information is in the data area, it is possible to transfer data over any required number of channels. There are three transfer modes: normal, repeat, and block. The DTC specifies the source address and destination address in SAR and DAR, respectively. After a transfer, SAR and DAR are incremented, decremented, or fixed independently. Table 8.2 shows the DTC transfer modes. Table 8.2 Transfer Mode Normal Repeat*1 Block*2 DTC Transfer Modes Size of Data Transferred at One Transfer Request 1 byte/word/longword 1 byte/word/longword Memory Address Increment or Decrement Transfer Count Incremented/decremented by 1, 2, or 4, 1 to 65536 or fixed Incremented/decremented by 1, 2, or 4, 1 to 256*3 or fixed Block size specified by CRAH (1 Incremented/decremented by 1, 2, or 4, 1 to 65536 to 256 bytes/words/longwords) or fixed Notes: 1. Either source or destination is specified to repeat area. 2. Either source or destination is specified to block area. 3. After transfer of the specified transfer count, initial state is recovered to continue the operation. Setting the CHNE bit in MRB to 1 makes it possible to perform a number of transfers with a single activation (chain transfer). Setting the CHNS bit in MRB to 1 can also be made to have chain transfer performed only when the transfer counter value is 0. Figure 8.4 shows a flowchart of DTC operation, and table 8.3 summarizes the chain transfer conditions (combinations for performing the second and third transfers are omitted). Rev. 2.00 Mar. 15, 2006 Page 223 of 754 REJ09B0199-0200 Section 8 Data Transfer Controller (DTC) Start Match & RRS = 1 Vector number comparison Not match | RRS = 0 Read DTC vector Next transfer Read transfer information Transfer data Update transfer information Update the start address of transfer information Write transfer information CHNE = 1 Yes No Transfer counter = 0 or DISEL = 1 Yes No CHNS = 0 Yes No Transfer counter = 0 Yes No DISEL = 1 No Yes Clear activation source flag Clear DTCER/request an interrupt to the CPU End Figure 8.4 Flowchart of DTC Operation Rev. 2.00 Mar. 15, 2006 Page 224 of 754 REJ09B0199-0200 Section 8 Data Transfer Controller (DTC) Table 8.3 Chain Transfer Conditions 1st Transfer 2nd Transfer Transfer 1 Counter* Not 0 0* 2 CHNE 0 0 0 1 CHNS 0 DISEL 0 0 1 CHNE 0 0 0 0 0 0 CHNS DISEL 0 0 1 Transfer 1 Counter* Not 0 0* 2 DTC Transfer Ends at 1st transfer Ends at 1st transfer Interrupt request to CPU Ends at 2nd transfer Ends at 2nd transfer Interrupt request to CPU Ends at 1st transfer Ends at 2nd transfer Ends at 2nd transfer Interrupt request to CPU 1 1 1 1 0 Not 0 0* 2 0 0 1 Not 0 0* 2 1 1 1 Not 0 Ends at 1st transfer Interrupt request to CPU Notes: 1. CRA in normal mode transfer, CRAL in repeat transfer mode, or CRB in block transfer mode 2. When the contents of the CRAH is written to the CRAL in repeat transfer mode 8.5.1 Bus Cycle Division When the address setting values in SAR and DAR do not match the boundary conditions of the transfer data size, the bus cycle is divided. Table 8.4 shows the relationship among, SAR, DAR, transfer data size, bus cycle divisions, and access data size. Figure 8.5 shows the bus cycle division example. Table 8.4 Number of Bus Cycle Divisions and Access Size Specified Data Size SAR and DAR Values Byte (B) Address 4n Address 2n + 1 Address 4n + 2 1 (B) 1 (B) 1 (B) Word (W) 1 (W) 2 (B-B) 1 (W) Longword (LW) 1 (LW) 3 (B-W-B) 2 (W-W) Rev. 2.00 Mar. 15, 2006 Page 225 of 754 REJ09B0199-0200 Section 8 Data Transfer Controller (DTC) [Example 1: When an odd address and even address are specified in SAR and DAR, respectively, and when the data size of transfer is specified as word] Clock DTC activation request DTC request R Address W B B W Vector read Transfer information Data transfer read Transfer information write [Example 2: When an odd address and address 4n are specified in SAR and DAR, respectively, and when the data size of transfer is specified as longword] Clock DTC activation request DTC request R Address W B W B L Vector read Transfer information read Data transfer Transfer information write [Example 3: When address 4n + 2 and address 4n are specified in SAR and DAR, respectively, and when the data size of transfer is specified as longword] Clock DTC activation request DTC request R Address W W W L Vector read Transfer information Data transfer read Transfer information write Figure 8.5 Bus Cycle Division Example Rev. 2.00 Mar. 15, 2006 Page 226 of 754 REJ09B0199-0200 Section 8 Data Transfer Controller (DTC) 8.5.2 Transfer Information Read Skip Function By setting the RRS bit of DTCCR, the vector address read and transfer information read can be skipped. The current DTC vector number is always compared with the vector number of previous activation. If the vector numbers match when RRS = 1, a DTC data transfer is performed without reading the vector address and transfer information. If the previous activation is a chain transfer, the vector address read and transfer information read are always performed. Figure 8.6 shows the transfer information read skip timing. To modify the vector table and transfer information, temporarily clear the RRS bit to 0, modify the vector table and transfer information, and then set the RRS bit to 1 again. When the RRS bit is cleared to 0, the stored vector number is deleted, and the updated vector table and transfer information are read at the next activation. Clock DTC activation request (1) (2) DTC request Transfer information read skip Address R W R W Vector read Transfer information Data Transfer information read transfer write Data Transfer information transfer write Note: Transfer information read is skipped when the activation sources of (1) and (2) (vector numbers) are the same while RRS = 1. Figure 8.6 Transfer Information Read Skip Timing Rev. 2.00 Mar. 15, 2006 Page 227 of 754 REJ09B0199-0200 Section 8 Data Transfer Controller (DTC) 8.5.3 Transfer Information Writeback Skip Function By specifying bit SM1 in MRA and bit DM1 in MRB to the fixed address mode, a part of transfer information will not be written back. This function is performed regardless of short or full address mode. Table 8.5 shows the transfer information writeback skip condition and writeback skipped registers. Note that the CRA and CRB are always written back regardless of the short or full address mode. In addition in full address mode, the writeback of the MRA and MRB are always skipped. Table 8.5 SM1 0 0 1 1 Transfer Information Writeback Skip Condition and Writeback Skipped Registers DM1 0 1 0 1 SAR Skipped Skipped Written back Written back DAR Skipped Written back Skipped Written back 8.5.4 Normal Transfer Mode In normal transfer mode, one operation transfers one byte, one word, or one longword of data. From 1 to 65,536 transfers can be specified. The transfer source and destination addresses can be specified as incremented, decremented, or fixed. When the specified number of transfers ends, an interrupt can be requested to the CPU. Table 8.6 lists the register function in normal transfer mode. Figure 8.7 shows the memory map in normal transfer mode. Table 8.6 Register SAR DAR CRA CRB Note: * Register Function in Normal Transfer Mode Function Source address Destination address Transfer count A Transfer count B Written Back Value Incremented/decremented/fixed* Incremented/decremented/fixed* CRA - 1 Not updated Transfer information writeback is skipped. Rev. 2.00 Mar. 15, 2006 Page 228 of 754 REJ09B0199-0200 Section 8 Data Transfer Controller (DTC) Transfer source data area Transfer destination data area SAR Transfer DAR Figure 8.7 Memory Map in Normal Transfer Mode 8.5.5 Repeat Transfer Mode In repeat transfer mode, one operation transfers one byte, one word, or one longword of data. By the DTS bit in MRB, either the source or destination can be specified as a repeat area. From 1 to 256 transfers can be specified. When the specified number of transfers ends, the transfer counter and address register specified as the repeat area is restored to the initial state, and transfer is repeated. The other address register is then incremented, decremented, or left fixed. In repeat transfer mode, the transfer counter (CRAL) is updated to the value specified in CRAH when CRAL becomes H'00. Thus the transfer counter value does not reach H'00, and therefore a CPU interrupt cannot be requested when DISEL = 0. Table 8.7 lists the register function in repeat transfer mode. Figure 8.8 shows the memory map in repeat transfer mode. Rev. 2.00 Mar. 15, 2006 Page 229 of 754 REJ09B0199-0200 Section 8 Data Transfer Controller (DTC) Table 8.7 Register Function in Repeat Transfer Mode Written Back Value Register Function SAR Source address CRAL is not 1 Incremented/decremented/fixed* CRAL is 1 DTS =0: Incremented/ decremented/fixed* DTS = 1: SAR initial value DTS = 0: DAR initial value DTS =1: Incremented/ decremented/fixed* DAR Destination address Incremented/decremented/fixed* CRAH CRAL CRB Note: * Transfer count storage Transfer count A Transfer count B CRAH CRAL - 1 Not updated CRAH CRAH Not updated Transfer information writeback is skipped. Transfer source data area (specified as repeat area) Transfer destination data area SAR Transfer DAR Figure 8.8 Memory Map in Repeat Transfer Mode (When Transfer Source is Specified as Repeat Area) Rev. 2.00 Mar. 15, 2006 Page 230 of 754 REJ09B0199-0200 Section 8 Data Transfer Controller (DTC) 8.5.6 Block Transfer Mode In block transfer mode, one operation transfers one block of data. Either the transfer source or the transfer destination is designated as a block area by the DTS bit in MRB. The block size is 1 to 256 bytes (1 to 256 words, or 1 to 256 longwords). When the transfer of one block ends, the block size counter (CRAL) and address register (SAR when DTS = 1 or DAR when DTS = 0) specified as the block area is restored to the initial state. The other address register is then incremented, decremented, or left fixed. From 1 to 65,536 transfers can be specified. When the specified number of transfers ends, an interrupt is requested to the CPU. Table 8.8 lists the register function in block transfer mode. Figure 8.9 shows the memory map in block transfer mode. Table 8.8 Register Function in Block Transfer Mode Written Back Value DTS =0: Incremented/decremented/fixed* DTS = 1: SAR initial value DAR CRAH CRAL CRB Note: * Destination address Block size storage Block size counter Block transfer counter DTS = 0: DAR initial value DTS =1: Incremented/decremented/fixed* CRAH CRAH CRB - 1 Register Function SAR Source address Transfer information writeback is skipped. Transfer source data area Transfer destination data area (specified as block area) SAR 1st block : : : Transfer Block area DAR Nth block Figure 8.9 Memory Map in Block Transfer Mode (When Transfer Destination is Specified as Block Area) Rev. 2.00 Mar. 15, 2006 Page 231 of 754 REJ09B0199-0200 Section 8 Data Transfer Controller (DTC) 8.5.7 Chain Transfer Setting the CHNE bit in MRB to 1 enables a number of data transfers to be performed consecutively in response to a single transfer request. Setting the CHNE and CHNS bits in MRB set to 1 enables a chain transfer only when the transfer counter reaches 0. SAR, DAR, CRA, CRB, MRA, and MRB, which define data transfers, can be set independently. Figure 8.10 shows the chain transfer operation. In the case of transfer with CHNE set to 1, an interrupt request to the CPU is not generated at the end of the specified number of transfers or by setting the DISEL bit to 1, and the interrupt source flag for the activation source and DTCER are not affected. In repeat transfer mode, setting the RCHNE bit in DTCCR and the CHNE and CHNS bits in MRB to 1 enables a chain transfer after transfer with transfer counter = 1 has been completed. Data area Transfer source data (1) Transfer information stored in user area Vector table Transfer destination data (1) DTC vector address Transfer information CHNE = 1 Transfer information CHNE = 0 Transfer source data (2) Transfer information start address Transfer destination data (2) Figure 8.10 Operation of Chain Transfer Rev. 2.00 Mar. 15, 2006 Page 232 of 754 REJ09B0199-0200 Section 8 Data Transfer Controller (DTC) 8.5.8 Operation Timing Figures 8.11 to 8.14 show the DTC operation timings. Clock DTC activation request DTC request Address R Vector read W Transfer information write Transfer Data transfer information read Figure 8.11 DTC Operation Timing (Example of Short Address Mode in Normal Transfer Mode or Repeat Transfer Mode) Clock DTC activation request DTC request Address R Vector read Transfer information read W R W Transfer information write Data transfer Figure 8.12 DTC Operation Timing (Example of Short Address Mode in Block Transfer Mode with Block Size of 2) Rev. 2.00 Mar. 15, 2006 Page 233 of 754 REJ09B0199-0200 Section 8 Data Transfer Controller (DTC) Clock DTC activation request DTC request Address R Vector read Transfer information read W Transfer information write Transfer information read R W Transfer information write Data transfer Data transfer Figure 8.13 DTC Operation Timing (Example of Short Address Mode in Chain Transfer) Clock DTC activation request DTC request Address R Vector read Transfer information read W Data Transfer information transfer write Figure 8.14 DTC Operation Timing (Example of Full Address Mode in Normal Transfer Mode or Repeat Transfer Mode) Rev. 2.00 Mar. 15, 2006 Page 234 of 754 REJ09B0199-0200 Section 8 Data Transfer Controller (DTC) 8.5.9 Number of DTC Execution Cycles Table 8.9 shows the execution status for a single DTC data transfer, and table 8.10 shows the number of cycles required for each execution. Table 8.9 DTC Execution Status Transfer Information Read J Transfer Information Write L Internal Operation N Mode Vector Read I Data Read L Data Write M Normal 1 Repeat 1 Block 1 transfer 0*1 4*2 0*1 4*2 0*1 4*2 3*3 0*1 3*3 0*1 3*3 0*1 3*2.3 2*4 3*2.3 2*4 3*2.3 2*4 1*5 1*5 1*5 3*6 3*6 3*P 6 * 2*7 2*7 7 1 1 3*6 3*6 3*P 6 * 2*7 2*7 7 1 1 1 1 1 0*1 0*1 0*1 2*P* 1*P 2*P* 1*P [Legend] P: Block size (CRAH and CRAL value) Notes: 1. When transfer information read is skipped 2. In full address mode operation 3. In short address mode operation 4. When the SAR or DAR is in fixed mode 5. When the SAR and DAR are in fixed mode 6. When a longword is transferred while an odd address is specified in the address register 7. When a word is transferred while an odd address is specified in the address register or when a longword is transferred while address 4n + 2 is specified P: Block size (initial setting of CRAH and CRAL) Rev. 2.00 Mar. 15, 2006 Page 235 of 754 REJ09B0199-0200 Section 8 Data Transfer Controller (DTC) Table 8.10 Number of Cycles Required for Each Execution State On- On- On-Chip Chip Chip I/O RAM ROM Registers 32 1 1 32 1 1 1 1 1 1 1 1 1 1 8 2 16 32 2 2 2 8 8 8 2 4 8 2 4 8 3 12 + 4m 12 + 4m 12 + 4m 3+m 4 + 2m 12 + 4m 3+m 4 + 2m 12 + 4m 1 8 2 4 4 4 2 2 4 2 2 4 Object to be Accessed Bus width Access cycles Execu- Vector read SI tion status External Devices 16 3 6 + 2m 6 + 2m 6 + 2m 3+m 3+m 6 + 2m 3+m 3+m 6 + 2m 2 2 2 2 2 2 2 2 2 2 32 3 3+m 3+m 3+m 3+m 3+m 3+m 3+m 3+m 3+m 2 4 8 2 4 8 2 2 4 2 2 4 2 2 2 2 2 2 Transfer information read SJ 1 Transfer information write Sk 1 Byte data read SL Word data read SL Longword data read SL Byte data write SM Word data write SM Longword data write SM Internal operation SN 1 1 1 1 1 1 [Legend] m: Number of wait cycles 0 to 7 (For details, see section 6, Bus Controller (BSC).) The number of execution cycles is calculated from the formula below. Note that means the sum of all transfers activated by one activation event (the number in which the CHNE bit is set to 1, plus 1). Number of execution cycles = I * SI + (J * SJ + K * SK + L * SL + M * SM) + N * SN 8.5.10 DTC Bus Release Timing The DTC requests the bus mastership to the bus arbiter when an activation request occurs. The DTC releases the bus after a vector read, transfer information read, a single data transfer, or transfer information writeback. The DTC does not release the bus during transfer information read, single data transfer, or transfer information writeback. 8.5.11 DTC Priority Level Control to the CPU The priority of the DTC activation sources over the CPU can be controlled by the CPU priority level specified by bits CPUP2 to CPUP0 in CPUPCR and the DTC priority level specified by bits DTCP2 to DTCP0. For details, see section 5, Interrupt Controller. Rev. 2.00 Mar. 15, 2006 Page 236 of 754 REJ09B0199-0200 Section 8 Data Transfer Controller (DTC) 8.6 8.6.1 DTC Usage Procedure Activation by Interrupt The procedure for using the DTC with interrupt activation is shown below. Activate DTC with an interrupt Set the RRS bit in DTCCR to 0 [1] [1] Setting the RRS bit in DTCCR resets the flag for the transfer information read skip. After this setting has been done, transfer information read skip is not performed in DTC activation. When the transfer information is updated, this setting should be done. [2] Locate the transfer information (MRA, MRB, SAR, DAR, CRA, and CRB) in the data area. For the procedure for setting the transfer information, see section 8.2, Register Descriptions. For the procedure for locating the transfer information, see 8.4, Location of Transfer Information and DTC Vector Table. [3] Set the start address of the transfer information to the DTC vector table. For the procedure for setting the transfer information to the DTC vector address, see section 8.4, Location of Transfer Information and DTC Vector Table. [4] By setting the RRS bit of DTCCR, the second and subsequent transfer information reads can be skipped when activating the DTC continuously by the same interrupts. Writing 1 to the RRS bit is always enabled. Note that if writing is performed during the DTC transfer, the RRS bit setting becomes effective in the next transmission. [5] Set the bit in DTCER which is relevant to an interrupt for the DTC activation. See table 8.1 for the correspondence between interrupt sources and DTCE bits. In the second and subsequent DTC transfers, the corresponding bit in DTCER may be set to 1. It is unnecessary to set the corresponding bit again. [6] Set the enable bit which specifies a relevant interrupt source to a DTC activation source. When an interrupt, which is to be an activation factor, is generated, DTC will be activated. For setting the enable bit for the interrupt source, see the procedure for setting the source module for activation. [7] After data has been transferred once, DTC clears the activation source flag and corresponding bit in DTCER, and generates an interrupt to the CPU. The operation after the transfer is decided according to the transfer information setting. For details, see section 8.2, Register Descriptions, and figure 8.4. Set the transfer information of MRA, MRB, SAR, DAR, CRA, and CRB [2] Set the start address of transfer information in the DTC vector table [3] Set the RRS bit in DTCCR to 1 [4] Set the corresponding bit in DTCER to 1 [5] Set the enable bit of interrupt, which is to be an activation factor to 1 [6] Interrupt is generated DTC is activated Activation source flag is cleared [7] Activation source clear decision Corresponding bit in DTCER is cleared Clear the corresponding bit in DTCER/request the CPU an interrupt Transfer end Figure 8.15 Using DTC with Interrupt Activation Rev. 2.00 Mar. 15, 2006 Page 237 of 754 REJ09B0199-0200 Section 8 Data Transfer Controller (DTC) 8.7 8.7.1 Examples of Use of the DTC Normal Transfer Mode An example is shown in which the DTC is used to receive 128 bytes of data via the SCI. 1. Set MRA to fixed source address (SM1 = SM0 = 0), incrementing destination address (DM1 = 1, DM0 = 0), normal transfer mode (MD1 = MD0 = 0), and byte size (Sz1 = Sz0 = 0). The DTS bit can have any value. Set MRB for one data transfer by one interrupt (CHNE = 0, DISEL = 0). Set the RDR address of the SCI in SAR, the start address of the RAM area where the data will be received in DAR, and 128 (H'0080) in CRA. CRB can be set to any value. 2. Set the start address of the transfer information for an RXI interrupt at the DTC vector address. 3. Set the corresponding bit in DTCER to 1. 4. Set the SCI to the appropriate receive mode. Set the RIE bit in SCR to 1 to enable the receive end (RXI) interrupt. Since the generation of a receive error during the SCI reception operation will disable subsequent reception, the CPU should be enabled to accept receive error interrupts. 5. Each time reception of one byte of data ends on the SCI, the RDRF flag in SSR is set to 1, an RXI interrupt is generated, and the DTC is activated. The receive data is transferred from RDR to RAM by the DTC. DAR is incremented and CRA is decremented. The RDRF flag is automatically cleared to 0. 6. When CRA becomes 0 after the 128 data transfers have ended, the RDRF flag is held at 1, the DTCE bit is cleared to 0, and an RXI interrupt request is sent to the CPU. Termination processing should be performed in the interrupt handling routine. Rev. 2.00 Mar. 15, 2006 Page 238 of 754 REJ09B0199-0200 Section 8 Data Transfer Controller (DTC) 8.7.2 Chain Transfer An example of DTC chain transfer is shown in which pulse output is performed using the PPG. Chain transfer can be used to perform pulse output data transfer and PPG output trigger cycle updating. Repeat mode transfer to the PPG's NDR is performed in the first half of the chain transfer, and normal mode transfer to the TPU's TGR in the second half. This is because clearing of the activation source and interrupt generation at the end of the specified number of transfers are restricted to the second half of the chain transfer (transfer when CHNE = 0). 1. Perform settings for transfer to the PPG's NDR. Set MRA to source address incrementing (SM1 = 1, SM0 = 0), fixed destination address (DM1 = DM0 = 0), repeat mode (MD1 = 0, MD0 = 1), and word size (Sz1 = 0, Sz0 = 1). Set the source side as a repeat area (DTS = 1). Set MRB to chain transfer mode (CHNE = 1, CHNS = 0, DISEL = 0). Set the data table start address in SAR, the NDRH address in DAR, and the data table size in CRAH and CRAL. CRB can be set to any value. 2. Perform settings for transfer to the TPU's TGR. Set MRA to source address incrementing (SM1 = 1, SM0 = 0), fixed destination address (DM1 = DM0 = 0), normal mode (MD1 = MD0 = 0), and word size (Sz1 = 0, Sz0 = 1). Set the data table start address in SAR, the TGRA address in DAR, and the data table size in CRA. CRB can be set to any value. 3. Locate the TPU transfer information consecutively after the NDR transfer information. 4. Set the start address of the NDR transfer information to the DTC vector address. 5. Set the bit corresponding to the TGIA interrupt in DTCER to 1. 6. Set TGRA as an output compare register (output disabled) with TIOR, and enable the TGIA interrupt with TIER. 7. Set the initial output value in PODR, and the next output value in NDR. Set bits in DDR and NDER for which output is to be performed to 1. Using PCR, select the TPU compare match to be used as the output trigger. 8. Set the CST bit in TSTR to 1, and start the TCNT count operation. 9. Each time a TGRA compare match occurs, the next output value is transferred to NDR and the set value of the next output trigger period is transferred to TGRA. The activation source TGFA flag is cleared. 10. When the specified number of transfers are completed (the TPU transfer CRA value is 0), the TGFA flag is held at 1, the DTCE bit is cleared to 0, and a TGIA interrupt request is sent to the CPU. Termination processing should be performed in the interrupt handling routine. Rev. 2.00 Mar. 15, 2006 Page 239 of 754 REJ09B0199-0200 Section 8 Data Transfer Controller (DTC) 8.7.3 Chain Transfer when Counter = 0 By executing a second data transfer and performing re-setting of the first data transfer only when the counter value is 0, it is possible to perform 256 or more repeat transfers. An example is shown in which a 128-kbyte input buffer is configured. The input buffer is assumed to have been set to start at lower address H'0000. Figure 8.16 shows the chain transfer when the counter value is 0. 1. For the first transfer, set the normal transfer mode for input data. Set the fixed transfer source address (G/A etc.), CRA = H'0000 (64k times), CHNE = 1, CHNS = 1, and DISEL = 0. 2. Prepare the upper 8-bit addresses of the start addresses for 64k-transfer units for the first data transfer in a separate area (in ROM, etc.). For example, if the input buffer is configured at addresses H'200000 to H'21FFFF, prepare H'21 and H'20. 3. For the second transfer, set repeat transfer mode (with the source side as the repeat area) for resetting the transfer destination address for the first data transfer. Use the upper eight bits of DAR in the first transfer information area as the transfer destination. Set CHNE = DISEL = 0. If the above input buffer is specified as H'200000 to H'21FFFF, set the transfer counter to 2. 4. Execute the first data transfer 64k times by means of interrupts. When the transfer counter for the first data transfer reaches 0, the second data transfer is started. Set the upper eight bits of the transfer source address for the first data transfer to H'21. The lower 16 bits of the transfer destination address of the first data transfer and the transfer counter are H'0000. 5. Next, execute the first data transfer the 64k times specified for the first data transfer by means of interrupts. When the transfer counter for the first data transfer reaches 0, the second data transfer is started. Set the upper eight bits of the transfer source address for the first data transfer to H'20. The lower 16 bits of the transfer destination address of the first data transfer and the transfer counter are H'0000. 6. Steps 4 and 5 are repeated endlessly. As repeat mode is specified for the second data transfer, no interrupt request is sent to the CPU. Rev. 2.00 Mar. 15, 2006 Page 240 of 754 REJ09B0199-0200 Section 8 Data Transfer Controller (DTC) Input circuit Transfer information located on the on-chip memory Input buffer 1st data transfer information 2nd data transfer information Chain transfer (counter = 0) Upper 8 bits of DAR Figure 8.16 Chain Transfer when Counter = 0 8.8 Interrupt Sources An interrupt request is issued to the CPU when the DTC finishes the specified number of data transfers or a data transfer for which the DISEL bit was set to 1. In the case of interrupt activation, the interrupt set as the activation source is generated. These interrupts to the CPU are subject to CPU mask level and priority level control in the interrupt controller. 8.9 8.9.1 Usage Notes Module Stop Mode Setting Operation of the DTC can be disabled or enabled using the module stop control register. The initial setting is for operation of the DTC to be enabled. Register access is disabled by setting module stop mode. Module stop mode cannot be set while the DTC is activated. For details, see section 19, Power-Down Modes. 8.9.2 On-Chip RAM Transfer information can be located in on-chip RAM. In this case, the RAME bit in SYSCR must not be cleared to 0. Rev. 2.00 Mar. 15, 2006 Page 241 of 754 REJ09B0199-0200 Section 8 Data Transfer Controller (DTC) 8.9.3 DMAC Transfer End Interrupt When DTC is activated by the DMAC transfer end interrupt, the data in the DTE bit in DMDR has priority over the DTC control regardless of the transfer counter or the DISEL bit. Therefore, an interrupt to CPU may not be generated even if the DTC transfer counter becomes 0. 8.9.4 DTCE Bit Setting For DTCE bit setting, use bit manipulation instructions such as BSET and BCLR. If all interrupts are disabled, multiple activation sources can be set at one time (only at the initial setting) by writing data after executing a dummy read on the relevant register. 8.9.5 Chain Transfer When chain transfer is used, clearing of the activation source or DTCER is performed when the last of the chain of data transfers is executed. SCI and high-speed A/D converter interrupt/activation sources, on the other hand, are cleared when the DTC reads or writes to the relevant register. Therefore, when the DTC is activated by an interrupt or activation source, if a read/write of the relevant register is not included in the last chained data transfer, the interrupt or activation source will be retained. 8.9.6 Transfer Information Start Address, Source Address, and Destination Address The transfer information start address to be specified in the vector table should be address 4n. If an address other than address 4n is specified, the lower 2 bits of the address are regarded as 0s. The source and destination addresses specified in SAR and DAR, respectively, will be transferred in the divided bus cycles depending on the address and data size. 8.9.7 Endian The DTC supports both big-endian and little-endian formats. The endian format should be the same when the transfer information is written to and when the transfer information is read by the DTC. Rev. 2.00 Mar. 15, 2006 Page 242 of 754 REJ09B0199-0200 Section 9 I/O Ports Section 9 I/O Ports Table 9.1 summarizes the port functions. The pins of each port also have other functions such as input/output pins of on-chip peripheral modules or external interrupt input pins. Each I/O port includes a data direction register (DDR) that controls input/output, a data register (DR) that stores output data, a port register (PORT) used to read the pin states, and an input buffer control register (ICR) that controls input buffer on/off. Ports 4 and 5 do not have a DR or a DDR register. Ports D, H, I, J and K have internal input pull-up MOSs and a pull-up MOS control register (PCR) that controls the on/off state of the input pull-up MOSs. Port 2 includes an open-drain control register (ODR) that controls on/off of the output buffer PMOSs. Ports 1, 2, 3, 6, A, B, D, H, I, J, and K can drive a single TTL load and capacitive loads up to 30 pF. All of the I/O ports can drive Darlington transistors when functioning as output ports. Schmitt-trigger inputs are enabled when a port is used as the IRQ and TPU inputs. Table 9.1 Port Functions Function SchmittTrigger 1 Input* IRQ7 IRQ6 IRQ5 IRQ4 IRQ3 IRQ2 IRQ1 IRQ0 Input Pull-up MOS Function OpenDrain Output Function Port Description Bit I/O P17 P16/SCK3 P15 P14 P13 P12 P11 P10 Input ADTRG1/ IRQ7 IRQ6 RxD3/ IRQ5 IRQ4 ADTRG0/ IRQ3 IRQ2 IRQ1 IRQ0 Output TxD3 Port 1 General I/O port 7 also functioning as interrupt inputs, 6 SCI I/Os, and A/D converter inputs 5 4 3 2 1 0 Rev. 2.00 Mar. 15, 2006 Page 243 of 754 REJ09B0199-0200 Section 9 I/O Ports Function SchmittTrigger 1 Input * P27, TIOCA5, TIOCB5, IRQ15-A P26, TIOCA5, IRQ14-A P25, IRQ13-A, TIOCA4 P24, TIOCA4, TIOCB4, IRQ12-A P23, TIOCC3, TIOCD3, IRQ11-A P22, TIOCC3, IRQ10-A P21, TIOCA3, IRQ9-A P20, TIOCA3, TIOCB3, IRQ8-A Port Description Bit I/O P27/ TIOCB5 Input IRQ15-A/ TIOCA5 Output Input Pull-up MOS Function OpenDrain Output Function O Port 2 General I/O port 7 also functioning as interrupt inputs, TPU I/Os, and SSU I/Os 6 P26/ TIOCA5 P25/ TIOCA4 P24/ TIOCB4 IRQ14-A 5 IRQ13-A 4 TIOCA4/ IRQ12-A 3 P23/ TIOCD3 TIOCC3/ IRQ11-A 2 P22/ TIOCC3 P21/ TIOCA3/ SCS2 P20/ TIOCB3 IRQ10-A 1 IRQ9-A 0 TIOCA3/ IRQ8-A Rev. 2.00 Mar. 15, 2006 Page 244 of 754 REJ09B0199-0200 Section 9 I/O Ports Function SchmittTrigger 1 Input * P37, TIOCA2, TIOCB2, TCLKD P36, TIOCA2 P35, TIOCA1, TIOCB1, TCLKC P34, TIOCA1 P33, TIOCC0, TIOCD0, TCLKB P32, TIOCC0, TCLKA P31, TIOCA0, TIOCB0 P30, TIOCA0 Port Description Bit 7 I/O P37/ TIOCB2 Input TIOCA2/ TCLKD Output PO15 Input Pull-up MOS Function OpenDrain Output Function Port 3 General I/O port also functioning as PPG outputs and TPU I/Os 6 5 P36/ TIOCA2 P35/ TIOCB1 TIOCA1/ TCLKC PO14 PO13 4 3 P34/ TIOCA1 P33/ TIOCD0 TIOCC0/ TCLKB PO12 PO11 2 P32/ TIOCC0 P31/ TIOCB0 P30/ TIOCA0 TCLKA PO10 1 TIOCA0 PO9 0 Port 4 General I/O port also functioning as A/D converter inputs 7 6 5 4 3 2 1 0 P47/AN11 P46/AN10 P45/AN9 P44/AN8 P43/AN15 P42/AN14 P41/AN13 P40/AN12 PO8 Rev. 2.00 Mar. 15, 2006 Page 245 of 754 REJ09B0199-0200 Section 9 I/O Ports Function SchmittTrigger 1 Input * Port Description Bit 7 6 5 4 3 2 1 0 I/O P67 P66 P65 P64 P63 P62/SCK4 P61 P60 PA6 PA5 PA4 PA3/SSO2 PA2/SSI2 Input P57/AN7 P56/AN6 P55/AN5 P54/AN4 P53/AN3 P52/AN2 P51/AN1 P50/AN0 IRQ15-B IRQ14-B IRQ13-B IRQ12-B IRQ11-B IRQ10-B RxD4/ IRQ9-B IRQ8-B PA7 Output Input Pull-up MOS Function OpenDrain Output Function Port 5 General I/O port also functioning as A/D converter inputs Port 6 General I/O port also functioning as SCI I/Os, and interrupt inputs 7 6 5 4 3 2 1 0 IRQ15-B IRQ14-B IRQ13-B IRQ12-B IRQ11-B IRQ10-B IRQ9-B IRQ8-B O Only for SSU TxD4 B Port A General I/O port also functioning as SSU I/Os and B output 7 6 5 4 3 2 1 0 PA1/SSCK2 PA0 PB2 PB1 PB0 Port B General I/O port 2 1 0 Rev. 2.00 Mar. 15, 2006 Page 246 of 754 REJ09B0199-0200 Section 9 I/O Ports Function SchmittTrigger 1 Input * Port Description Bit 7 6 5 4 3 2 1 0 I/O PD7/SCS1 Input Output Input Pull-up MOS Function O OpenDrain Output Function O Only for SSU Port D General I/O port also functioning as SSU I/Os PD6/SSCK1 PD5/SSI1 PD4/SSO1 PD3/SCS0 PD2/SSCK0 PD1/SSI0 PD0/SSO0 PH7 PH6 PH5 PH4 PH3 PH2 PH1 PH0 PI7 PI6 PI5 PI4 PI3 PI2 PI1 PI0 Port H General I/O port 7 6 5 4 3 2 1 0 O Port I General I/O port 7 6 5 4 3 2 1 0 O Rev. 2.00 Mar. 15, 2006 Page 247 of 754 REJ09B0199-0200 Section 9 I/O Ports Function Port Description Bit 7 I/O PJ7/ TIOCB8 Input TIOCA8/ TCLKH Output SchmittTrigger 1 Input * PJ7, TIOCA8, TIOCB8, TCLKH PJ6, TIOCA8 PJ5, TIOCA7, TIOCB7, TCLKG PJ4, TIOCA7 PJ3, TIOCC6, TIOCD6, TCLKF PJ2, TIOCC6, TCLKE PJ1, TIOCA6, TIOCB6 PJ0, TIOCA6 PK7, O TIOCA11, TIOCB11 PK6, TIOCA11 PK5, TIOCA10, TIOCB10 PK4, TIOCA10 PK3, TIOCC9, TIOCD9 PK2, TIOCC9 PK1, TIOCA9, TIOCB9 PK0, TIOCA9 Input Pull-up MOS Function O OpenDrain Output Function Port J General I/O port also functioning as TPU I/Os 6 5 PJ6/ TIOCA8 PJ5/ TIOCB7 TIOCA7/ TCLKG 4 3 PJ4/ TIOCA7 PJ3/ TIOCD6 TIOCC6/ TCLKF 2 PJ2/ TIOCC6 PJ1/ TIOCB6 PJ0/ TIOCA6 PK7/ TIOCB11 PK6/ TIOCA11 PK5/ TIOCB10 PK4/ TIOCA10 PK3/ TIOCD9 PK2/ TIOCC9 PK1/ TIOCB9 PK0/ TIOCA9 TCLKE 1 TIOCA6 0 Port K General I/O port also functioning as TPU I/Os 7 TIOCA11 6 5 TIOCA10 4 3 TIOCC9 2 1 TIOCA9 0 Note: * Pins without Schmitt-trigger input buffer have CMOS input buffer. Rev. 2.00 Mar. 15, 2006 Page 248 of 754 REJ09B0199-0200 Section 9 I/O Ports 9.1 Register Descriptions Table 9.2 lists each port registers. Table 9.2 Register Configuration in Each Port Number of Port Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port A Port B* Port D Port H Port I Port J Port K Pins 8 4 8 8 8 8 8 3 8 8 8 8 8 DDR O O O O O O O O O O O DR O O O O O O O O O O O PORT O O O O O O O O O O O O O Registers ICR O O O O O O O O O O O O O PCR O O O O O ODR O PHRTIDR O [Legend] O: Register exists : No register exists Note: * The lower three bits are valid and the upper five bits are reserved. The write value should always be the initial value. Rev. 2.00 Mar. 15, 2006 Page 249 of 754 REJ09B0199-0200 Section 9 I/O Ports Figure 9.1 is a port block diagram. Address output Data output R Q PCR S CK On-chip peripheral module output WPCR RPCR R Q DDR S CK WDDR On-chip peripheral module output enable On-chip peripheral module output signal 1 0 R Q DR S CK WDR Internal bus R Q ODR S CK WODR RODR RDR 1 0 Input buffer RPOR RPOR To on-chip Peripheral module R Q ICR S CK [Legend] WDDR: DDR write WDR: DR write WICR: ICR write WPCR: PCR write WODR: ODR write RDR: RPOR: RICR: RPCR: RODR: DR read PORT read ICR read PCR read ODR read WICR RICR Figure 9.1 Port Block Diagram Rev. 2.00 Mar. 15, 2006 Page 250 of 754 REJ09B0199-0200 Section 9 I/O Ports 9.1.1 Data Direction Register (PnDDR) (n = 1 to 3, 6, A, B, D, H, I, J, and K) DDR is an 8-bit write-only register that specifies the port input or output for each bit. A read from the DDR is invalid and DDR is always read as an undefined value. When the general I/O port function is selected, the corresponding pin functions as an output port by setting the corresponding DDR bit to 1; the corresponding pin functions as an input port by clearing the corresponding DDR bit to 0. Bit Bit Name Initial Value R/W Note: 7 Pn7DDR 0 W 6 Pn6DDR 0 W 5 Pn5DDR 0 W 4 Pn4DDR 0 W 3 Pn3DDR 0 W 2 Pn2DDR 0 W 1 Pn1DDR 0 W 0 Pn0DDR 0 W The lower three bits are valid and the upper five bits are reserved for port B data direction register (PBDDR). 9.1.2 Data Register (PnDR) (n = 1 to 3, 6, A, B, D, H, I, J, and K) DR is an 8-bit readable/writable register that stores the output data of the pins to be used as the general output port. The initial value of DR is H'00. Bit Bit Name Initial Value R/W Note: 7 Pn7DR 0 R/W 6 Pn6DR 0 R/W 5 Pn5DR 0 R/W 4 Pn4DR 0 R/W 3 Pn3DR 0 R/W 2 Pn2DR 0 R/W 1 Pn1DR 0 R/W 0 Pn0DR 0 R/W The lower three bits are valid and the upper five bits are reserved for port B data register (PBDR). Rev. 2.00 Mar. 15, 2006 Page 251 of 754 REJ09B0199-0200 Section 9 I/O Ports 9.1.3 Port Register (PORTn) (n = 1 to 6, A, B, D, H, I, J, and K) PORT is an 8-bit read-only register that reflects the port pin status. A write to PORT is invalid. When PORT is read, the DR bits that correspond to the respective DDR bits set to 1 are read and the status of each pin whose corresponding DDR bit is cleared to 0 is also read regardless of the ICR value. The initial value of PORT is undefined and is determined based on the port pin status. Bit Bit Name Initial Value R/W Note: 7 Pn7 Undefined R 6 Pn6 Undefined R 5 Pn5 Undefined R 4 Pn4 Undefined R 3 Pn3 Undefined R 2 Pn2 Undefined R 1 Pn1 Undefined R 0 Pn0 Undefined R The lower three bits are valid and the upper five bits are reserved for port B register (PORTB). 9.1.4 Input Buffer Control Register (PnICR) (n = 1 to 6, A, B, D, H, I, J, and K) ICR is an 8-bit readable/writable register that controls the port input buffers. For bits in ICR set to 1, the input buffers of the corresponding pins are valid. For bits in ICR cleared to 0, the input buffers of the corresponding pins are invalid and the input signals are fixed high. When the pin functions as an input for the peripheral modules, the corresponding bits should be set to 1. The initial value should be written to a bit whose corresponding pin is not used as an input or is used as an analog input/output pin. When PORT is read, the pin status is always read regardless of the ICR value. On-chip modules are not affected by the pin status when the ICR value is cleared to 0. If ICR is modified, an internal edge may occur depending on the pin status. Accordingly, ICR should be modified when the corresponding input pins are not used. For example, in IRQ input, modify ICR while the corresponding interrupt is disabled, clear the IRQF flag in ISR of the interrupt controller to 0, and then enable the corresponding interrupt. If an edge occurs after the ICR setting, the edge should be cancelled. The initial value of ICR is H'00. Rev. 2.00 Mar. 15, 2006 Page 252 of 754 REJ09B0199-0200 Section 9 I/O Ports Bit Bit Name Initial Value R/W Note: 7 Pn7ICR 0 R/W 6 Pn6ICR 0 R/W 5 Pn5ICR 0 R/W 4 Pn4ICR 0 R/W 3 Pn3ICR 0 R/W 2 Pn2ICR 0 R/W 1 Pn1ICR 0 R/W 0 Pn0ICR 0 R/W The lower three bits are valid and the upper five bits are reserved for port B input buffer control register (PBICR). 9.1.5 Pull-Up MOS Control Register (PnPCR) (n = D, H, I, J, and K) PCR is an 8-bit readable/writable register that controls on/off of the port input pull-up MOS. If a bit in PCR is set to 1 while the pin is in input state, the input pull-up MOS corresponding to the bit in PCR is turned on. Table 9.3 shows the input pull-up MOS status. The initial value of PCR is H'00. Bit Bit Name Initial Value R/W 7 Pn7PCR 0 R/W 6 Pn6PCR 0 R/W 5 Pn5PCR 0 R/W 4 Pn4PCR 0 R/W 3 Pn3PCR 0 R/W 2 Pn2PCR 0 R/W 1 Pn1PCR 0 R/W 0 Pn0PCR 0 R/W Table 9.3 Port Port D Input Pull-Up MOS State Pin State On-chip peripheral module output Port input Reset OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF Software Standby Mode OFF ON/OFF OFF ON/OFF OFF ON/OFF OFF ON/OFF OFF ON/OFF Other Operation OFF ON/OFF OFF ON/OFF OFF ON/OFF OFF ON/OFF OFF ON/OFF Port H Port output Port input Port I Port output Port input Port J On-chip peripheral module output Port input Port K On-chip peripheral module output Port input [Legend] OFF: ON/OFF: The input pull-up MOS is always off. If PCR is set to 1, the input pull-up MOS is on; if PCR is cleared to 0, the input pull-up MOS is off. Rev. 2.00 Mar. 15, 2006 Page 253 of 754 REJ09B0199-0200 Section 9 I/O Ports 9.1.6 Open-Drain Control Register (PnODR) (n = 2) ODR is an 8-bit readable/writable register that selects the open-drain output function. If a bit in ODR is set to 1, the pin corresponding to that bit in ODR functions as an NMOS opendrain output. If a bit in ODR is cleared to 0, the pin corresponding to that bit in ODR functions as a CMOS output. The initial value of ODR is H'00. Bit Bit Name Initial Value R/W 7 Pn7ODR 0 R/W 6 Pn6ODR 0 R/W 5 Pn5ODR 0 R/W 4 Pn4ODR 0 R/W 3 Pn3ODR 0 R/W 2 Pn2ODR 0 R/W 1 Pn1ODR 0 R/W 0 Pn0ODR 0 R/W 9.1.7 Port H Realtime Input Data Register (PHRTIDR) PHRTIDR stores the status of port H using pin IRQ14 as a trigger. The detection method is specified by the IRQ14SR and IRQ14SF bits in the IRQ sense control register H (ISCRH) and is selected from a low level, a falling edge, a rising edge of pin, and both edges of pin IRQ14. For details, see section 5.3.5, IRQ Sense Control Registers H and L (ISCRH and ISCRL). Bit Bit Name Initial Value R/W 7 6 5 4 3 2 1 0 PHRTIDR7 PHRTIDR6 PHRTIDR5 PHRTIDR4 PHRTIDR3 PHRTIDR2 PHRTIDR1 PHRTIDR0 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R Rev. 2.00 Mar. 15, 2006 Page 254 of 754 REJ09B0199-0200 Section 9 I/O Ports 9.2 Output Buffer Control This section describes the output priority of each pin. The name of each peripheral module pin is followed by "_OE". This (for example: MIOCA4_OE) indicates whether the output of the corresponding function is valid (1) or if another setting is specified (0). Table 9.4 lists each port output signal's valid setting. For details on the corresponding output signals, see the register description of each peripheral module. If the name of each peripheral module pin is followed by A or B, the pin function can be modified by the port function control register (PFCR). For details, see section 9.3.3, Port Function Control Register B (PFCRB). 9.2.1 (1) Port 1 P17/ADTRG1/IRQ7 The pin function is switched as shown below according to the P17DDR bit setting. Setting I/O Port Module Name I/O port Pin Function P17 output P17 input (initial setting) P17DDR 1 0 (2) P16/SCK3/IRQ6 The pin function is switched as shown below according to the combination of the SCI_3 and P16DDR bit settings. Setting SCI_3 Module Name SCI_3 I/O port Pin Function SCK3 output P16 output P16 input initial setting) SCK3_OE 1 0 0 I/O Port P16DDR 1 0 Rev. 2.00 Mar. 15, 2006 Page 255 of 754 REJ09B0199-0200 Section 9 I/O Ports (3) P15/RxD3/IRQ5 The pin function is switched as shown below according to the P15DDR bit setting. Setting I/O Port Module Name I/O port Pin Function P15 output P15 input (initial setting) P15DDR 1 0 (4) P14/TxD3/IRQ4 The pin function is switched as shown below according to the combination of the SCI_3 and P14DDR bit settings. Setting SCI_4 Module Name SCI_3 I/O port Pin Function TxD3 output P14 output P14 input (initial setting) TxD3_OE 1 0 0 I/O Port P14DDR 1 0 (5) P13/ADTRG0/IRQ3 The pin function is switched as shown below according to the P13DDR bit setting. Setting I/O Port Module Name I/O port Pin Function P13 output P13 input (initial setting) P13DDR 1 0 Rev. 2.00 Mar. 15, 2006 Page 256 of 754 REJ09B0199-0200 Section 9 I/O Ports (6) P12/IRQ2 The pin function is switched as shown below according to the P12DDR bit setting. Setting I/O Port Module Name I/O port Pin Function P12 output P12DDR 1 P12 input (initial setting) 0 (7) P11/IRQ1 The pin function is switched as shown below according to the P11DDR bit setting. Setting I/O Port Module Name I/O port Pin Function P11 output P11 input (initial setting) P11DDR 1 0 (8) P10/IRQ0 The pin function is switched as shown below according to the P10DDR bit setting. Setting I/O Port Module Name I/O port Pin Function P10 output P10 input (initial setting) P10DDR 1 0 Rev. 2.00 Mar. 15, 2006 Page 257 of 754 REJ09B0199-0200 Section 9 I/O Ports 9.2.2 (1) Port 2 P27/TIOCA5/TIOCB5/IRQ15-A The pin function is switched as shown below according to the combination of the port function control register 9 (PFCR9), TPU_5, and P27DDR bit settings. Setting TPU_5 Module Name TPU_5 I/O port Pin Function TIOCB5 output P27 output P27 input (initial setting) TIOCB5_OE 1 0 0 I/O Port P27DDR 1 0 (2) P26/TIOCA5/IRQ14-A The pin function is switched as shown below according to the combination of the port function control register 9 (PFCR9), TPU_5, and P26DDR bit settings. Setting TPU_5 Module Name TPU_5 I/O port Pin Function TIOCA5 output P26 output TIOCA5_OE 1 0 I/O Port P26DDR 1 0 P26 input (initial setting) 0 Rev. 2.00 Mar. 15, 2006 Page 258 of 754 REJ09B0199-0200 Section 9 I/O Ports (3) P25/TIOCA4/IRQ13-A The pin function is switched as shown below according to the combination of the port function control register 9 (PFCR9), TPU_4, and P25DDR bit settings. Setting TPU_4 Module Name TPU_4 I/O port Pin Function TIOCA4 output P25 output P25 input (initial setting) TIOCA4_OE 1 0 0 I/O Port P25DDR 1 0 (4) P24/TIOCA4/TIOCB4/IRQ12-A The pin function is switched as shown below according to the combination of the port function control register 9 (PFCR9), TPU_4, and P24DDR bit settings. Setting TPU_4 Module Name TPU_4 I/O port Pin Function TIOCB4 output P24 output P24 input (initial setting) TIOCB4_OE 1 0 0 I/O Port P24DDR 1 0 (5) P23/TIOCC3/TIOCD3/IRQ11-A The pin function is switched as shown below according to the combination of the port function control register 9 (PFCR9), TPU_3, and P23DDR bit settings. Setting TPU_3 Module Name TPU_3 I/O port Pin Function TIOCD3 output P23 output P23 input (initial setting) TIOCD3_OE 1 0 0 I/O Port P23DDR 1 0 Rev. 2.00 Mar. 15, 2006 Page 259 of 754 REJ09B0199-0200 Section 9 I/O Ports (6) P22/TIOCC3/IRQ10-A The pin function is switched as shown below according to the combination of the port function control register 9 (PFCR9), TPU_3, and P22DDR bit settings. Setting TPU_3 Module Name TPU_3 I/O port Pin Function TIOCC3 output P22 output P22 input (initial setting) TIOCC3_OE 1 0 0 I/O Port P22DDR 1 0 (7) P21/TIOCA3/IRQ9-A/SCS2 The pin function is switched as shown below according to the combination of the port function control register 9 (PFCR9), SSU_2, TPU_3, and P21DDR bit settings. SSU_2 Module Name SSU_2 TPU_3 I/O port Pin Function SCS2 output TIOCA3 output P21 output P21 input (initial setting) SCS2_OE 1 0 0 0 TPU_3 TIOCA3_OE 1 0 0 I/O Port P21DDR 1 0 (8) P20/TIOCA3/TIOCB3/IRQ8-A The pin function is switched as shown below according to the combination of the port function control register 9 (PFCR9), TPU_3, and P20DDR bit settings. Setting TPU_3 Module Name TPU_3 I/O port Pin Function TIOCB3 output P20 output P20 input (initial setting) TIOCB3_OE 1 0 0 I/O Port P20DDR 1 0 Rev. 2.00 Mar. 15, 2006 Page 260 of 754 REJ09B0199-0200 Section 9 I/O Ports 9.2.3 (1) Port 3 P37/PO15/TIOCA2/TIOCB2/TCLKD The pin function is switched as shown below according to the combination of the port function control register 9 (PFCR9), TPU_2, PPG, and P37DDR bit settings. Setting TPU_2 Module Name TPU_2 PPG I/O port Pin Function TIOCB2 output PO15 output P37 output P37 input (initial setting) TIOCB2_OE 1 0 0 0 PPG PO15_OE 1 0 0 I/O Port P37DDR 1 0 (2) P36/PO14/TIOCA2 The pin function is switched as shown below according to the combination of the port function control register 9 (PFCR9), TPU_2, PPG, and P36DDR bit settings. Setting TPU_2 Module Name TPU_2 PPG I/O port Pin Function TIOCA2 output PO14 output P36 output TIOCA2_OE 1 0 0 PPG PO14_OE 1 0 0 I/O Port P36DDR 1 0 P36 input (initial setting) 0 Rev. 2.00 Mar. 15, 2006 Page 261 of 754 REJ09B0199-0200 Section 9 I/O Ports (3) P35/PO13/TIOCA1/TIOCB1/TCLKC The pin function is switched as shown below according to the combination of the port function control register 9 (PFCR9), TPU_1, PPG, and P35DDR bit settings. Setting TPU_1 Module Name TPU_1 PPG I/O port Pin Function TIOCB1 output PO13 output P35 output P35 input (initial setting) TIOCB1_OE 1 0 0 0 PPG PO13_OE 1 0 0 I/O Port P35DDR 1 0 (4) P34/PO12/TIOCA1 The pin function is switched as shown below according to the combination of the port function control register 9 (PFCR9), TPU_1, PPG, and P34DDR bit settings. Setting TPU_1 Module Name TPU_1 PPG I/O port Pin Function TIOCA1 output PO12 output P34 output P34 input (initial setting) TIOCA1_OE 1 0 0 0 PPG PO12_OE 1 0 0 I/O Port P34DDR 1 0 (5) P33/PO11/TIOCC0/TIOCD0/TCLKB The pin function is switched as shown below according to the combination of the port function control register 9 (PFCR9), TPU_0, PPG, and P33DDR bit settings. Setting TPU_0 Module Name TPU_0 PPG I/O port Pin Function TIOCD0 output PO11 output P33 output P33 input (initial setting) TIOCD0_OE 1 0 0 0 PPG PO11_OE 1 0 0 I/O Port P33DDR 1 0 Rev. 2.00 Mar. 15, 2006 Page 262 of 754 REJ09B0199-0200 Section 9 I/O Ports (6) P32/PO10/TIOCC0/TCLKA The pin function is switched as shown below according to the combination of the port function control register 9 (PFCR9), TPU_0, PPG, and P32DDR bit settings. Setting TPU_0 Module Name TPU_0 PPG I/O port Pin Function TIOCC0 output PO10 output P32 output P32 input (initial setting) TIOCC0_OE 1 0 0 0 PPG PO10_OE 1 0 0 I/O Port P32DDR 1 0 (7) P31/PO9/TIOCA0/TIOCB0 The pin function is switched as shown below according to the combination of the port function control register 9 (PFCR9), TPU_0, PPG, and P31DDR bit settings. Setting TPU_0 Module Name TPU_0 PPG I/O port Pin Function TIOCB0 output PO9 output P31 output P31 input (initial setting) TIOCB0_OE 1 0 0 0 PPG PO9_OE 1 0 0 I/O Port P31DDR 1 0 (8) P30/PO8/TIOCA0 The pin function is switched as shown below according to the combination of the port function control register 9 (PFCR9), TPU_0, PPG, and P30DDR bit settings. Setting TPU_0 Module Name TPU_0 PPG I/O port Pin Function TIOCA0 output PO8 output P30 output P30 input (initial setting) TIOCA0_OE 1 0 0 0 PPG PO8_OE 1 0 0 I/O Port P30DDR 1 0 Rev. 2.00 Mar. 15, 2006 Page 263 of 754 REJ09B0199-0200 Section 9 I/O Ports 9.2.4 (1) Port 6 P67/IRQ15-B The pin function is switched as shown below according to the P67DDR bit setting. Setting I/O Port Module Name I/O port Pin Function P67 output P67DDR 1 P67 input (initial setting) 0 (2) P66/IRQ14-B The pin function is switched as shown below according to the P66DDR bit setting. Setting I/O Port Module Name I/O port Pin Function P66 output P66DDR 1 P66 input (initial setting) 0 (3) P65/IRQ13-B/HRxD The pin function is switched as shown below according to the P65DDR bit setting. Setting I/O Port Module Name I/O port Pin Function P65 output P65DDR 1 P65 input (initial setting) 0 Rev. 2.00 Mar. 15, 2006 Page 264 of 754 REJ09B0199-0200 Section 9 I/O Ports (4) P64/IRQ12-B The pin function is switched as shown below according to the P64DDR bit setting. Setting I/O Port Module Name I/O port Pin Function P64 output P64 input (initial setting) P64DDR 1 0 (5) P63/IRQ11-B The pin function is switched as shown below according to the P63DDR bit setting. Setting I/O Port Module Name I/O port Pin Function P63 output P63 input (initial setting) P63DDR 1 0 (6) P62/SCK4/IRQ10-B The pin function is switched as shown below according to the combination of the SCI_4 and P62DDR bit settings. Setting SCI_4 Module Name SCI_4 I/O port Pin Function SCK4 output P62 output SCK4_OE 1 0 I/O Port P62DDR 1 0 P62 input (initial setting) 0 Rev. 2.00 Mar. 15, 2006 Page 265 of 754 REJ09B0199-0200 Section 9 I/O Ports (7) P61/RxD4/IRQ9-B The pin function is switched as shown below according to the P61DDR bit setting. Setting I/O Port Module Name I/O port Pin Function P61 output P61 input (initial setting) P61DDR 1 0 (8) P60/TxD4/IRQ8-B The pin function is switched as shown below according to the combination of the SCI_4 and P60DDR bit settings. Setting SCI_4 Module Name SCI_4 I/O port Pin Function TxD4 output P60 output P60 input(initial setting) TxD4_OE 1 0 0 I/O Port P60DDR 1 0 Rev. 2.00 Mar. 15, 2006 Page 266 of 754 REJ09B0199-0200 Section 9 I/O Ports 9.2.5 (1) Port A PA7 The pin function is switched as shown below according to the PA7DDR bit setting. Setting I/O Port Module Name I/O port Pin Function B output PA7DDR 1 PA7 input (initial setting) 0 (2) PA6 The pin function is switched as shown below according to the PA6DDR bit setting. Setting I/O Port Module Name I/O port Pin Function PA6 output PA6DDR 1 PA6 input (initial setting) 0 (3) PA5 The pin function is switched as shown below according to the PA5DDR bit setting. Setting I/O Port Module Name I/O port Pin Function PA5 output PA5DDR 1 PA5 input (initial setting) 0 Rev. 2.00 Mar. 15, 2006 Page 267 of 754 REJ09B0199-0200 Section 9 I/O Ports (4) PA4 The pin function is switched as shown below according to the PA4DDR bit setting. Setting I/O Port Module Name I/O port Pin Function PA4 output PA4DDR 1 PA4 input (initial setting) 0 (5) PA3/SSO2 The pin function is switched as shown below according to the combination of the SSU_2 and the PA3DDR bit settings. Setting SSU_2 Module Name SSU_2 I/O port Pin Function SSO2 output PA3 output SSO2_OE 1 0 PA3DDR 1 0 PA3 input (initial setting) 0 (6) PA2/SSI2 The pin function is switched as shown below according to the combination of the SSU_2 and the PA2DDR bit settings. Setting SSU_2 Module Name SSU_2 I/O port Pin Function SSI2 output PA2 output SSI2_OE 1 0 I/O Port PA2DDR 1 0 PA2 input (initial setting) 0 Rev. 2.00 Mar. 15, 2006 Page 268 of 754 REJ09B0199-0200 Section 9 I/O Ports (7) PA1/SSCK2 The pin function is switched as shown below according to the combination of the SSU_2 and the PA1DDR bit settings. Setting SSU_2 Module Name SSU_2 I/O port Pin Function SSCK2 output PA1 output SSCK2_OE 1 0 I/O Port PA1DDR 1 0 PA1 input (initial setting) 0 (8) PA0 The pin function is switched as shown below according to the PA0DDR bit setting. Setting I/O Port Module Name I/O port Pin Function PA0 output PA0 input (initial setting) PA0DDR 1 0 9.2.6 (1) Port B PB2 The pin function is switched as shown below according to the PB2DDR bit setting. Setting I/O Port Module Name I/O port Pin Function PB2 output PB2 input (initial setting) PB2DDR 1 0 Rev. 2.00 Mar. 15, 2006 Page 269 of 754 REJ09B0199-0200 Section 9 I/O Ports (2) PB1 The pin function is switched as shown below according to the PB1DDR bit setting. Setting I/O Port Module Name I/O port Pin Function PB1 output PB1 input (initial setting) PB1DDR 1 0 (3) PB0 The pin function is switched as shown below according to the PB0DDR bit setting. Setting I/O Port Module Name I/O port Pin Function PB0 output PB0 input (initial setting) PB0DDR 1 0 9.2.7 (1) Port D PD7/SCS1 The pin function is switched as shown below according to the combination of the SSU_1 and the PD7DDR bit settings. Setting SSU_2 Module Name SSU_1 I/O port Pin Function SCS1 output PD7 output PD7 input (initial setting) SCS1_OE 1 0 0 I/O Port PD7DDR 1 0 Rev. 2.00 Mar. 15, 2006 Page 270 of 754 REJ09B0199-0200 Section 9 I/O Ports (2) PD6/SSCK1 The pin function is switched as shown below according to the combination of the SSU_1 and the PD6DDR bit settings. Setting SSU_1 Module Name SSU_1 I/O port Pin Function SSCK1 output PD6 output PD6 input (initial setting) SSCK1_OE 1 0 0 I/O Port PD6DDR 1 0 (3) PD5/SSI1 The pin function is switched as shown below according to the combination of the SSU_1 and the PD5DDR bit settings. Setting SSU_1 Module Name SSU_1 I/O port Pin Function SSI1 output PD5 output PD5 input (initial setting) SSI1_OE 1 0 0 I/O Port PD5DDR 1 0 (4) PD4/SSO1 The pin function is switched as shown below according to the combination of the SSU_1 and the PD4DDR bit settings. Setting SSU_1 Module Name SSU_1 I/O port Pin Function SSO1 output PD4 output PD4 input (initial setting) SSO1_OE 1 0 0 I/O Port PD4DDR 1 0 Rev. 2.00 Mar. 15, 2006 Page 271 of 754 REJ09B0199-0200 Section 9 I/O Ports (5) PD3/SCS0 The pin function is switched as shown below according to the combination of the SSU_0 and the PD3DDR bit settings. Setting SSU_0 Module Name SSU_0 I/O port Pin Function SCS0 output PD3 output PD3 input (initial setting) SCS0_OE 1 0 0 I/O Port PD3DDR 1 0 (6) PD2/SSCK0 The pin function is switched as shown below according to the combination of the SSU_0 and the PD2DDR bit settings. Setting SSU_0 Module Name SSU_0 I/O port Pin Function SSCK0 output PD2 output PD2 input (initial setting) SSCK0_OE 1 0 0 I/O Port PD2DDR 1 0 (7) PD1/SSI0 The pin function is switched as shown below according to the combination of the SSU_0 and the PD1DDR bit settings. Setting SSU_0 Module Name SSU_0 I/O port Pin Function SSI0 output PD1 output PD1 input (initial setting) SSI0_OE 1 0 0 I/O Port PD1DDR 1 0 Rev. 2.00 Mar. 15, 2006 Page 272 of 754 REJ09B0199-0200 Section 9 I/O Ports (8) PD0/SSO0 The pin function is switched as shown below according to the combination of the SSU_0 and the PD0DDR bit settings. Setting SSU_0 Module Name SSU_0 I/O port Pin Function SSO0 output PD0 output PD0 input (initial setting) SSO0_OE 1 0 0 I/O Port PD0DDR 1 0 9.2.8 (1) Port H PH7, PH6, PH5, PH4, PH3, PH2, PH1, and PH0 Port H functions as an 8-bit I/O port and also functions as a realtime input port. Using port H as the realtime input port, the pin status of port H is stored in PHRTIDR by the following triggers: a low level, a falling edge, a rising edge, or both edges of pin IRQ14. The pin function is switched as shown below according to the PHnDDR bit setting. Setting I/O Port Module Name I/O port [Legend] n = 7 to 0 Pin Function PHn output PHn input (initial setting) PHnDDR 1 0 Rev. 2.00 Mar. 15, 2006 Page 273 of 754 REJ09B0199-0200 Section 9 I/O Ports 9.2.9 (1) Port I PI7, PI6, PI5, PI4, PI3, PI2, PI1, and PI0 The pin function is switched as shown below according to the PInDDR bit setting. Setting I/O Port Module Name I/O port [Legend] n = 7 to 0 Pin Function PIn output PIn input (initial setting) PInDDR 1 0 9.2.10 (1) Port J PJ7/TIOCA8/TIOCB8/TCLKH The pin function is switched as shown below according to the combination of the port function control register A (PFCRA), TPU_8, and PJ7DDR bit settings. Setting TPU_8 Module Name TPU_8 I/O port Pin Function TIOCB8 output PJ7 output PJ7 input (initial setting) TIOCB8_OE 1 0 0 I/O Port PJ7DDR 1 0 Rev. 2.00 Mar. 15, 2006 Page 274 of 754 REJ09B0199-0200 Section 9 I/O Ports (2) PJ6/TIOCA8 The pin function is switched as shown below according to the combination of the port function control register A (PFCRA), TPU_8, and PJ6DDR bit settings. Setting TPU_8 Module Name TPU_8 I/O port Pin Function TIOCA8 output PJ6 output PJ6 input (initial setting) TIOCA8_OE 1 0 0 I/O Port PJ6DDR 1 0 (3) PJ5/TIOCA7/TIOCB7/TCLKG The pin function is switched as shown below according to the combination of the port function control register A (PFCRA), TPU_7, and PJ5DDR bit settings. Setting TPU_7 Module Name TPU_7 I/O port Pin Function TIOCB7 output PJ5 output PJ5 input (initial setting) TIOCB7_OE 1 0 0 I/O Port PJ5DDR 1 0 (4) PJ4/TIOCA7 The pin function is switched as shown below according to the combination of the port function control register A (PFCRA), TPU_7, and PJ4DDR bit settings. Setting TPU_7 Module Name TPU_7 I/O port Pin Function TIOCA7 output PJ4 output PJ4 input (initial setting) TIOCA7_OE 1 0 0 I/O Port PJ4DDR 1 0 Rev. 2.00 Mar. 15, 2006 Page 275 of 754 REJ09B0199-0200 Section 9 I/O Ports (5) PJ3/TIOCC6/TIOCD6/TCLKF The pin function is switched as shown below according to the combination of the port function control register A (PFCRA), TPU_6, and PJ3DDR bit settings. Setting TPU_6 Module Name TPU_6 I/O port Pin Function TIOCD6 output PJ3 output PJ3 input (initial setting) TIOCD6_OE 1 0 0 I/O Port PJ3DDR 1 0 (6) PJ2/TIOCC6/TCLKE The pin function is switched as shown below according to the combination of the port function control register A (PFCRA), TPU_6, and PJ2DDR bit settings. Setting TPU_6 Module Name TPU_6 I/O port Pin Function TIOCC6 output PJ2 output PJ2 input (initial setting) TIOCC6_OE 1 0 0 I/O Port PJ2DDR 1 0 (7) PJ1/TIOCA6/TIOCB6 The pin function is switched as shown below according to the combination of the port function control register A (PFCRA), TPU_6, and PJ1DDR bit settings. Setting TPU_6 Module Name TPU_6 I/O port Pin Function TIOCB6 output PJ1 output PJ1 input (initial setting) TIOCB6_OE 1 0 0 I/O Port PJ1DDR 1 0 Rev. 2.00 Mar. 15, 2006 Page 276 of 754 REJ09B0199-0200 Section 9 I/O Ports (8) PJ0/TIOCA6 The pin function is switched as shown below according to the combination of the port function control register A (PFCRA), TPU_6, and PJ0DDR bit settings. Setting TPU_6 Module Name TPU_6 I/O port Pin Function TIOCA6 output PJ0 output PJ0 input (initial setting) TIOCA6_OE 1 0 0 I/O Port PJ0DDR 1 0 9.2.11 (1) Port K PK7/TIOCA11/TIOCB11 The pin function is switched as shown below according to the combination of the port function control register A (PFCRA), TPU_11, and PK7DDR bit settings. Setting TPU_11 Module Name TPU_11 I/O port Pin Function TIOCB11 output PK7 output PK7 input (initial setting) TIOCB11_OE 1 0 0 I/O Port PK7DDR 1 0 (2) PK6/TIOCA11 The pin function is switched as shown below according to the combination of the port function control register A (PFCRA), TPU_11, and PK6DDR bit settings. Setting TPU_11 Module Name TPU_11 I/O port Pin Function TIOCA11 output PK6 output PK6 input (initial setting) TIOCA11_OE 1 0 0 I/O Port PK6DDR 1 0 Rev. 2.00 Mar. 15, 2006 Page 277 of 754 REJ09B0199-0200 Section 9 I/O Ports (3) PK5/TIOCA10/TIOCB10 The pin function is switched as shown below according to the combination of the port function control register A (PFCRA), TPU_10, and PK5DDR bit settings. Setting TPU_10 Module Name TPU_10 I/O port Pin Function TIOCB10 output PK5 output PK5 input (initial setting) TIOCB10_OE 1 0 0 I/O Port PK5DDR 1 0 (4) PK4/TIOCA10 The pin function is switched as shown below according to the combination of the port function control register A (PFCRA), TPU_10, and PK4DDR bit settings. Setting TPU_10 Module Name TPU_10 I/O port Pin Function TIOCA10 output PK4 output PK4 input (initial setting) TIOCA10_OE 1 0 0 I/O Port PK4DDR 1 0 (5) PK3/TIOCC9/TIOCD9 The pin function is switched as shown below according to the combination of the port function control register A (PFCRA), TPU_9, and PK3DDR bit settings. Setting TPU_9 Module Name TPU_9 I/O port Pin Function TIOCD9 output PK3 output PK3 input (initial setting) TIOCD9_OE 1 0 0 I/O Port PK3DDR 1 0 Rev. 2.00 Mar. 15, 2006 Page 278 of 754 REJ09B0199-0200 Section 9 I/O Ports (6) PK2/TIOCC9 The pin function is switched as shown below according to the combination of the port function control register A (PFCRA), TPU_9, and PK2DDR bit settings. Setting TPU_9 Module Name TPU_6 I/O port Pin Function TIOCC9 output PK2 output PK2 input (initial setting) TIOCC9_OE 1 0 0 I/O Port PK2DDR 1 0 (7) PK1/TIOCA6/TIOCB6 The pin function is switched as shown below according to the combination of the port function control register A (PFCRA), TPU_9, and PK1DDR bit settings. Setting TPU_9 Module Name TPU_9 I/O port Pin Function TIOCB9 output PK1 output PK1 input (initial setting) TIOCB9_OE 1 0 0 I/O Port PK1DDR 1 0 (8) PK0/TIOCA9 The pin function is switched as shown below according to the combination of the port function control register A (PFCRA), TPU_9, and PK0DDR bit settings. Setting TPU_9 Module Name TPU_9 I/O port Pin Function TIOCA9 output PK0 output PK0 input (initial setting) TIOCA9_OE 1 0 0 I/O Port PK0DDR 1 0 Rev. 2.00 Mar. 15, 2006 Page 279 of 754 REJ09B0199-0200 Section 9 I/O Ports Table 9.4 Available Output Signals and Settings in Each Port Output Specification Signal Name Output Signal Name SCK3 Signal Selection Register Settings Peripheral Module Settings When SCMR_3.SMIF = 1: SCR_3.TE = 1 or SCR_3.RE = 1 while SMR_3.GM = 0, SCR.CKE [1, 0] = 01 or while SMR.GM = 1 When SCMR_3.SMIF = 0: SCR_3.TE = 1 or SCR_3.RE = 1 while SMR_3.C/A = 0, SCR_3.CKE [1, 0] = 01 or while SMR_3.C/A = 1, SCR_3.CKE 1 = 0 Port P1 6 SCK3_OE 4 P2 7 6 5 4 3 2 1 TxD3_OE TIOCB5_OE TIOCA5_OE TIOCA4_OE TIOCB4_OE TIOCD3_OE TIOCC3_OE SCS2_OE TxD3 TIOCB5 TIOCA5 TIOCA4 TIOCB4 TIOCD3 TIOCC3 SCS2 SCR.TE = 1 TPU.TIOR_5.IOB3 = 0, TPU.TIOR_5.IOB[1,0] = 01/10/11 TPU.TIOR_5.IOA3 = 0, TPU.TIOR_5.IOA[1,0] = 01/10/11 TPU.TIOR_4.IOA3 = 0, TPU.TIOR_4.IOA[1,0] = 01/10/11 TPU.TIOR_4.IOB3 = 0, TPU.TIOR_4.IOB[1,0] = 01/10/11 TPU.TMDR.BFB = 0, TPU.TIORL_3.IOD3 = 0, TPU.TIORL_3.IOD[1,0] = 01/10/11 TPU.TMDR.BFA = 0, TPU.TIORL_3.IOC3 = 0, TPU.TIORL_3.IOD[1,0] = 01/10/11 SSU.SSCRH_2.CSS1 = 1, SSU.SSCRH_2.CSS0 = 0, or SSU.SSCRH_2.CSS1 = 1, SSU.SSCRH_2.CSS0 = 1 while SSU.SSCRL_2.SSUMS = 0, SSU.SSCRH_2.MSS = 1 TIOCA3_OE 0 P3 7 TIOCB3_OE TIOCB2_OE PO15_OE 6 TIOCA2_OE PO14_OE 5 TIOCB1_OE PO13_OE TIOCA3 TIOCB3 TIOCB2 PO15 TIOCA2 PO14 TIOCB1 PO13 TPU.TIORH_3.IOA3 = 0, TPU.TIORH_3.IOA[1,0] = 01/10/11 TPU.TIORH_3.IOB3 = 0, TPU.TIORH_3.IOB[1,0] = 01/10/11 TPU.TIOR_2.IOB3 = 0, TPU.TIOR_2.IOB[1,0] = 01/10/11 NDERH.NDER15 = 1 TPU.TIOR_2.IOA3 = 0, TPU.TIOR_2.IOA[1,0] = 01/10/11 NDERH.NDER14 = 1 TPU.TIOR_1.IOB3 = 0, TPU.TIOR_1.IOB[1,0] = 01/10/11 NDERH.NDER13 = 1 Rev. 2.00 Mar. 15, 2006 Page 280 of 754 REJ09B0199-0200 Section 9 I/O Ports Port P3 4 Output Specification Signal Name TIOCA1_OE PO12_OE 3 TIOCD0_OE PO11_OE 2 TIOCC0_OE PO10_OE 1 TIOCB0_OE PO9_OE 0 TIOCA0_OE PO8_OE Output Signal Name TIOCA1 PO12 TIOCD0 PO11 TIOCC0 PO10 TIOCB0 PO9 TIOCA0 PO8 SCK4 Signal Selection Register Settings Peripheral Module Settings TPU.TIOR_1.IOA3 = 0, TPU.TIOR_1.IOA[1,0] = 01/10/11 NDERH.NDER12 = 1 TPU.TMDR_0.BFB = 0, TPU.TIORL_0.IOD3 = 0, TPU.TIORL_0.IOD[1,0] = 01/10/11 NDERH.NDER11 = 1 TPU.TMDR_0.BFA = 0, TPU.TIORL_0.IOC3 = 0, TPU.TIORL_0.IOD[1,0] = 01/10/11 NDERH.NDER10 = 1 TPU.TIORH_0.IOB3 = 0, TPU.TIORH_0.IOB[1,0] = 01/10/11 NDERH.NDER9 = 1 TPU.TIORH_0.IOA3 = 0, TPU.TIORH_0.IOA[1,0] = 01/10/11 NDERH.NDER8 = 1 When SCMR_4.SMIF = 1: SCR_4.TE = 1 or SCR_4.RE = 1 while SMR_4.GM = 0, SCR_4.CKE [1, 0] = 01 or while SMR_4.GM = 1 When SCMR_4.SMIF = 0: SCR_4.TE = 1 or SCR_4.RE = 1 while SMR_4.C/A = 0, SCR_4.CKE [1, 0] = 01 or while SMR_4.C/A = 1, SCR_4.CKE 1 = 0 P6 2 SCK4_OE 0 PA 7 3 TxD4_OE B_OE SSO2_OE TxD4 B SSI02 SCR.TE = 1 PADDR.PA7DDR = 1, SCKCR.PSTOP1 = 0, SCKCR.POSEL1 = 0 When SSU.SSCRL_2.SSUMS = 0, SSU.SSCRH_2.MSS = 1: SSU.SSCRH_2.BIDE = 0, SSU.SSER_2.TE = 1 or SSU.SSCRH_2.BIDE = 1, SSU.SSER_2.RE = 0, SSU.SSER_2.TE = 1 When SSU.SSCRL_2.SSUMS = 0, SSU.SSCRH_2.MSS = 0: SSU.SSCRH_2.BIDE = 1, SSU.SSER_2.RE = 0, SSU.SSER_1.TE = 1 When SSU.SSCRL_2.SSUMS = 1: SSU.SSER_2.TE = 1 Rev. 2.00 Mar. 15, 2006 Page 281 of 754 REJ09B0199-0200 Section 9 I/O Ports Port PA 2 Output Specification Signal Name SSI2_OE Output Signal Name SSI2 Signal Selection Register Settings Peripheral Module Settings SSU.SSCRL_2SSUMS = 0, SSU.SSCRH_2.MSS = 0 SSU.SSCRH_2.BIDE = 0, SSU.SSER_2.TE = 1 1 PD 7 SSCK2_OE SCS1_OE SSCK2 SCS1 SSU.SSCRH_2.MSS = 1, SSU.SSCRH_2.SCKS = 1 SSU.SSCRH_0.CSS1 = 1, SSU.SSCRH_0.CSS0 = 0 or SSU.SSCRH_0.CSS1 = 1, SSU.SSCRH_0.CSS0 = 1 while SSU.SSCRL_0.SSUMS = 0, SSU.SSCRH_0.MSS = 1 6 5 4 SSCK1_OE SSI1_OE SSO1_OE SSCK1 SSI1 SSO1 SSU.SSCRH_1.MSS = 1, SSU.SSCRH_1.SCKS = 1 SSU.SSCRL_1.SSUMS = 0, SSU.SSCRH_1.MSS = 0 SSU.SSCRH_1.BIDE = 0, SSU.SSER_1.TE = 1 When SSU.SSCRL_1.SSUMS = 0, SSU.SSCRH_1.MSS = 1: SSU.SSCRH_1.BIDE = 0, SSU.SSER_1.TE = 1 or SSU.SSCRH_1.BIDE = 1, SSU.SSER_1.RE = 0, SSU.SSER_1.TE = 1 When SSU.SSCRL_1.SSUMS = 0, SSU.SSCRH_1.MSS = 0: SSU.SSCRH_1.BIDE = 1, SSU.SSER_1.RE = 0, SSU.SSER_1.TE = 1 When SSU.SSCRL_1.SSUMS = 1: SSU.SSER_1.TE = 1 3 SCS0_OE SCS0 SSU.SSCRH_0.CSS1 = 1, SSU.SSCRH_0.CSS0 = 0 or SSU.SSCRH_0.CSS1 = 1, SSU.SSCRH_0.CSS0 = 1 while SSU.SSCRL_0.SSUMS = 0, SSU.SSCRH_0.MSS = 1 2 1 0 SSCK0_OE SSI0_OE SSO0_OE SSCK0 SSI0 SSO0 SSU.SSCRH_0.MSS = 1, SSU.SSCRH_0.SCKS = 1 SSU.SSCRL_0.SSUMS = 0, SSU.SSCRH_0.MSS = 0 SSU.SSCRH_0.BIDE = 0, SSU.SSER_0.TE = 1 When SSU.SSCRL_0.SSUMS = 0, SSU.SSCRH_0.MSS = 1: SSU.SSCRH_0.BIDE = 0, SSU.SSER_0.TE = 1 or SSU.SSCRH_0.BIDE = 1, SSU.SSER_0.RE = 0, SSU.SSER_0.TE = 1 When SSU.SSCRL_0.SSUMS = 0, SSU.SSCRH_0.MSS = 0: SSU.SSCRH_0.BIDE = 1, SSU.SSER_0.RE = 0, SSU.SSER_0.TE = 1 When SSU.SSCRL_0.SSUMS = 1: SSU.SSER_0.TE = 1 Rev. 2.00 Mar. 15, 2006 Page 282 of 754 REJ09B0199-0200 Section 9 I/O Ports Port PJ 7 6 5 4 3 2 1 0 PK 7 6 5 4 3 2 1 0 Output Specification Signal Name TIOCB8_OE TIOCA8_OE TIOCB7_OE TIOCA7_OE TIOCD6_OE TIOCC6_OE TIOCB6_OE TIOCA6_OE TIOCB11_OE TIOCA11_OE TIOCB10_OE TIOCA10_OE TIOCD9_OE TIOCC9_OE TIOCB9_OE TIOCA9_OE Output Signal Name TIOCB8 TIOCA8 TIOCB7 TIOCA7 TIOCD6 TIOCC6 TIOCB6 TIOCA6 TIOCB11 TIOCA11 TIOCB10 TIOCA10 TIOCD9 TIOCC9 TIOCB9 TIOCA9 Signal Selection Register Settings Peripheral Module Settings TPU.TIOR_8.IOB3 = 0, TPU.TIOR_8.IOB[1, 0] = 01/10/11 TPU.TIOR_8.IOA3 = 0, TPU.TIOR_8.IOA[1, 0] = 01/10/11 TPU.TIOR_7.IOB3 = 0, TPU.TIOR_7.IOB[1, 0] = 01/10/11 TPU.TIOR_7.IOA3 = 0, TPU.TIOR_7.IOA[1, 0] = 01/10/11 TPU.TMDR_6.BFB = 0, TPU.TIORL_6.IOD3 = 0 TPU.TIORL_6.IOD[1, 0] = 01/10/11 TPU.TMDR_6.BFA = 0, TPU.TIORL_6.IOC3 = 0 TPU.TIORL_6.IOC[1, 0] = 01/10/11 TPU.TIORH_6.IOB3 = 0, TPU.TIORH_6.IOB[1, 0] = 01/10/11 TPU.TIORH_6.IOA3 = 0, TPU.TIORH_6.IOA[1, 0] = 01/10/11 TPU.TIOR_11.IOB3 = 0, TPU.TIOR_11.IOB[1, 0] = 01/10/11 TPU.TIOR_11.IOA3 = 0, TPU.TIOR_11.IOA[1, 0] = 01/10/11 TPU.TIOR_10.IOB3 = 0, TPU.TIOR_10.IOB[1, 0] = 01/10/11 TPU.TIOR_10.IOA3 = 0, TPU.TIOR_10.IOA[1, 0] = 01/10/11 TPU.TMDR_9.BFB = 0, TPU.TIORL_9.IOD3 = 0 TPU.TIORL_9.IOD[1, 0] = 01/10/11 TPU.TMDR_9.BFA = 0, TPU.TIORL_9.IOC3 = 0 TPU.TIORL_9.IOC[1, 0] = 01/10/11 TPU.TIOR_9.IOB3 = 0, TPU.TIOR_9.IOB[1, 0] = 01/10/11 TPU.TIOR_9.IOA3 = 0, TPU.TIOR_9.IOA[1, 0] = 01/10/11 Rev. 2.00 Mar. 15, 2006 Page 283 of 754 REJ09B0199-0200 Section 9 I/O Ports 9.3 Port Function Controller The port function controller controls the I/O ports. The port function controller incorporates the following registers. * Port function control register 9 (PFCR9) * Port function control register A (PFCRA) * Port function control register B (PFCRB) 9.3.1 Port Function Control Register 9 (PFCR9) PFCR9 selects the multiple functions for the TPU (unit 0) I/O pins. Bit Bit Name Initial Value R/W 7 TPUMS5 0 R/W 6 TPUMS4 0 R/W 5 TPUMS3A 0 R/W 4 TPUMS3B 0 R/W 3 TPUMS2 0 R/W 2 TPUMS1 0 R/W 1 TPUMS0A 0 R/W 0 TPUMS0B 0 R/W Bit 7 Bit Name TPUMS5 Initial Value 0 R/W R/W Description TPU I/O Pin Multiplex Function Select Selects TIOCA5 function 0: Specifies P26 as output compare output and input capture 1: Specifies P27 as input capture input and P26 as output compare 6 TPUMS4 0 R/W TPU I/O Pin Multiplex Function Select Selects TIOCA4 function 0: Specifies P25 as output compare output and input capture 1: Specifies P24 as input capture input and P25 as output compare 5 TPUMS3A 0 R/W TPU I/O Pin Multiplex Function Select Selects TIOCA3 function 0: Specifies P21 as output compare output and input capture 1: Specifies P20 as input capture input and P21 as output compare Rev. 2.00 Mar. 15, 2006 Page 284 of 754 REJ09B0199-0200 Section 9 I/O Ports Bit 4 Bit Name Initial Value R/W R/W Description TPU I/O Pin Multiplex Function Select Selects TIOCC3 function 0: Specifies P22 as output compare output and input capture 1: Specifies P23 as input capture input and P22 as output compare TPUMS3B 0 3 TPUMS2 0 R/W TPU I/O Pin Multiplex Function Select Selects TIOCA2 function 0: Specifies P36 as output compare output and input capture 1: Specifies P37 as input capture input and P36 as output compare 2 TPUMS1 0 R/W TPU I/O Pin Multiplex Function Select Selects TIOCA1 function 0: Specifies P34 as output compare output and input capture 1: Specifies P35 as input capture input and P34 as output compare 1 TPUMS0A 0 R/W TPU I/O Pin Multiplex Function Select Selects TIOCA0 function 0: Specifies P30 as output compare output and input capture 1: Specifies P31 as input capture input and P30 as output compare 0 TPUMS0B 0 R/W TPU I/O Pin Multiplex Function Select Selects TIOCC0 function 0: Specifies P32 as output compare output and input capture 1: Specifies P33 as input capture input and P32 as output compare Rev. 2.00 Mar. 15, 2006 Page 285 of 754 REJ09B0199-0200 Section 9 I/O Ports 9.3.2 Port Function Control Register A (PFCRA) PFCRA selects the multiple functions for the TPU (unit 1) I/O pins. Bit Bit Name Initial Value R/W 7 TPUMS11 0 R/W 6 TPUMS10 0 R/W 5 TPUMS9A 0 R/W 4 TPUMS9B 0 R/W 3 TPUMS8 0 R/W 2 TPUMS7 0 R/W 1 TPUMS6A 0 R/W 0 TPUMS6B 0 R/W Bit 7 Bit Name Initial Value R/W R/W Description TPU I/O Pin Multiplex Function Select Selects TIOCA11 function 0: Specifies PK6 as output compare output and input capture 1: Specifies PK7 as input capture input and PK6 as output compare TPUMS11 0 6 TPUMS10 0 R/W TPU I/O Pin Multiplex Function Select Selects TIOCA10 function 0: Specifies PK4 as output compare output and input capture 1: Specifies PK5 as input capture input and PK4 as output compare 5 TPUMS9A 0 R/W TPU I/O Pin Multiplex Function Select Selects TIOCA9 function 0: Specifies PK0 as output compare output and input capture 1: Specifies PK1 as input capture input and PK0 as output compare 4 TPUMS9B 0 R/W TPU I/O Pin Multiplex Function Select Selects TIOCC9 function 0: Specifies PK2 as output compare output and input capture 1: Specifies PK3 as input capture input and PK2 as output compare Rev. 2.00 Mar. 15, 2006 Page 286 of 754 REJ09B0199-0200 Section 9 I/O Ports Bit 3 Bit Name TPUMS8 Initial Value 0 R/W R/W Description TPU I/O Pin Multiplex Function Select Selects TIOCA8 function 0: Specifies PJ6 as output compare output and input capture 1: Specifies PJ7 as input capture input and PJ6 as output compare 2 TPUMS7 0 R/W TPU I/O Pin Multiplex Function Select Selects TIOCA7 function 0: Specifies PJ4 as output compare output and input capture 1: Specifies PJ5 as input capture input and PJ4 as output compare 1 TPUMS6A 0 R/W TPU I/O Pin Multiplex Function Select Selects TIOCA6 function 0: Specifies PJ0 as output compare output and input capture 1: Specifies PJ1 as input capture input and PJ0 as output compare 0 TPUMS6B 0 R/W TPU I/O Pin Multiplex Function Select Selects TIOCC6 function 0: Specifies PJ2 as output compare output and input capture 1: Specifies PJ3 as input capture input and PJ2 as output compare 9.3.3 Port Function Control Register B (PFCRB) PFCRB selects the input pins for IRQ15 to IRQ8. Bit Bit Name Initial Value R/W 7 ITS15 0 R/W 6 ITS14 0 R/W 5 ITS13 0 R/W 4 ITS12 0 R/W 3 ITS11 0 R/W 2 ITS10 0 R/W 1 ITS9 0 R/W 0 ITS8 0 R/W Rev. 2.00 Mar. 15, 2006 Page 287 of 754 REJ09B0199-0200 Section 9 I/O Ports Bit 7 Bit Name ITS15 Initial Value 0 R/W R/W Description IRQ15 Pin Select Selects an input pin for IRQ15. 0: Pin P27 must not be used as IRQ15-A input 1: Pin P67 is used as IRQ15-B input 6 ITS14 0 R/W IRQ14 Pin Select Selects an input pin for IRQ14. 0: Pin P26 must not be used as IRQ14-A input 1: Pin P66 is used as IRQ14-B input 5 ITS13 0 R/W IRQ13 Pin Select Selects an input pin for IRQ13. 0: Pin P25 must not be used as IRQ13-A input 1: Pin P65 is used as IRQ13-B input 4 ITS12 0 R/W IRQ12 Pin Select Selects an input pin for IRQ12. 0: Pin P24 must not be used as IRQ12-A input 1: Pin P64 is used as IRQ12-B input 3 ITS11 0 R/W IRQ11 Pin Select Selects an input pin for IRQ11. 0: Pin P23 is used as IRQ11-A input 1: Pin P63 is used as IRQ11-B input 2 ITS10 0 R/W IRQ10 Pin Select Selects an input pin for IRQ10. 0: Pin P22 is used as IRQ10-A input 1: Pin P62 is used as IRQ10-B input 1 ITS9 0 R/W IRQ9 Pin Select Selects an input pin for IRQ9. 0: Pin P21 is used as IRQ9-A input 1: Pin P61 is used as IRQ9-B input 0 ITS8 0 R/W IRQ8 Pin Select Selects an input pin for IRQ8. 0: Pin P20 is used as IRQ8-A input 1: Pin P60 is used as IRQ8-B input Rev. 2.00 Mar. 15, 2006 Page 288 of 754 REJ09B0199-0200 Section 9 I/O Ports 9.4 9.4.1 * Usage Notes Notes on Input Buffer Control Register (ICR) Setting * * When the ICR setting is changed, the LSI may malfunction due to an edge occurred internally according to the pin states. To change the ICR setting, fix the pin high or disable the input function corresponding to the pin by setting the on-chip module registers. If an input is enabled by setting ICR while multiple input functions are assigned to the pin, the pin state is reflected in all the inputs of individual modules. Care must be taken for the settings of unused input function on each module side. When a pin is used as an output, data to be output from the pin will be latched as the pin state if the input function corresponding to the pin is enabled. To use the pin as an output, disable the input function for the pin by setting ICR. Notes on Port Function Control Register (PFCR) Settings 9.4.2 * The PFC controls I/O ports. To specify the function of each pin, specify the input/output destination before enabling the input/output function. * When the input/output destination is changed by the corresponding selection bit, an edge may occur if the previous pin level differs from the pin level after the change. To change the pin direction correctly, follow the procedure shown below. 1. Disable the input function corresponding to the pin by the on-chip module registers. 2. Select the input function by setting PFCR. 3. Enable the input function. * If a pin function has both a selection bit that modifies the input/output destination and an enable bit that enables the pin function, first specify the input/output destination by the selection bit and then enable the pin function by the enable bit. Rev. 2.00 Mar. 15, 2006 Page 289 of 754 REJ09B0199-0200 Section 9 I/O Ports Rev. 2.00 Mar. 15, 2006 Page 290 of 754 REJ09B0199-0200 Section 10 16-Bit Timer Pulse Unit (TPU) Section 10 16-Bit Timer Pulse Unit (TPU) This LSI has two on-chip 16-bit timer pulse units (TPU): unit 0 and unit1. Each unit comprises six 16-bit timer channels, that is, there are 12 timer channels in total. Table 10.1 shows the unit configuration for each product. Table 10.2 is a list of the functions and figure 10.1 is a block diagram for unit 0. Table 10.3 and figure 10.2 are for unit 1. This section describes unit 0, which has the same functions as the other unit. 10.1 Features * Maximum 16-pulse input/output * Selection of eight counter input clocks for each channel * The following operations can be set for each channel: Waveform output at compare match Input capture function Counter clear operation Synchronous operations: * Multiple timer counters (TCNT) can be written to simultaneously * Simultaneous clearing by compare match and input capture possible * Simultaneous input/output for registers possible by counter synchronous operation * Maximum of 15-phase PWM output possible by combination with synchronous operation * Buffer operation settable for channels 0 and 3 * Phase counting mode settable independently for each of channels 1, 2, 4, and 5 * Cascaded operation * Fast access via internal 16-bit bus * 26 interrupt sources * Automatic transfer of register data * Programmable pulse generator (PPG) output trigger can be generated (supported only by unit 0) * Conversion start trigger for the A/D converter can be generated (supported only by unit 0) * Module stop mode can be set Rev. 2.00 Mar. 15, 2006 Page 291 of 754 REJ09B0199-0200 Section 10 16-Bit Timer Pulse Unit (TPU) Table 10.1 Unit Configuration for Each Product Product H8SX/1582 Unit Configuration Unit 0 Unit 1 Channel Configuration Channels 0 to 5 Channels 6 to 11 Table 10.2 TPU Functions (Unit 0) Item Count clock Channel 0 P/1 P/4 P/16 P/64 TCLKA TCLKB TCLKC TCLKD TGRA_0 TGRB_0 TGRC_0 TGRD_0 TIOCA0 TIOCB0 TIOCC0 TIOCD0 TGR compare match or input capture O O O O O O O Channel 1 P/1 P/4 P/16 P/64 P/256 TCLKA TCLKB TGRA_1 TGRB_1 TIOCA1 TIOCB1 Channel 2 P/1 P/4 P/16 P/64 P/1024 TCLKA TCLKB TCLKC TGRA_2 TGRB_2 TIOCA2 TIOCB2 Channel 3 P/1 P/4 P/16 P/64 P/256 P/1024 P/4096 TCLKA TGRA_3 TGRB_3 TGRC_3 TGRD_3 TIOCA3 TIOCB3 TIOCC3 TIOCD3 TGR compare match or input capture O O O O O O O Channel 4 P/1 P/4 P/16 P/64 P/1024 TCLKA TCLKC TGRA_4 TGRB_4 TIOCA4 TIOCB4 Channel 5 P/1 P/4 P/16 P/64 P/256 TCLKA TCLKC TCLKD TGRA_5 TGRB_5 TIOCA5 TIOCB5 General registers (TGR) General registers/ buffer registers I/O pins Counter clear function TGR compare match or input capture O O O O O O O TGR compare match or input capture O O O O O O O TGR compare match or input capture O O O O O O O TGR compare match or input capture O O O O O O O Compare match output 0 output 1 output Toggle output Input capture function Synchronous operation PWM mode Phase counting mode Buffer operation Rev. 2.00 Mar. 15, 2006 Page 292 of 754 REJ09B0199-0200 Section 10 16-Bit Timer Pulse Unit (TPU) Item DTC activation Channel 0 TGR compare match or input capture TGRA_0 compare match or input capture TGRA_0 compare match or input capture TGRA_0/ TGRB_0 compare match or input capture 5 sources Compare match or input capture 0A Compare match or input capture 0B Compare match or input capture 0C Compare match or input capture 0D Overflow Channel 1 TGR compare match or input capture TGRA_1 compare match or input capture TGRA_1 compare match or input capture TGRA_1/ TGRB_1 compare match or input capture 4 sources Compare match or input capture 1A Compare match or input capture 1B Overflow Underflow Channel 2 TGR compare match or input capture TGRA_2 compare match or input capture TGRA_2 compare match or input capture TGRA_2/ TGRB_2 compare match or input capture 4 sources Compare match or input capture 2A Compare match or input capture 2B Overflow Underflow Channel 3 TGR compare match or input capture TGRA_3 compare match or input capture TGRA_3 compare match or input capture TGRA_3/ TGRB_3 compare match or input capture 5 sources Compare match or input capture 3A Compare match or input capture 3B Compare match or input capture 3C Compare match or input capture 3D Overflow Channel 4 TGR compare match or input capture TGRA_4 compare match or input capture TGRA_4 compare match or input capture Channel 5 TGR compare match or input capture TGRA_5 compare match or input capture TGRA_5 compare match or input capture DMAC activation A/D converter trigger PPG trigger Interrupt sources 4 sources Compare match or input capture 4A Compare match or input capture 4B Overflow Underflow 4 sources Compare match or input capture 5A Compare match or input capture 5B Overflow Underflow [Legend] Possible O: : Not possible Rev. 2.00 Mar. 15, 2006 Page 293 of 754 REJ09B0199-0200 Section 10 16-Bit Timer Pulse Unit (TPU) Table 10.3 TPU Functions (Unit 1) Item Count clock Channel 6 P/1 P/4 P/16 P/64 TCLKE TCLKF TCLKG TCLKH TGRA_6 TGRB_6 TGRC_6 TGRD_6 TIOCA6 TIOCB6 TIOCC6 TIOCD6 TGR compare match or input capture O O O O O O O TGR compare match or input capture TGRA_6 compare match or input capture Channel 7 P/1 P/4 P/16 P/64 P/256 TCLKE TCLKF TGRA_7 TGRB_7 TIOCA7 TIOCB7 Channel 8 P/1 P/4 P/16 P/64 P/1024 TCLKE TCLKF TCLKG TGRA_8 TGRB_8 TIOCA8 TIOCB8 Channel 9 P/1 P/4 P/16 P/64 P/256 P/1024 P/4096 TCLKE TGRA_9 TGRB_9 TGRC_9 TGRD_9 TIOCA9 TIOCB9 TIOCC9 TIOCD9 TGR compare match or input capture O O O O O O O TGR compare match or input capture TGRA_9 compare match or input capture Channel 10 Channel 11 P/1 P/4 P/16 P/64 P/1024 TCLKE TCLKG TGRA_10 TGRB_10 TIOCA10 TIOCB10 P/1 P/4 P/16 P/64 P/256 TCLKE TCLKG TCLKH TGRA_11 TGRB_11 TIOCA11 TIOCB11 General registers (TGR) General registers/ buffer registers I/O pins Counter clear function TGR compare match or input capture O O O O O O O TGR compare match or input capture TGRA_7 compare match or input capture TGR compare match or input capture O O O O O O O TGR compare match or input capture TGRA_8 compare match or input capture TGR compare match or input capture O O O O O O O TGR compare match or input capture TGRA_10 compare match or input capture TGR compare match or input capture O O O O O O O TGR compare match or input capture TGRA_11 compare match or input capture Compare match output 0 output 1 output Toggle output Input capture function Synchronous operation PWM mode Phase counting mode Buffer operation DTC activation DMAC activation Rev. 2.00 Mar. 15, 2006 Page 294 of 754 REJ09B0199-0200 Section 10 16-Bit Timer Pulse Unit (TPU) Item Interrupt sources Channel 6 5 sources Compare match or input capture 6A Compare match or input capture 6B Compare match or input capture 6C Compare match or input capture 6D Overflow Channel 7 4 sources Compare match or input capture 7A Compare match or input capture 7B Overflow Underflow Channel 8 4 sources Compare match or input capture 8A Compare match or input capture 8B Overflow Underflow Channel 9 5 sources Compare match or input capture 9A Compare match or input capture 9B Compare match or input capture 9C Compare match or input capture 9D Overflow Channel 10 Channel 11 4 sources Compare match or input capture 10A Compare match or input capture 10B Overflow Underflow 4 sources Compare match or input capture 11A Compare match or input capture 11B Overflow Underflow [Legend] Possible O: : Not possible Rev. 2.00 Mar. 15, 2006 Page 295 of 754 REJ09B0199-0200 Section 10 16-Bit Timer Pulse Unit (TPU) TIORH TIORL TMDR Channel 3 TSR TGRC TGRD TGRA TGRB TCNT Control logic for channels 3 to 5 Input/output pins TIOCA3 Channel 3: TIOCB3 TIOCC3 TIOCD3 TIOCA4 Channel 4: TIOCB4 TIOCA5 Channel 5: TIOCB5 Channel 5 TIOR TMDR Channel 2 TSR Clock input Internal clock: P/1 P/4 P/16 P/64 P/256 P/1024 P/4096 External clock: TCLKA TCLKB TCLKC TCLKD TIER TCR Module data bus TSTR TSYR TGRA Bus interface TGRB TCNT Interrupt request signals Channel 3: TGI3A TGI3B TGI3C TGI3D TCI3V Channel 4: TGI4A TGI4B TCI4V TCI4U Channel 5: TGI5A TGI5B TCI5V TCI5U TMDR Channel 4 TSR TIER TCR TIOR TMDR TSR TIER TCR TGRA TGRB TCNT Common Control logic Internal data bus A/D conversion start request signal PPG output trigger signal TIOR TIER TCR TGRA TGRB TCNT Control logic for channels 0 to 2 TIORH TIORL TMDR Input/output pins TIOCA0 Channel 0: TIOCB0 TIOCC0 TIOCD0 TIOCA1 Channel 1: TIOCB1 TIOCA2 Channel 2: TIOCB2 Interrupt request signals Channel 0: TGI0A TGI0B TGI0C TGI0D TCI0V Channel 1: TGI1A TGI1B TCI1V TCI1U Channel 2: TGI2A TGI2B TCI2V TCI2U TMDR Channel 1 TSR TGRA TIOR Channel 0 TSR TIER TCR TGRB TGRC TGRD TGRB TCNT TCNT [Legend] TSTR: TSYR: TCR: TMDR: TIOR (H, L): Timer start register Timer synchronous register Timer control register Timer mode register Timer I/O control registers (H, L) TIER: TSR: TGR (A, B, C, D): TCNT: TIER TCR Timer interrupt enable register Timer status register Timer general registers (A, B, C, D) Timer counter Figure 10.1 Block Diagram of TPU (Unit 0) Rev. 2.00 Mar. 15, 2006 Page 296 of 754 REJ09B0199-0200 TGRA Section 10 16-Bit Timer Pulse Unit (TPU) TIORH TIORL TMDR Channel 11 TSR TGRC TGRD TGRA TGRB TCNT Control logic for channels 9 to 11 Input/output pins TIOCA9 Channel 9: TIOCB9 TIOCC9 TIOCD9 Channel 10: TIOCA10 TIOCB10 Channel 11: TIOCA11 TIOCB11 Channel 9 TIOR TMDR Channel 8 TSR Clock input Internal clock: P/1 P/4 P/16 P/64 P/256 P/1024 P/4096 External clock: TCLKE TCLKF TCLKG TCLKH TIER TCR Module data bus TSTRB TSYRB TGRA Bus interface TGRB TCNT Interrupt request signals Channel 9: TGI9A TGI9B TGI9C TGI9D TCI9V Channel 10: TGI10A TGI10B TCI10V TCI10U Channel 11: TGI11A TGI11B TCI11V TCI11U TMDR Channel 10 TSR TIER TCR TIOR TMDR TSR TIER TCR TGRA TGRB TCNT Common Control logic Internal data bus TIOR TIER TCR TGRA TGRB TCNT Control logic for channels 6 to 8 TIORH TIORL TMDR Input/output pins TIOCA6 Channel 6: TIOCB6 TIOCC6 TIOCD6 TIOCA7 Channel 7: TIOCB7 TIOCA8 Channel 8: TIOCB8 Interrupt request signals Channel 6: TGI6A TGI6B TGI6C TGI6D TCI6V Channel 7: TGI7A TGI7B TCI7V TCI7U Channel 8: TGI8A TGI8B TCI8V TCI8U TMDR Channel 7 TSR TGRA TIOR Channel 6 TSR TIER TCR TGRB TGRC TGRD TGRB TCNT TCNT [Legend] TSTRB: TSYRB: TCR: TMDR: TIOR (H, L): Timer start register Timer synchronous register Timer control register Timer mode register Timer I/O control registers (H, L) TIER: TSR: TGR (A, B, C, D): TCNT: TIER TCR Timer interrupt enable register Timer status register Timer general registers (A, B, C, D) Timer counter Figure 10.2 Block Diagram of TPU (Unit 1) TGRA Rev. 2.00 Mar. 15, 2006 Page 297 of 754 REJ09B0199-0200 Section 10 16-Bit Timer Pulse Unit (TPU) 10.2 Input/Output Pins Table 10.4 shows TPU pin configurations. Table 10.4 Pin Configuration Unit 0 Channel All Symbol TCLKA I/O Input Function External clock A input pin (Channel 1 and 5 phase counting mode A phase input) TCLKB Input External clock B input pin (Channel 1 and 5 phase counting mode B phase input) TCLKC Input External clock C input pin (Channel 2 and 4 phase counting mode A phase input) TCLKD Input External clock D input pin (Channel 2 and 4 phase counting mode B phase input) 0 TIOCA0 TIOCB0 TIOCC0 TIOCD0 1 TIOCA1 TIOCB1 2 TIOCA2 TIOCB2 3 TIOCA3 TIOCB3 TIOCC3 TIOCD3 4 TIOCA4 TIOCB4 5 TIOCA5 TIOCB5 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O TGRA_0 input capture input/output compare output/PWM output pin TGRB_0 input capture input/output compare output/PWM output pin TGRC_0 input capture input/output compare output/PWM output pin TGRD_0 input capture input/output compare output/PWM output pin TGRA_1 input capture input/output compare output/PWM output pin TGRB_1 input capture input/output compare output/PWM output pin TGRA_2 input capture input/output compare output/PWM output pin TGRB_2 input capture input/output compare output/PWM output pin TGRA_3 input capture input/output compare output/PWM output pin TGRB_3 input capture input/output compare output/PWM output pin TGRC_3 input capture input/output compare output/PWM output pin TGRD_3 input capture input/output compare output/PWM output pin TGRA_4 input capture input/output compare output/PWM output pin TGRB_4 input capture input/output compare output/PWM output pin TGRA_5 input capture input/output compare output/PWM output pin TGRB_5 input capture input/output compare output/PWM output pin Rev. 2.00 Mar. 15, 2006 Page 298 of 754 REJ09B0199-0200 Section 10 16-Bit Timer Pulse Unit (TPU) Unit 1 Channel All Symbol TCLKE I/O Input Function External clock A input pin (Channel 7 and 11 phase counting mode A phase input) TCLKF Input External clock B input pin (Channel 7 and 11 phase counting mode B phase input) TCLKG Input External clock C input pin (Channel 8 and 10 phase counting mode A phase input) TCLKH Input External clock D input pin (Channel 8 and 10 phase counting mode B phase input) 6 TIOCA6 TIOCB6 TIOCC6 TIOCD6 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O TGRA_6 input capture input/output compare output/PWM output pin TGRB_6 input capture input/output compare output/PWM output pin TGRC_6 input capture input/output compare output/PWM output pin TGRD_6 input capture input/output compare output/PWM output pin TGRA_7 input capture input/output compare output/PWM output pin TGRB_7 input capture input/output compare output/PWM output pin TGRA_8 input capture input/output compare output/PWM output pin TGRB_8 input capture input/output compare output/PWM output pin TGRA_9 input capture input/output compare output/PWM output pin TGRB_9 input capture input/output compare output/PWM output pin TGRC_9 input capture input/output compare output/PWM output pin TGRD_9 input capture input/output compare output/PWM output pin TGRA_10 input capture input/output compare output/PWM output pin TGRB_10 input capture input/output compare output/PWM output pin TGRA_11 input capture input/output compare output/PWM output pin TGRB_11 input capture input/output compare output/PWM output pin 7 TIOCA7 TIOCB7 8 TIOCA8 TIOCB8 9 TIOCA9 TIOCB9 TIOCC9 TIOCD9 10 TIOCA10 TIOCB10 11 TIOCA11 TIOCB11 Rev. 2.00 Mar. 15, 2006 Page 299 of 754 REJ09B0199-0200 Section 10 16-Bit Timer Pulse Unit (TPU) 10.3 Register Descriptions The TPU has the following registers in each channel. The registers for unit 0 and unit 1 have the same functions except bit 7 (TTGE bit for unit 0 and reserved bit for unit 1) in TIER. This section describes unit 0 registers. * Unit 0 Channel 0: Timer control register_0 (TCR_0) Timer mode register_0 (TMDR_0) Timer I/O control register H_0 (TIORH_0) Timer I/O control register L_0 (TIORL_0) Timer interrupt enable register_0 (TIER_0) Timer status register_0 (TSR_0) Timer counter_0 (TCNT_0) Timer general register A_0 (TGRA_0) Timer general register B_0 (TGRB_0) Timer general register C_0 (TGRC_0) Timer general register D_0 (TGRD_0) Channel 1: Timer control register_1 (TCR_1) Timer mode register_1 (TMDR_1) Timer I/O control register _1 (TIOR_1) Timer interrupt enable register_1 (TIER_1) Timer status register_1 (TSR_1) Timer counter_1 (TCNT_1) Timer general register A_1 (TGRA_1) Timer general register B_1 (TGRB_1) Rev. 2.00 Mar. 15, 2006 Page 300 of 754 REJ09B0199-0200 Section 10 16-Bit Timer Pulse Unit (TPU) Channel 2: Timer control register_2 (TCR_2) Timer mode register_2 (TMDR_2) Timer I/O control register_2 (TIOR_2) Timer interrupt enable register_2 (TIER_2) Timer status register_2 (TSR_2) Timer counter_2 (TCNT_2) Timer general register A_2 (TGRA_2) Timer general register B_2 (TGRB_2) Channel 3: Timer control register_3 (TCR_3) Timer mode register_3 (TMDR_3) Timer I/O control register H_3 (TIORH_3) Timer I/O control register L_3 (TIORL_3) Timer interrupt enable register_3 (TIER_3) Timer status register_3 (TSR_3) Timer counter_3 (TCNT_3) Timer general register A_3 (TGRA_3) Timer general register B_3 (TGRB_3) Timer general register C_3 (TGRC_3) Timer general register D_3 (TGRD_3) Channel 4: Timer control register_4 (TCR_4) Timer mode register_4 (TMDR_4) Timer I/O control register _4 (TIOR_4) Timer interrupt enable register_4 (TIER_4) Timer status register_4 (TSR_4) Timer counter_4 (TCNT_4) Timer general register A_4 (TGRA_4) Timer general register B_4 (TGRB_4) Rev. 2.00 Mar. 15, 2006 Page 301 of 754 REJ09B0199-0200 Section 10 16-Bit Timer Pulse Unit (TPU) Channel 5: Timer control register_5 (TCR_5) Timer mode register_5 (TMDR_5) Timer I/O control register_5 (TIOR_5) Timer interrupt enable register_5 (TIER_5) Timer status register_5 (TSR_5) Timer counter_5 (TCNT_5) Timer general register A_5 (TGRA_5) Timer general register B_5 (TGRB_5) Common Registers Timer start register (TSTR) Timer synchronous register (TSYR) * Unit 1 Channel 6: Timer control register_6 (TCR_6) Timer mode register_6 (TMDR_6) Timer I/O control register H_6 (TIORH_6) Timer I/O control register L_6 (TIORL_6) Timer interrupt enable register_6 (TIER_6) Timer status register_6 (TSR_6) Timer counter_6 (TCNT_6) Timer general register A_6 (TGRA_6) Timer general register B_6 (TGRB_6) Timer general register C_6 (TGRC_6) Timer general register D_6 (TGRD_6) Rev. 2.00 Mar. 15, 2006 Page 302 of 754 REJ09B0199-0200 Section 10 16-Bit Timer Pulse Unit (TPU) Channel 7: Timer control register_7 (TCR_7) Timer mode register_7 (TMDR_7) Timer I/O control register _7 (TIOR_7) Timer interrupt enable register_7 (TIER_7) Timer status register_7 (TSR_7) Timer counter_7 (TCNT_7) Timer general register A_7 (TGRA_7) Timer general register B_7 (TGRB_7) Channel 8: Timer control register_8 (TCR_8) Timer mode register_8 (TMDR_8) Timer I/O control register_8 (TIOR_8) Timer interrupt enable register_8 (TIER_8) Timer status register_8 (TSR_8) Timer counter_8 (TCNT_8) Timer general register A_8 (TGRA_8) Timer general register B_8 (TGRB_8) Channel 9: Timer control register_9 (TCR_9) Timer mode register_9 (TMDR_9) Timer I/O control register H_9 (TIORH_9) Timer I/O control register L_9 (TIORL_9) Timer interrupt enable register_9 (TIER_9) Timer status register_9 (TSR_9) Timer counter_9 (TCNT_9) Timer general register A_9 (TGRA_9) Timer general register B_9 (TGRB_9) Timer general register C_9 (TGRC_9) Timer general register D_9 (TGRD_9) Rev. 2.00 Mar. 15, 2006 Page 303 of 754 REJ09B0199-0200 Section 10 16-Bit Timer Pulse Unit (TPU) Channel 10: Timer control register_10 (TCR_10) Timer mode register_10 (TMDR_10) Timer I/O control register _10 (TIOR_10) Timer interrupt enable register_10 (TIER_10) Timer status register_10 (TSR_10) Timer counter_10 (TCNT_10) Timer general register A_10 (TGRA_10) Timer general register B_10 (TGRB_10) Channel 11: Timer control register_11 (TCR_11) Timer mode register_11 (TMDR_11) Timer I/O control register_11 (TIOR_11) Timer interrupt enable register_11 (TIER_11) Timer status register_11 (TSR_11) Timer counter_11 (TCNT_11) Timer general register A_11 (TGRA_11) Timer general register B_11 (TGRB_11) Common Registers Timer start register (TSTRB) Timer synchronous register (TSYRB) Rev. 2.00 Mar. 15, 2006 Page 304 of 754 REJ09B0199-0200 Section 10 16-Bit Timer Pulse Unit (TPU) 10.3.1 Timer Control Register (TCR) TCR controls the TCNT operation for each channel. The TPU has a total of six TCR registers, one for each channel. TCR register settings should be made only while TCNT operation is stopped. Bit Bit Name Initial Value R/W 7 CCLR2 0 R/W 6 CCLR1 0 R/W 5 CCLR0 0 R/W 4 CKEG1 0 R/W 3 CKEG0 0 R/W 2 TPSC2 0 R/W 1 TPSC1 0 R/W 0 TPSC0 0 R/W Bit 7 6 5 4 3 Bit Name CCLR2 CCLR1 CCLR0 CKEG1 CKEG0 Initial Value 0 0 0 0 0 R/W R/W R/W R/W R/W R/W Description Counter Clear 2 to 0 These bits select the TCNT counter clearing source. See tables 10.5 and 10.6 for details. Clock Edge 1 and 0 These bits select the input clock edge. For details, see table 10.7. When the input clock is counted using both edges, the input clock period is halved (e.g. P/4 both edges = P/2 rising edge). If phase counting mode is used on channels 1, 2, 4, and 5, this setting is ignored and the phase counting mode setting has priority. Internal clock edge selection is valid when the input clock is P/4 or slower. This setting is ignored if the input clock is P/1, or when overflow/underflow of another channel is selected. Timer Prescaler 2 to 0 These bits select the TCNT counter clock. The clock source can be selected independently for each channel. See tables 10.8 to 10.13 for details. To select the external clock as the clock source, the DDR bit and ICR bit for the corresponding pin should be set to 0 and 1, respectively. For details, see section 9, I/O Ports. 2 1 0 TPSC2 TPSC1 TPSC0 0 0 0 R/W R/W R/W Rev. 2.00 Mar. 15, 2006 Page 305 of 754 REJ09B0199-0200 Section 10 16-Bit Timer Pulse Unit (TPU) Table 10.5 CCLR2 to CCLR0 (Channels 0 and 3) Channel 0, 3 Bit 7 CCLR2 0 0 0 0 Bit 6 CCLR1 0 0 1 1 Bit 5 CCLR0 0 1 0 1 Description TCNT clearing disabled TCNT cleared by TGRA compare match/input capture TCNT cleared by TGRB compare match/input capture TCNT cleared by counter clearing for another channel performing synchronous clearing/ 1 synchronous operation* TCNT clearing disabled TCNT cleared by TGRC compare match/input 2 capture* TCNT cleared by TGRD compare match/input capture*2 TCNT cleared by counter clearing for another channel performing synchronous clearing/ 1 synchronous operation* 1 1 1 1 0 0 1 1 0 1 0 1 Notes: 1. Synchronous operation is selected by setting the SYNC bit in TSYR to 1. 2. When TGRC or TGRD is used as a buffer register, TCNT is not cleared because the buffer register setting has priority, and compare match/input capture does not occur. Table 10.6 CCLR2 to CCLR0 (Channels 1, 2, 4, and 5) Channel 1, 2, 4, 5 Bit 7*2 Reserved 0 0 0 0 Bit 6 CCLR1 0 0 1 1 Bit 5 CCLR0 0 1 0 1 Description TCNT clearing disabled TCNT cleared by TGRA compare match/input capture TCNT cleared by TGRB compare match/input capture TCNT cleared by counter clearing for another channel performing synchronous clearing/ 1 synchronous operation* Notes: 1. Synchronous operation is selected by setting the SYNC bit in TSYR to 1. 2. Bit 7 is reserved in channels 1, 2, 4, and 5. It is a read-only bit and cannot be modified. Rev. 2.00 Mar. 15, 2006 Page 306 of 754 REJ09B0199-0200 Section 10 16-Bit Timer Pulse Unit (TPU) Table 10.7 Input Clock Edge Selection Clock Edge Selection CKEG1 0 0 1 [Legend] X: Don't care CKEG0 0 1 X Internal Clock Counted at falling edge Counted at rising edge Counted at both edges Input Clock External Clock Counted at rising edge Counted at falling edge Counted at both edges Table 10.8 TPSC2 to TPSC0 (Channel 0) Channel 0 Bit 2 TPSC2 0 0 0 0 1 1 1 1 Bit 1 TPSC1 0 0 1 1 0 0 1 1 Bit 0 TPSC0 0 1 0 1 0 1 0 1 Description Internal clock: counts on P/1 Internal clock: counts on P/4 Internal clock: counts on P/16 Internal clock: counts on P/64 External clock: counts on TCLKA pin input External clock: counts on TCLKB pin input External clock: counts on TCLKC pin input External clock: counts on TCLKD pin input Table 10.9 TPSC2 to TPSC0 (Channel 1) Channel 1 Bit 2 TPSC2 0 0 0 0 1 1 1 1 Bit 1 TPSC1 0 0 1 1 0 0 1 1 Bit 0 TPSC0 0 1 0 1 0 1 0 1 Description Internal clock: counts on P/1 Internal clock: counts on P/4 Internal clock: counts on P/16 Internal clock: counts on P/64 External clock: counts on TCLKA pin input External clock: counts on TCLKB pin input Internal clock: counts on P/256 Counts on TCNT2 overflow/underflow Note: This setting is ignored when channel 1 is in phase counting mode. Rev. 2.00 Mar. 15, 2006 Page 307 of 754 REJ09B0199-0200 Section 10 16-Bit Timer Pulse Unit (TPU) Table 10.10 TPSC2 to TPSC0 (Channel 2) Channel 2 Bit 2 TPSC2 0 0 0 0 1 1 1 1 Bit 1 TPSC1 0 0 1 1 0 0 1 1 Bit 0 TPSC0 0 1 0 1 0 1 0 1 Description Internal clock: counts on P/1 Internal clock: counts on P/4 Internal clock: counts on P/16 Internal clock: counts on P/64 External clock: counts on TCLKA pin input External clock: counts on TCLKB pin input External clock: counts on TCLKC pin input Internal clock: counts on P/1024 Note: This setting is ignored when channel 2 is in phase counting mode. Table 10.11 TPSC2 to TPSC0 (Channel 3) Channel 3 Bit 2 TPSC2 0 0 0 0 1 1 1 1 Bit 1 TPSC1 0 0 1 1 0 0 1 1 Bit 0 TPSC0 0 1 0 1 0 1 0 1 Description Internal clock: counts on P/1 Internal clock: counts on P/4 Internal clock: counts on P/16 Internal clock: counts on P/64 External clock: counts on TCLKA pin input Internal clock: counts on P/1024 Internal clock: counts on P/256 Internal clock: counts on P/4096 Rev. 2.00 Mar. 15, 2006 Page 308 of 754 REJ09B0199-0200 Section 10 16-Bit Timer Pulse Unit (TPU) Table 10.12 TPSC2 to TPSC0 (Channel 4) Channel 4 Bit 2 TPSC2 0 0 0 0 1 1 1 1 Bit 1 TPSC1 0 0 1 1 0 0 1 1 Bit 0 TPSC0 0 1 0 1 0 1 0 1 Description Internal clock: counts on P/1 Internal clock: counts on P/4 Internal clock: counts on P/16 Internal clock: counts on P/64 External clock: counts on TCLKA pin input External clock: counts on TCLKC pin input Internal clock: counts on P/1024 Counts on TCNT5 overflow/underflow Note: This setting is ignored when channel 4 is in phase counting mode. Table 10.13 TPSC2 to TPSC0 (Channel 5) Channel 5 Bit 2 TPSC2 0 0 0 0 1 1 1 1 Bit 1 TPSC1 0 0 1 1 0 0 1 1 Bit 0 TPSC0 0 1 0 1 0 1 0 1 Description Internal clock: counts on P/1 Internal clock: counts on P/4 Internal clock: counts on P/16 Internal clock: counts on P/64 External clock: counts on TCLKA pin input External clock: counts on TCLKC pin input Internal clock: counts on P/256 External clock: counts on TCLKD pin input Note: This setting is ignored when channel 5 is in phase counting mode. Rev. 2.00 Mar. 15, 2006 Page 309 of 754 REJ09B0199-0200 Section 10 16-Bit Timer Pulse Unit (TPU) 10.3.2 Timer Mode Register (TMDR) TMDR sets the operating mode for each channel. The TPU has six TMDR registers, one for each channel. TMDR register settings should be made only while TCNT operation is stopped. Bit Bit Name Initial Value R/W 7 -- 1 R 6 -- 1 R 5 BFB 0 R/W 4 BFA 0 R/W 3 MD3 0 R/W 2 MD2 0 R/W 1 MD1 0 R/W 0 MD0 0 R/W Bit 7, 6 5 Bit Name Initial Value All 1 0 R/W R R/W Description Reserved These are read-only bits and cannot be modified. Buffer Operation B Specifies whether TGRB is to normally operate, or TGRB and TGRD are to be used together for buffer operation. When TGRD is used as a buffer register, TGRD input capture/output compare is not generated. In channels 1, 2, 4, and 5, which have no TGRD, bit 5 is reserved. It is a read-only bit and cannot be modified. 0: TGRB operates normally 1: TGRB and TGRD used together for buffer operation BFB 4 BFA 0 R/W Buffer Operation A Specifies whether TGRA is to normally operate, or TGRA and TGRC are to be used together for buffer operation. When TGRC is used as a buffer register, TGRC input capture/output compare is not generated. In channels 1, 2, 4, and 5, which have no TGRC, bit 4 is reserved. It is a read-only bit and cannot be modified. 0: TGRA operates normally 1: TGRA and TGRC used together for buffer operation 3 2 1 0 MD3 MD2 MD1 MD0 0 0 0 0 R/W R/W R/W R/W Modes 3 to 0 Set the timer operating mode. MD3 is a reserved bit. The write value should always be 0. See table 10.14 for details. Rev. 2.00 Mar. 15, 2006 Page 310 of 754 REJ09B0199-0200 Section 10 16-Bit Timer Pulse Unit (TPU) Table 10.14 MD3 to MD0 Bit 3 1 MD3* 0 0 0 0 0 0 0 0 1 Bit 2 MD2*2 0 0 0 0 1 1 1 1 X Bit 1 MD1 0 0 1 1 0 0 1 1 X Bit 0 MD0 0 1 0 1 0 1 0 1 X Description Normal operation Reserved PWM mode 1 PWM mode 2 Phase counting mode 1 Phase counting mode 2 Phase counting mode 3 Phase counting mode 4 [Legend] X: Don't care Notes: 1. MD3 is a reserved bit. The write value should always be 0. 2. Phase counting mode cannot be set for channels 0 and 3. In this case, the write value should always be 0. 10.3.3 Timer I/O Control Register (TIOR) TIOR controls TGR. The TPU has eight TIOR registers, two each for channels 0 and 3, and one each for channels 1, 2, 4, and 5. Care is required since TIOR is affected by the TMDR setting. The initial output specified by TIOR is valid when the counter is stopped (the CST bit in TSTR is cleared to 0). Note also that, in PWM mode 2, the output at the point at which the counter is cleared to 0 is specified. When TGRC or TGRD is designated for buffer operation, this setting is invalid and the register operates as a buffer register. To designate the input capture pin in TIOR, the DDR bit and ICR bit for the corresponding pin should be set to 0 and 1, respectively. For details, see section 9, I/O Ports. Rev. 2.00 Mar. 15, 2006 Page 311 of 754 REJ09B0199-0200 Section 10 16-Bit Timer Pulse Unit (TPU) * TIORH_0, TIOR_1, TIOR_2, TIORH_3, TIOR_4, TIOR_5 Bit Bit Name Initial Value R/W 7 IOB3 0 R/W 6 IOB2 0 R/W 5 IOB1 0 R/W 4 IOB0 0 R/W 3 IOA3 0 R/W 2 IOA2 0 R/W 1 IOA1 0 R/W 0 IOA0 0 R/W * TIORL_0, TORL_3 Bit Bit Name Initial Value R/W 7 IOD3 0 R/W 6 IOD2 0 R/W 5 IOD1 0 R/W 4 IOD0 0 R/W 3 IOC3 0 R/W 2 IOC2 0 R/W 1 IOC1 0 R/W 0 IOC0 0 R/W * TIORH_0, TIOR_1, TIOR_2, TIORH_3, TIOR_4, TIOR_5 Bit 7 6 5 4 3 2 1 0 Bit Name IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0 Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description I/O Control B3 to B0 Specify the function of TGRB. For details, see tables 10.15, 10.17, 10.18, 10.19, 10.21, and 10.22. I/O Control A3 to A0 Specify the function of TGRA. For details, see tables 10.23, 10.25, 10.26, 10.27, 10.29, and 10.30. * TIORL_0, TIORL_3: Bit 7 6 5 4 3 2 1 0 Bit Name IOD3 IOD2 IOD1 IOD0 IOC3 IOC2 IOC1 IOC0 Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W I/O Control C3 to C0 Specify the function of TGRC. For details, see tables 10.24, and 10.28. Description I/O Control D3 to D0 Specify the function of TGRD. For details, see tables 10.16, and 10.20. Rev. 2.00 Mar. 15, 2006 Page 312 of 754 REJ09B0199-0200 Section 10 16-Bit Timer Pulse Unit (TPU) Table 10.15 TIORH_0 Description Bit 7 IOB3 0 0 0 0 0 0 0 0 1 1 1 1 Bit 6 IOB2 0 0 0 0 1 1 1 1 0 0 0 1 Bit 5 IOB1 0 0 1 1 0 0 1 1 0 0 1 x Bit 4 IOB0 0 1 0 1 0 1 0 1 0 1 x x Input capture register TGRB_0 Function Output compare register TIOCB0 Pin Function Output disabled Initial output is 0 output 0 output at compare match Initial output is 0 output 1 output at compare match Initial output is 0 output Toggle output at compare match Output disabled Initial output is 1 output 0 output at compare match Initial output is 1 output 1 output at compare match Initial output is 1 output Toggle output at compare match Capture input source is TIOCB0 pin Input capture at rising edge Capture input source is TIOCB0 pin Input capture at falling edge Capture input source is TIOCB0 pin Input capture at both edges Capture input source is channel 1/count clock Input capture at TCNT_1 count-up/count-down* [Legend] X: Don't care Note: When bits TPSC2 to TPSC0 in TCR_1 are set to B'000 and P/1 is used as the TCNT_1 count clock, this setting is invalid and input capture is not generated. Rev. 2.00 Mar. 15, 2006 Page 313 of 754 REJ09B0199-0200 Section 10 16-Bit Timer Pulse Unit (TPU) Table 10.16 TIORL_0 Description Bit 7 IOD3 0 0 0 0 0 0 0 0 1 1 1 1 Bit 6 IOD2 0 0 0 0 1 1 1 1 0 0 0 1 Bit 5 IOD1 0 0 1 1 0 0 1 1 0 0 1 X Bit 4 IOD0 0 1 0 1 0 1 0 1 0 1 X X Input capture register*2 TGRD_0 Function Output compare register*2 TIOCD0 Pin Function Output disabled Initial output is 0 output 0 output at compare match Initial output is 0 output 1 output at compare match Initial output is 0 output Toggle output at compare match Output disabled Initial output is 1 output 0 output at compare match Initial output is 1 output 1 output at compare match Initial output is 1 output Toggle output at compare match Capture input source is TIOCD0 pin Input capture at rising edge Capture input source is TIOCD0 pin Input capture at falling edge Capture input source is TIOCD0 pin Input capture at both edges Capture input source is channel 1/count clock Input capture at TCNT_1 count-up/count-down* 1 [Legend] X: Don't care Notes: 1. When bits TPSC2 to TPSC0 in TCR_1 are set to B'000 and P/1 is used as the TCNT_1 count clock, this setting is invalid and input capture is not generated. 2. When the BFB bit in TMDR_0 is set to 1 and TGRD_0 is used as a buffer register, this setting is invalid and input capture/output compare is not generated. Rev. 2.00 Mar. 15, 2006 Page 314 of 754 REJ09B0199-0200 Section 10 16-Bit Timer Pulse Unit (TPU) Table 10.17 TIOR_1 Description Bit 7 IOB3 0 0 0 0 0 0 0 0 1 1 1 1 Bit 6 IOB2 0 0 0 0 1 1 1 1 0 0 0 1 Bit 5 IOB1 0 0 1 1 0 0 1 1 0 0 1 X Bit 4 IOB0 0 1 0 1 0 1 0 1 0 1 X X Input capture register TGRB_1 Function Output compare register TIOCB1 Pin Function Output disabled Initial output is 0 output 0 output at compare match Initial output is 0 output 1 output at compare match Initial output is 0 output Toggle output at compare match Output disabled Initial output is 1 output 0 output at compare match Initial output is 1 output 1 output at compare match Initial output is 1 output Toggle output at compare match Capture input source is TIOCB1 pin Input capture at rising edge Capture input source is TIOCB1 pin Input capture at falling edge Capture input source is TIOCB1 pin Input capture at both edges TGRC_0 compare match/input capture Input capture at generation of TGRC_0 compare match/input capture [Legend] X: Don't care Rev. 2.00 Mar. 15, 2006 Page 315 of 754 REJ09B0199-0200 Section 10 16-Bit Timer Pulse Unit (TPU) Table 10.18 TIOR_2 Description Bit 7 IOB3 0 0 0 0 0 0 0 0 1 1 1 Bit 6 IOB2 0 0 0 0 1 1 1 1 X X X Bit 5 IOB1 0 0 1 1 0 0 1 1 0 0 1 Bit 4 IOB0 0 1 0 1 0 1 0 1 0 1 X Input capture register TGRB_2 Function Output compare register TIOCB2 Pin Function Output disabled Initial output is 0 output 0 output at compare match Initial output is 0 output 1 output at compare match Initial output is 0 output Toggle output at compare match Output disabled Initial output is 1 output 0 output at compare match Initial output is 1 output 1 output at compare match Initial output is 1 output Toggle output at compare match Capture input source is TIOCB2 pin Input capture at rising edge Capture input source is TIOCB2 pin Input capture at falling edge Capture input source is TIOCB2 pin Input capture at both edges [Legend] X: Don't care Rev. 2.00 Mar. 15, 2006 Page 316 of 754 REJ09B0199-0200 Section 10 16-Bit Timer Pulse Unit (TPU) Table 10.19 TIORH_3 Description Bit 7 IOB3 0 0 0 0 0 0 0 0 1 1 1 1 Bit 6 IOB2 0 0 0 0 1 1 1 1 0 0 0 1 Bit 5 IOB1 0 0 1 1 0 0 1 1 0 0 1 x Bit 4 IOB0 0 1 0 1 0 1 0 1 0 1 x x Input capture register TGRB_3 Function Output compare register TIOCB3 Pin Function Output disabled Initial output is 0 output 0 output at compare match Initial output is 0 output 1 output at compare match Initial output is 0 output Toggle output at compare match Output disabled Initial output is 1 output 0 output at compare match Initial output is 1 output 1 output at compare match Initial output is 1 output Toggle output at compare match Capture input source is TIOCB3 pin Input capture at rising edge Capture input source is TIOCB3 pin Input capture at falling edge Capture input source is TIOCB3 pin Input capture at both edges Capture input source is channel 4/count clock Input capture at TCNT_4 count-up/count-down* [Legend] X: Don't care Note: When bits TPSC2 to TPSC0 in TCR_4 are set to B'000 and P/1 is used as the TCNT_4 count clock, this setting is invalid and input capture is not generated. Rev. 2.00 Mar. 15, 2006 Page 317 of 754 REJ09B0199-0200 Section 10 16-Bit Timer Pulse Unit (TPU) Table 10.20 TIORL_3 Description Bit 7 IOD3 0 0 0 0 0 0 0 0 1 1 1 1 Bit 6 IOD2 0 0 0 0 1 1 1 1 0 0 0 1 Bit 5 IOD1 0 0 1 1 0 0 1 1 0 0 1 x Bit 4 IOD0 0 1 0 1 0 1 0 1 0 1 x x Input capture register*2 TGRD_3 Function Output compare register*2 TIOCD3 Pin Function Output disabled Initial output is 0 output 0 output at compare match Initial output is 0 output 1 output at compare match Initial output is 0 output Toggle output at compare match Output disabled Initial output is 1 output 0 output at compare match Initial output is 1 output 1 output at compare match Initial output is 1 output Toggle output at compare match Capture input source is TIOCD3 pin Input capture at rising edge Capture input source is TIOCD3 pin Input capture at falling edge Capture input source is TIOCD3 pin Input capture at both edges Capture input source is channel 4/count clock Input capture at TCNT_4 count-up/count-down* 1 [Legend] X: Don't care Notes: 1. When bits TPSC2 to TPSC0 in TCR_4 are set to B'000 and P/1 is used as the TCNT_4 count clock, this setting is invalid and input capture is not generated. 2. When the BFB bit in TMDR_3 is set to 1 and TGRD_3 is used as a buffer register, this setting is invalid and input capture/output compare is not generated. Rev. 2.00 Mar. 15, 2006 Page 318 of 754 REJ09B0199-0200 Section 10 16-Bit Timer Pulse Unit (TPU) Table 10.21 TIOR_4 Description Bit 7 IOB3 0 0 0 0 0 0 0 0 1 1 1 1 Bit 6 IOB2 0 0 0 0 1 1 1 1 0 0 0 1 Bit 5 IOB1 0 0 1 1 0 0 1 1 0 0 1 x Bit 4 IOB0 0 1 0 1 0 1 0 1 0 1 x x Input capture register TGRB_4 Function Output compare register TIOCB4 Pin Function Output disabled Initial output is 0 output 0 output at compare match Initial output is 0 output 1 output at compare match Initial output is 0 output Toggle output at compare match Output disabled Initial output is 1 output 0 output at compare match Initial output is 1 output 1 output at compare match Initial output is 1 output Toggle output at compare match Capture input source is TIOCB4 pin Input capture at rising edge Capture input source is TIOCB4 pin Input capture at falling edge Capture input source is TIOCB4 pin Input capture at both edges Capture input source is TGRC_3 compare match/input capture Input capture at generation of TGRC_3 compare match/input capture [Legend] X: Don't care Rev. 2.00 Mar. 15, 2006 Page 319 of 754 REJ09B0199-0200 Section 10 16-Bit Timer Pulse Unit (TPU) Table 10.22 TIOR_5 Description Bit 7 IOB3 0 0 0 0 0 0 0 0 1 1 1 Bit 6 IOB2 0 0 0 0 1 1 1 1 x x x Bit 5 IOB1 0 0 1 1 0 0 1 1 0 0 1 Bit 4 IOB0 0 1 0 1 0 1 0 1 0 1 x Input capture register TGRB_5 Function Output compare register TIOCB5 Pin Function Output disabled Initial output is 0 output 0 output at compare match Initial output is 0 output 1 output at compare match Initial output is 0 output Toggle output at compare match Output disabled Initial output is 1 output 0 output at compare match Initial output is 1 output 1 output at compare match Initial output is 1 output Toggle output at compare match Capture input source is TIOCB5 pin Input capture at rising edge Capture input source is TIOCB5 pin Input capture at falling edge Capture input source is TIOCB5 pin Input capture at both edges [Legend] X: Don't care Table 10.23 TIORH_0 Description Bit 3 IOA3 0 0 Bit 2 IOA2 0 0 Bit 1 IOA1 0 0 Bit 0 IOA0 0 1 TGRA_0 Function Output compare register TIOCA0 Pin Function Output disabled Initial output is 0 output 0 output at compare match Rev. 2.00 Mar. 15, 2006 Page 320 of 754 REJ09B0199-0200 Section 10 16-Bit Timer Pulse Unit (TPU) Description Bit 3 IOA3 0 0 0 0 0 0 1 1 1 1 Bit 2 IOA2 0 0 1 1 1 1 0 0 0 1 Bit 1 IOA1 1 1 0 0 1 1 0 0 1 X Bit 0 IOA0 0 1 0 1 0 1 1 0 X X Input capture register TGRA_0 Function TIOCA0 Pin Function Initial output is 0 output 1 output at compare match Initial output is 0 output Toggle output at compare match Output disabled Initial output is 1 output 0 output at compare match Initial output is 1 output 1 output at compare match Initial output is 1 output Toggle output at compare match Capture input source is TIOCA0 pin Input capture at rising edge Capture input source is TIOCA0 pin Input capture at rising edge Capture input source is TIOCA0 pin Input capture at both edges Capture input source is channel 1/count clock Input capture* at TCNT_1 count-up/count-down [Legend] X: Don't care Note: * When bits TPSC2 to TPSC0 in TCR_1 are set to B'000 and P/1 is used as the TCNT_1 counter clock, this setting is ignored and an input capture interrupt is not generated. Rev. 2.00 Mar. 15, 2006 Page 321 of 754 REJ09B0199-0200 Section 10 16-Bit Timer Pulse Unit (TPU) Table 10.24 TIORL_0 Description Bit 3 IOC3 0 0 0 0 0 0 0 0 1 1 1 1 Bit 2 IOC2 0 0 0 0 1 1 1 1 0 0 0 1 Bit 1 IOC1 0 0 1 1 0 0 1 1 0 0 1 X Bit 0 IOC0 0 1 0 1 0 1 0 1 0 1 X X Input capture register*2 TGRC_0 Function Output compare register*2 TIOCC0 Pin Function Output disabled Initial output is 0 output 0 output at compare match Initial output is 0 output 1 output at compare match Initial output is 0 output Toggle output at compare match Output disabled Initial output is 1 output 0 output at compare match Initial output is 1 output 1 output at compare match Initial output is 1 output Toggle output at compare match Capture input source is TIOCC0 pin Input capture at rising edge Capture input source is TIOCC0 pin Input capture at falling edge Capture input source is TIOCC0 pin Input capture at both edges Capture input source is channel 1/count clock 1 Input capture* at TCNT_1 count-up/count-down [Legend] X: Don't care Notes: 1. When bits TPSC2 to TPSC0 in TCR_1 are set to B'000 and P/1 is used as the TCNT_1 counter clock, this setting is ignored and an input capture interrupt is not generated. 2. When the BFA bit in TMDR_0 is set to 1 and TGRC_0 is used as a buffer register, this setting is invalid and input capture/output compare is not generated. Rev. 2.00 Mar. 15, 2006 Page 322 of 754 REJ09B0199-0200 Section 10 16-Bit Timer Pulse Unit (TPU) Table 10.25 TIOR_1 Description Bit 3 IOA3 0 0 0 0 0 0 0 0 1 1 1 1 Bit 2 IOA2 0 0 0 0 1 1 1 1 0 0 0 1 Bit 1 IOA1 0 0 1 1 0 0 1 1 0 0 1 X Bit 0 IOA0 0 1 0 1 0 1 0 1 0 1 X X Input capture register TGRA_1 Function Output compare register TIOCA1 Pin Function Output disabled Initial output is 0 output 0 output at compare match Initial output is 0 output 1 output at compare match Initial output is 0 output Toggle output at compare match Output disabled Initial output is 1 output 0 output at compare match Initial output is 1 output 1 output at compare match Initial output is 1 output Toggle output at compare match Capture input source is TIOCA1 pin Input capture at rising edge Capture input source is TIOCA1 pin Input capture at falling edge Capture input source is TIOCA1 pin Input capture at both edges Capture input source is TGRA_0 compare match/input capture Input capture at generation of channel 0/TGRA_0 compare match/input capture [Legend] X: Don't care Rev. 2.00 Mar. 15, 2006 Page 323 of 754 REJ09B0199-0200 Section 10 16-Bit Timer Pulse Unit (TPU) Table 10.26 TIOR_2 Description Bit 3 IOA3 0 0 0 0 0 0 0 0 1 1 1 Bit 2 IOA2 0 0 0 0 1 1 1 1 X X X Bit 1 IOA1 0 0 1 1 0 0 1 1 0 0 1 Bit 0 IOA0 0 1 0 1 0 1 0 1 0 1 X Input capture register TGRA_2 Function Output compare register TIOCA2 Pin Function Output disabled Initial output is 0 output 0 output at compare match Initial output is 0 output 1 output at compare match Initial output is 0 output Toggle output at compare match Output disabled Initial output is 1 output 0 output at compare match Initial output is 1 output 1 output at compare match Initial output is 1 output Toggle output at compare match Capture input source is TIOCA2 pin Input capture at rising edge Capture input source is TIOCA2 pin Input capture at falling edge Capture input source is TIOCA2 pin Input capture at both edges [Legend] X: Don't care Rev. 2.00 Mar. 15, 2006 Page 324 of 754 REJ09B0199-0200 Section 10 16-Bit Timer Pulse Unit (TPU) Table 10.27 TIORH_3 Description Bit 3 IOA3 0 0 0 0 0 0 0 0 1 1 1 1 Bit 2 IOA2 0 0 0 0 1 1 1 1 0 0 0 1 Bit 1 IOA1 0 0 1 1 0 0 1 1 0 0 1 X Bit 0 IOA0 0 1 0 1 0 1 0 1 0 1 X X Input capture register TGRA_3 Function Output compare register TIOCA3 Pin Function Output disabled Initial output is 0 output 0 output at compare match Initial output is 0 output 1 output at compare match Initial output is 0 output Toggle output at compare match Output disabled Initial output is 1 output 0 output at compare match Initial output is 1 output 1 output at compare match Initial output is 1 output Toggle output at compare match Capture input source is TIOCA3 pin Input capture at rising edge Capture input source is TIOCA3 pin Input capture at falling edge Capture input source is TIOCA3 pin Input capture at both edges Capture input source is channel 4/count clock Input capture* at TCNT_4 count-up/count-down [Legend] X: Don't care Note: * When bits TPSC2 to TPSC0 in TCR_4 are set to B'000 and P/1 is used as the TCNT_4 counter clock, this setting is ignored and an input capture interrupt is not generated. Rev. 2.00 Mar. 15, 2006 Page 325 of 754 REJ09B0199-0200 Section 10 16-Bit Timer Pulse Unit (TPU) Table 10.28 TIORL_3 Description Bit 3 IOC3 0 0 0 0 0 0 0 0 1 1 1 1 Bit 2 IOC2 0 0 0 0 1 1 1 1 0 0 0 1 Bit 1 IOC1 0 0 1 1 0 0 1 1 0 0 1 X Bit 0 IOC0 0 1 0 1 0 1 0 1 0 1 X X Input capture register*2 TGRC_3 Function Output compare register*2 TIOCC3 Pin Function Output disabled Initial output is 0 output 0 output at compare match Initial output is 0 output 1 output at compare match Initial output is 0 output Toggle output at compare match Output disabled Initial output is 1 output 0 output at compare match Initial output is 1 output 1 output at compare match Initial output is 1 output Toggle output at compare match Capture input source is TIOCC3 pin Input capture at rising edge Capture input source is TIOCC3 pin Input capture at falling edge Capture input source is TIOCC3 pin Input capture at both edges Capture input source is channel 4/count clock 1 Input capture* at TCNT_4 count-up/count-down [Legend] X: Don't care Notes: 1. When bits TPSC2 to TPSC0 in TCR_4 are set to B'000 and P/1 is used as the TCNT_4 counter clock, this setting is ignored and an input capture interrupt is not generated. 2. When the BFA bit in TMDR_3 is set to 1 and TGRC_3 is used as a buffer register, this setting is invalid and input capture/output compare is not generated. Rev. 2.00 Mar. 15, 2006 Page 326 of 754 REJ09B0199-0200 Section 10 16-Bit Timer Pulse Unit (TPU) Table 10.29 TIOR_4 Description Bit 3 IOA3 0 0 0 0 0 0 0 0 1 1 1 1 Bit 2 IOA2 0 0 0 0 1 1 1 1 0 0 0 1 Bit 1 IOA1 0 0 1 1 0 0 1 1 0 0 1 X Bit 0 IOA0 0 1 0 1 0 1 0 1 0 1 X X Input capture register TGRA_4 Function Output compare register TIOCA4 Pin Function Output disabled Initial output is 0 output 0 output at compare match Initial output is 0 output 1 output at compare match Initial output is 0 output Toggle output at compare match Output disabled Initial output is 1 output 0 output at compare match Initial output is 1 output 1 output at compare match Initial output is 1 output Toggle output at compare match Capture input source is TIOCA4 pin Input capture at rising edge Capture input source is TIOCA4 pin Input capture at falling edge Capture input source is TIOCA4 pin Input capture at both edges Capture input source is TGRA_3 compare match/input capture Input capture at generation of TGRA_3 compare match/input capture [Legend] X: Don't care Rev. 2.00 Mar. 15, 2006 Page 327 of 754 REJ09B0199-0200 Section 10 16-Bit Timer Pulse Unit (TPU) Table 10.30 TIOR_5 Description Bit 3 IOA3 0 0 0 0 0 0 0 0 1 1 1 Bit 2 IOA2 0 0 0 0 1 1 1 1 X X X Bit 1 IOA1 0 0 1 1 0 0 1 1 0 0 1 Bit 0 IOA0 0 1 0 1 0 1 0 1 0 1 X Input capture register TGRA_5 Function Output compare register TIOCA5 Pin Function Output disabled Initial output is 0 output 0 output at compare match Initial output is 0 output 1 output at compare match Initial output is 0 output Toggle output at compare match Output disabled Initial output is 1 output 0 output at compare match Initial output is 1 output 1 output at compare match Initial output is 1 output Toggle output at compare match Input capture source is TIOCA5 pin Input capture at rising edge Input capture source is TIOCA5 pin Input capture at falling edge Input capture source is TIOCA5 pin Input capture at both edges [Legend] X: Don't care Rev. 2.00 Mar. 15, 2006 Page 328 of 754 REJ09B0199-0200 Section 10 16-Bit Timer Pulse Unit (TPU) 10.3.4 Timer Interrupt Enable Register (TIER) TIER controls enabling or disabling of interrupt requests for each channel. The TPU has six TIER registers, one for each channel. Bit Bit Name Initial Value R/W 7 TTGE* 0 R/W 6 -- 1 R 5 TCIEU 0 R/W 4 TCIEV 0 R/W 3 TGIED 0 R/W 2 TGIEC 0 R/W 1 TGIEB 0 R/W 0 TGIEA 0 R/W Note: * Bit 7 in TIER for unit 1 is a reserved bit and is always read as 0. The write value should always be 0. Bit 7 Bit Name TTGE* Initial value 0 R/W R/W Description A/D Conversion Start Request Enable Enables/disables generation of A/D conversion start requests by TGRA input capture/compare match. 0: A/D conversion start request generation disabled 1: A/D conversion start request generation enabled 6 5 TCIEU 1 0 R R/W Reserved This is a read-only bit and cannot be modified. Underflow Interrupt Enable Enables/disables interrupt requests (TCIU) by the TCFU flag when the TCFU flag in TSR is set to 1 in channels 1, 2, 4, and 5. In channels 0 and 3, bit 5 is reserved. It is a read-only bit and cannot be modified. 0: Interrupt requests (TCIU) by TCFU disabled 1: Interrupt requests (TCIU) by TCFU enabled 4 TCIEV 0 R/W Overflow Interrupt Enable Enables/disables interrupt requests (TCIV) by the TCFV flag when the TCFV flag in TSR is set to 1. 0: Interrupt requests (TCIV) by TCFV disabled 1: Interrupt requests (TCIV) by TCFV enabled Rev. 2.00 Mar. 15, 2006 Page 329 of 754 REJ09B0199-0200 Section 10 16-Bit Timer Pulse Unit (TPU) Bit 3 Bit Name TGIED Initial value 0 R/W R/W Description TGR Interrupt Enable D Enables/disables interrupt requests (TGID) by the TGFD bit when the TGFD bit in TSR is set to 1 in channels 0 and 3. In channels 1, 2, 4, and 5, bit 3 is reserved. It is a readonly bit and cannot be modified. 0: Interrupt requests (TGID) by TGFD bit disabled 1: Interrupt requests (TGID) by TGFD bit enabled 2 TGIEC 0 R/W TGR Interrupt Enable C Enables/disables interrupt requests (TGIC) by the TGFC bit when the TGFC bit in TSR is set to 1 in channels 0 and 3. In channels 1, 2, 4, and 5, bit 2 is reserved. It is a readonly bit and cannot be modified. 0: Interrupt requests (TGIC) by TGFC bit disabled 1: Interrupt requests (TGIC) by TGFC bit enabled 1 TGIEB 0 R/W TGR Interrupt Enable B Enables/disables interrupt requests (TGIB) by the TGFB bit when the TGFB bit in TSR is set to 1. 0: Interrupt requests (TGIB) by TGFB bit disabled 1: Interrupt requests (TGIB) by TGFB bit enabled 0 TGIEA 0 R/W TGR Interrupt Enable A Enables/disables interrupt requests (TGIA) by the TGFA bit when the TGFA bit in TSR is set to 1. 0: Interrupt requests (TGIA) by TGFA bit disabled 1: Interrupt requests (TGIA) by TGFA bit enabled Note: * Bit 7 in TIER for unit 1 is a reserved bit and is always read as 0. The write value should always be 0. Rev. 2.00 Mar. 15, 2006 Page 330 of 754 REJ09B0199-0200 Section 10 16-Bit Timer Pulse Unit (TPU) 10.3.5 Timer Status Register (TSR) TSR indicates the status of each channel. The TPU has six TSR registers, one for each channel. Bit Bit Name Initial Value R/W 7 TCFD 1 R 6 -- 1 R 5 TCFU 0 R/(W)* 4 TCFV 0 R/(W)* 3 TGFD 0 R/(W)* 2 TGFC 0 R/(W)* 1 TGFB 0 R/(W)* 0 TGFA 0 R/(W)* Note: * Only 0 can be written to bits 5 to 0, to clear flags. Bit 7 Bit Name TCFD Initial value 1 R/W R Description Count Direction Flag Status flag that shows the direction in which TCNT counts in channels 1, 2, 4, and 5. In channels 0 and 3, bit 7 is reserved. It is a read-only bit and cannot be modified. 0: TCNT counts down 1: TCNT counts up 6 5 TCFU 1 0 R Reserved This is a read-only bit and cannot be modified. R/(W)* Underflow Flag Status flag that indicates that a TCNT underflow has occurred when channels 1, 2, 4, and 5 are set to phase counting mode. In channels 0 and 3, bit 5 is reserved. It is a read-only bit and cannot be modified. [Setting condition] * When the TCNT value underflows (changes from H'0000 to H'FFFF) When a 0 is written to TCFU after reading TCFU = 1 (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) [Clearing condition] * Rev. 2.00 Mar. 15, 2006 Page 331 of 754 REJ09B0199-0200 Section 10 16-Bit Timer Pulse Unit (TPU) Bit 4 Bit Name TCFV Initial value 0 R/W Description Status flag that indicates that a TCNT overflow has occurred. [Setting condition] * When the TCNT value overflows (changes from H'FFFF to H'0000) When a 0 is written to TCFV after reading TCFV = 1 (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) R/(W)* Overflow Flag [Clearing condition] * 3 TGFD 0 R/(W)* Input Capture/Output Compare Flag D Status flag that indicates the occurrence of TGRD input capture or compare match in channels 0 and 3. In channels 1, 2, 4, and 5, bit 3 is reserved. It is a readonly bit and cannot be modified. [Setting conditions] * * When TCNT = TGRD while TGRD is functioning as output compare register When TCNT value is transferred to TGRD by input capture signal while TGRD is functioning as input capture register When DTC is activated by a TGID interrupt while the DISEL bit in MRB of DTC is 0 When 0 is written to TGFD after reading TGFD = 1 (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) [Clearing conditions] * * Rev. 2.00 Mar. 15, 2006 Page 332 of 754 REJ09B0199-0200 Section 10 16-Bit Timer Pulse Unit (TPU) Bit 2 Bit Name TGFC Initial value 0 R/W Description R/(W)* Input Capture/Output Compare Flag C Status flag that indicates the occurrence of TGRC input capture or compare match in channels 0 and 3. In channels 1, 2, 4, and 5, bit 2 is reserved. It is a readonly bit and cannot be modified. [Setting conditions] * * When TCNT = TGRC while TGRC is functioning as output compare register When TCNT value is transferred to TGRC by input capture signal while TGRC is functioning as input capture register When DTC is activated by a TGIC interrupt while the DISEL bit in MRB of DTC is 0 When 0 is written to TGFC after reading TGFC = 1 (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) [Clearing conditions] * * 1 TGFB 0 R/(W)* Input Capture/Output Compare Flag B Status flag that indicates the occurrence of TGRB input capture or compare match. [Setting conditions] * * When TCNT = TGRB while TGRB is functioning as output compare register When TCNT value is transferred to TGRB by input capture signal while TGRB is functioning as input capture register When DTC is activated by a TGIB interrupt while the DISEL bit in MRB of DTC is 0 When 0 is written to TGFB after reading TGFB = 1 (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) [Clearing conditions] * * Rev. 2.00 Mar. 15, 2006 Page 333 of 754 REJ09B0199-0200 Section 10 16-Bit Timer Pulse Unit (TPU) Bit 0 Bit Name TGFA Initial value 0 R/W Description R/(W)* Input Capture/Output Compare Flag A Status flag that indicates the occurrence of TGRA input capture or compare match. [Setting conditions] * * When TCNT = TGRA while TGRA is functioning as output compare register When TCNT value is transferred to TGRA by input capture signal while TGRA is functioning as input capture register When DTC is activated by a TGIA interrupt while the DISEL bit in MRB of DTC is 0 When DMAC is activated by a TGIA interrupt while the DTA bit in DMDR of DMAC is 1 When 0 is written to TGFA after reading TGFA = 1 (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) [Clearing conditions] * * * Note: * Only 0 can be written to clear the flag. Rev. 2.00 Mar. 15, 2006 Page 334 of 754 REJ09B0199-0200 Section 10 16-Bit Timer Pulse Unit (TPU) 10.3.6 Timer Counter (TCNT) TCNT is a 16-bit readable/writable counter. The TPU has six TCNT counters, one for each channel. TCNT is initialized to H'0000 by a reset or in hardware standby mode. TCNT cannot be accessed in 8-bit units. TCNT must always be accessed in 16-bit units. Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 15 14 13 12 11 10 9 8 10.3.7 Timer General Register (TGR) TGR is a 16-bit readable/writable register with a dual function as output compare and input capture registers. The TPU has 16 TGR registers, four each for channels 0 and 3 and two each for channels 1, 2, 4, and 5. TGRC and TGRD for channels 0 and 3 can also be designated for operation as buffer registers. The TGR registers cannot be accessed in 8-bit units; they must always be accessed in 16-bit units. TGR and buffer register combinations during buffer operations are TGRA-TGRC and TGRB-TGRD. Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W 3 1 R/W 2 1 R/W 1 1 R/W 0 15 14 13 12 11 10 9 8 Rev. 2.00 Mar. 15, 2006 Page 335 of 754 REJ09B0199-0200 Section 10 16-Bit Timer Pulse Unit (TPU) 10.3.8 Timer Start Register (TSTR) TSTR starts or stops operation for channels 0 to 5. When setting the operating mode in TMDR or setting the count clock in TCR, first stop the TCNT counter. Bit Bit Name Initial Value R/W 7 -- 0 R/W 6 -- 0 R/W 5 CST5 0 R/W 4 CST4 0 R/W 3 CST3 0 R/W 2 CST2 0 R/W 1 CST1 0 R/W 0 CST0 0 R/W Bit 7, 6 Bit Name Initial value All 0 R/W R/W Description Reserved These bits are always read as 0. The write value should always be 0. 5 4 3 2 1 0 CST5 CST4 CST3 CST2 CST1 CST0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W Counter Start 5 to 0 These bits select operation or stoppage for TCNT. If 0 is written to the CST bit during operation with the TIOC pin designated for output, the counter stops but the TIOC pin output compare output level is retained. If TIOR is written to when the CST bit is cleared to 0, the pin output level will be changed to the set initial output value. 0: TCNT_5 to TCNT_0 count operation is stopped 1: TCNT_5 to TCNT_0 performs count operation Rev. 2.00 Mar. 15, 2006 Page 336 of 754 REJ09B0199-0200 Section 10 16-Bit Timer Pulse Unit (TPU) 10.3.9 Timer Synchronous Register (TSYR) TSYR selects independent operation or synchronous operation for the TCNT counters of channels 0 to 5. A channel performs synchronous operation when the corresponding bit in TSYR is set to 1. Bit Bit Name Initial Value R/W 7 -- 0 R/W 6 -- 0 R/W 5 SYNC5 0 R/W 4 SYNC4 0 R/W 3 SYNC3 0 R/W 2 SYNC2 0 R/W 1 SYNC1 0 R/W 0 SYNC0 0 R/W Bit 7, 6 Bit Name Initial value All 0 R/W R/W Description Reserved These bits are always read as 0. The write value should always be 0. 5 4 3 2 1 0 SYNC5 SYNC4 SYNC3 SYNC2 SYNC1 SYNC0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W Timer Synchronization 5 to 0 These bits select whether operation is independent of or synchronized with other channels. When synchronous operation is selected, synchronous presetting of multiple channels, and synchronous clearing through counter clearing on another channel are possible. To set synchronous operation, the SYNC bits for at least two channels must be set to 1. To set synchronous clearing, in addition to the SYNC bit, the TCNT clearing source must also be set by means of bits CCLR2 to CCLR0 in TCR. 0: TCNT_5 to TCNT_0 operate independently (TCNT presetting/clearing is unrelated to other channels) 1: TCNT_5 to TCNT_0 perform synchronous operation (TCNT synchronous presetting/synchronous clearing is possible) Rev. 2.00 Mar. 15, 2006 Page 337 of 754 REJ09B0199-0200 Section 10 16-Bit Timer Pulse Unit (TPU) 10.4 10.4.1 Operation Basic Functions Each channel has a TCNT and TGR register. TCNT performs up-counting, and is also capable of free-running operation, periodic counting, and external event counting. Each TGR can be used as an input capture register or output compare register. (1) Counter Operation When one of bits CST0 to CST5 is set to 1 in TSTR, the TCNT counter for the corresponding channel starts counting. TCNT can operate as a free-running counter, periodic counter, and so on. (a) Example of count operation setting procedure Figure 10.3 shows an example of the count operation setting procedure. Operation selection Select counter clock [1] [1] Select the counter clock with bits TPSC2 to TPSC0 in TCR. At the same time, select the input clock edge with bits CKEG1 and CKEG0 in TCR. Free-running counter [2] For periodic counter operation, select the TGR to be used as the TCNT clearing source with bits CCLR2 to CCLR0 in TCR. [3] Designate the TGR selected in [2] as an output compare register by means of TIOR. [4] Set the periodic counter cycle in the TGR selected in [2]. Start count Periodic counter Select counter clearing source [2] Select output compare register [3] Set period [4] Start count [5] Figure 10.3 Example of Counter Operation Setting Procedure Rev. 2.00 Mar. 15, 2006 Page 338 of 754 REJ09B0199-0200 Section 10 16-Bit Timer Pulse Unit (TPU) (b) Free-running count operation and periodic count operation Immediately after a reset, the TPU's TCNT counters are all designated as free-running counters. When the relevant bit in TSTR is set to 1 the corresponding TCNT counter starts up-count operation as a free-running counter. When TCNT overflows (changes from H'FFFF to H'0000), the TCFV bit in TSR is set to 1. If the value of the corresponding TCIEV bit in TIER is 1 at this point, the TPU requests an interrupt. After overflow, TCNT starts counting up again from H'0000. Figure 10.4 illustrates free-running counter operation. TCNT value H'FFFF H'0000 CST bit TCFV Time Figure 10.4 Free-Running Counter Operation When compare match is selected as the TCNT clearing source, the TCNT counter for the relevant channel performs periodic count operation. The TGR register for setting the period is designated as an output compare register, and counter clearing by compare match is selected by means of bits CCLR2 to CCLR0 in TCR. After the settings have been made, TCNT starts count-up operation as a periodic counter when the corresponding bit in TSTR is set to 1. When the count value matches the value in TGR, the TGF bit in TSR is set to 1 and TCNT is cleared to H'0000. If the value of the corresponding TGIE bit in TIER is 1 at this point, the TPU requests an interrupt. After a compare match, TCNT starts counting up again from H'0000. Figure 10.5 illustrates periodic counter operation. Rev. 2.00 Mar. 15, 2006 Page 339 of 754 REJ09B0199-0200 Section 10 16-Bit Timer Pulse Unit (TPU) TCNT value TGR Counter cleared by TGR compare match H'0000 CST bit Time Flag cleared by software or DMAC activation TGF Figure 10.5 Periodic Counter Operation (2) Waveform Output by Compare Match The TPU can perform 0, 1, or toggle output from the corresponding output pin using a compare match. (a) Example of setting procedure for waveform output by compare match Figure 10.6 shows an example of the setting procedure for waveform output by a compare match. Output selection Select waveform output mode [1] [1] Select initial value from 0-output or 1-output, and compare match output value from 0-output, 1-output, or toggle-output, by means of TIOR. The set initial value is output on the TIOC pin until the first compare match occurs. [2] Set the timing for compare match generation in TGR. [3] Set the CST bit in TSTR to 1 to start the count operation. Set output timing [2] Start count [3] Figure 10.6 Example of Setting Procedure for Waveform Output by Compare Match Rev. 2.00 Mar. 15, 2006 Page 340 of 754 REJ09B0199-0200 Section 10 16-Bit Timer Pulse Unit (TPU) (b) Examples of waveform output operation Figure 10.7 shows an example of 0-output and 1-output. In this example, TCNT has been designated as a free-running counter, and settings have been made so that 1 is output by compare match A, and 0 is output by compare match B. When the set level and the pin level match, the pin level does not change. TCNT value H'FFFF TGRA TGRB H'0000 No change TIOCA TIOCB No change No change No change 1-output 0-output Time Figure 10.7 Example of 0-Output/1-Output Operation Figure 10.8 shows an example of toggle output. In this example, TCNT has been designated as a periodic counter (with counter clearing performed by compare match B), and settings have been made so that output is toggled by both compare match A and compare match B. TCNT value Counter cleared by TGRB compare match H'FFFF TGRB TGRA H'0000 Time Toggle-output Toggle-output TIOCB TIOCA Figure 10.8 Example of Toggle Output Operation Rev. 2.00 Mar. 15, 2006 Page 341 of 754 REJ09B0199-0200 Section 10 16-Bit Timer Pulse Unit (TPU) (3) Input Capture Function The TCNT value can be transferred to TGR on detection of the TIOC pin input edge. Rising edge, falling edge, or both edges can be selected as the detection edge. For channels 0, 1, 3, and 4, it is also possible to specify another channel's counter input clock or compare match signal as the input capture source. Note: When another channel's counter input clock is used as the input capture input for channels 0 and 3, P/1 should not be selected as the counter input clock used for input capture input. Input capture will not be generated if P/1 is selected. (a) Example of setting procedure for input capture operation Figure 10.9 shows an example of the setting procedure for input capture operation. Input selection Select input capture input [1] [1] Designate TGR as an input capture register by means of TIOR, and select the input capture source and input signal edge (rising edge, falling edge, or both edges). [2] Set the CST bit in TSTR to 1 to start the count operation. Start count [2] Figure 10.9 Example of Setting Procedure for Input Capture Operation Rev. 2.00 Mar. 15, 2006 Page 342 of 754 REJ09B0199-0200 Section 10 16-Bit Timer Pulse Unit (TPU) (b) Example of input capture operation Figure 10.10 shows an example of input capture operation. In this example, both rising and falling edges have been selected as the TIOCA pin input capture input edge, falling edge has been selected as the TIOCB pin input capture input edge, and counter clearing by TGRB input capture has been designated for TCNT. Counter cleared by TIOCB input (falling edge) TCNT value H'0180 H'0160 H'0010 H'0005 H'0000 Time TIOCA TGRA H'0005 H'0160 H'0010 TIOCB TGRB H'0180 Figure 10.10 Example of Input Capture Operation Rev. 2.00 Mar. 15, 2006 Page 343 of 754 REJ09B0199-0200 Section 10 16-Bit Timer Pulse Unit (TPU) 10.4.2 Synchronous Operation In synchronous operation, the values in multiple TCNT counters can be rewritten simultaneously (synchronous presetting). Also, multiple TCNT counters can be cleared simultaneously (synchronous clearing) by making the appropriate setting in TCR. Synchronous operation enables TGR to be incremented with respect to a single time base. Channels 0 to 5 can all be designated for synchronous operation. (1) Example of Synchronous Operation Setting Procedure Figure 10.11 shows an example of the synchronous operation setting procedure. Synchronous operation selection Set synchronous operation [1] Synchronous presetting Synchronous clearing Set TCNT [2] Clearing source generation channel? Yes Select counter clearing source No [3] Set synchronous counter clearing [4] Start count [5] Start count [5] [1] Set the SYNC bits in TSYR corresponding to the channels to be designated for synchronous operation to 1. [2] When the TCNT counter of any of the channels designated for synchronous operation is written to, the same value is simultaneously written to the other TCNT counters. [3] Use bits CCLR2 to CCLR0 in TCR to specify TCNT clearing by input capture/output compare, etc. [4] Use bits CCLR2 to CCLR0 in TCR to designate synchronous clearing for the counter clearing source. [5] Set the CST bits in TSTR for the relevant channels to 1, to start the count operation. Figure 10.11 Example of Synchronous Operation Setting Procedure Rev. 2.00 Mar. 15, 2006 Page 344 of 754 REJ09B0199-0200 Section 10 16-Bit Timer Pulse Unit (TPU) (2) Example of Synchronous Operation Figure 10.12 shows an example of synchronous operation. In this example, synchronous operation and PWM mode 1 have been designated for channels 0 to 2, TGRB_0 compare match has been set as the channel 0 counter clearing source, and synchronous clearing has been set for the channel 1 and 2 counter clearing source. Three-phase PWM waveforms are output from pins TIOCA0, TIOCA1, and TIOCA2. At this time, synchronous presetting and synchronous clearing by TGRB_0 compare match are performed for channel 0 to 2 TCNT counters, and the data set in TGRB_0 is used as the PWM cycle. For details on PWM modes, see section 10.4.5, PWM Modes. Synchronous clearing by TGRB_0 compare match TCNT_0 to TCNT_2 values TGRB_0 TGRB_1 TGRA_0 TGRB_2 TGRA_1 TGRA_2 H'0000 Time TIOCA_0 TIOCA_1 TIOCA_2 Figure 10.12 Example of Synchronous Operation Rev. 2.00 Mar. 15, 2006 Page 345 of 754 REJ09B0199-0200 Section 10 16-Bit Timer Pulse Unit (TPU) 10.4.3 Buffer Operation Buffer operation, provided for channels 0 and 3, enables TGRC and TGRD to be used as buffer registers. Buffer operation differs depending on whether TGR has been designated as an input capture register or a compare match register. Table 10.31 shows the register combinations used in buffer operation. Table 10.31 Register Combinations in Buffer Operation Channel 0 Timer General Register TGRA_0 TGRB_0 3 TGRA_3 TGRB_3 Buffer Register TGRC_0 TGRD_0 TGRC_3 TGRD_3 * When TGR is an output compare register When a compare match occurs, the value in the buffer register for the corresponding channel is transferred to the timer general register. This operation is illustrated in figure 10.13. Compare match signal Buffer register Timer general register Comparator TCNT Figure 10.13 Compare Match Buffer Operation Rev. 2.00 Mar. 15, 2006 Page 346 of 754 REJ09B0199-0200 Section 10 16-Bit Timer Pulse Unit (TPU) * When TGR is an input capture register When input capture occurs, the value in TCNT is transferred to TGR and the value previously held in TGR is transferred to the buffer register. This operation is illustrated in figure 10.14. Input capture signal Timer general register Buffer register TCNT Figure 10.14 Input Capture Buffer Operation (1) Example of Buffer Operation Setting Procedure Figure 10.15 shows an example of the buffer operation setting procedure. [1] Designate TGR as an input capture register or output compare register by means of TIOR. [1] Buffer operation Select TGR function [2] Designate TGR for buffer operation with bits BFA and BFB in TMDR. [3] Set the CST bit in TSTR to 1 to start the count operation. Set buffer operation [2] Start count [3] Figure 10.15 Example of Buffer Operation Setting Procedure Rev. 2.00 Mar. 15, 2006 Page 347 of 754 REJ09B0199-0200 Section 10 16-Bit Timer Pulse Unit (TPU) (2) (a) Examples of Buffer Operation: When TGR is an output compare register Figure 10.16 shows an operation example in which PWM mode 1 has been designated for channel 0, and buffer operation has been designated for TGRA and TGRC. The settings used in this example are TCNT clearing by compare match B, 1 output at compare match A, and 0 output at compare match B. As buffer operation has been set, when compare match A occurs, the output changes and the value in buffer register TGRC is simultaneously transferred to timer general register TGRA. This operation is repeated each time compare match A occurs. For details on PWM modes, see section 10.4.5, PWM Modes. TCNT value TGRB_0 H'0200 TGRA_0 H'0000 TGRC_0 H'0200 Transfer TGRA_0 H'0200 H'0450 H'0450 H'0520 Time H'0520 H'0450 TIOCA Figure 10.16 Example of Buffer Operation (1) (b) When TGR is an input capture register Figure 10.17 shows an operation example in which TGRA has been designated as an input capture register, and buffer operation has been designated for TGRA and TGRC. Counter clearing by TGRA input capture has been set for TCNT, and both rising and falling edges have been selected as the TIOCA pin input capture input edge. As buffer operation has been set, when the TCNT value is stored in TGRA upon occurrence of input capture A, the value previously stored in TGRA is simultaneously transferred to TGRC. Rev. 2.00 Mar. 15, 2006 Page 348 of 754 REJ09B0199-0200 Section 10 16-Bit Timer Pulse Unit (TPU) TCNT value H'0F07 H'09FB H'0532 H'0000 Time TIOCA TGRA H'0532 H'0F07 H'09FB TGRC H'0532 H'0F07 Figure 10.17 Example of Buffer Operation (2) 10.4.4 Cascaded Operation In cascaded operation, two 16-bit counters for different channels are used together as a 32-bit counter. This function works by counting the channel 1 (channel 4) counter clock at overflow/underflow of TCNT_2 (TCNT_5) as set in bits TPSC2 to TPSC0 in TCR. Underflow occurs only when the lower 16-bit TCNT is in phase-counting mode. Table 10.32 shows the register combinations used in cascaded operation. Note: When phase counting mode is set for channel 1 or 4, the counter clock setting is invalid and the counter operates independently in phase counting mode. Table 10.32 Cascaded Combinations Combination Channels 1 and 2 Channels 4 and 5 Upper 16 Bits TCNT_1 TCNT_4 Lower 16 Bits TCNT_2 TCNT_5 Rev. 2.00 Mar. 15, 2006 Page 349 of 754 REJ09B0199-0200 Section 10 16-Bit Timer Pulse Unit (TPU) (1) Example of Cascaded Operation Setting Procedure Figure 10.18 shows an example of the setting procedure for cascaded operation. [1] Set bits TPSC2 to TPSC0 in the channel 1 (channel 4) TCR to B'1111 to select TCNT_2 (TCNT_5) overflow/underflow counting. [1] [2] Set the CST bit in TSTR for the upper and lower channels to 1 to start the count operation. Cascaded operation Set cascading Start count [2] Figure 10.18 Example of Cascaded Operation Setting Procedure (2) Examples of Cascaded Operation Figure 10.19 illustrates the operation when counting upon TCNT_2 overflow/underflow has been set for TCNT_1, TGRA_1 and TGRA_2 have been designated as input capture registers, and the TIOC pin rising edge has been selected. When a rising edge is input to the TIOCA1 and TIOCA2 pins simultaneously, the upper 16 bits of the 32-bit data are transferred to TGRA_1, and the lower 16 bits to TGRA_2. TCNT_1 clock TCNT_1 TCNT_2 clock TCNT_2 TIOCA1, TIOCA2 TGRA_1 H'03A2 H'FFFF H'0000 H'0001 H'03A1 H'03A2 TGRA_2 H'0000 Figure 10.19 Example of Cascaded Operation (1) Rev. 2.00 Mar. 15, 2006 Page 350 of 754 REJ09B0199-0200 Section 10 16-Bit Timer Pulse Unit (TPU) Figure 10.20 illustrates the operation when counting upon TCNT_2 overflow/underflow has been set for TCNT_1, and phase counting mode has been designated for channel 2. TCNT_1 is incremented by TCNT_2 overflow and decremented by TCNT_2 underflow. TCLKC TCLKD TCNT_2 FFFD FFFE FFFF 0000 0001 0002 0001 0000 FFFF TCNT_1 0000 0001 0000 Figure 10.20 Example of Cascaded Operation (2) 10.4.5 PWM Modes In PWM mode, PWM waveforms are output from the output pins. 0-, 1-, or toggle-output can be selected as the output level in response to compare match of each TGR. Settings of TGR registers can output a PWM waveform in the range of 0% to 100% duty cycle. Designating TGR compare match as the counter clearing source enables the cycle to be set in that register. All channels can be designated for PWM mode independently. Synchronous operation is also possible. There are two PWM modes, as described below. 1. PWM mode 1 PWM output is generated from the TIOCA and TIOCC pins by pairing TGRA with TGRB and TGRC with TGRD. The outputs specified by bits IOA3 to IOA0 and IOC3 to IOC0 in TIOR are output from the TIOCA and TIOCC pins at compare matches A and C, respectively. The outputs specified by bits IOB3 to IOB0 and IOD3 to IOD0 in TIOR are output at compare matches B and D, respectively. The initial output value is the value set in TGRA or TGRC. If the set values of paired TGRs are identical, the output value does not change when a compare match occurs. In PWM mode 1, a maximum 8-phase PWM output is possible. Rev. 2.00 Mar. 15, 2006 Page 351 of 754 REJ09B0199-0200 Section 10 16-Bit Timer Pulse Unit (TPU) 2. PWM mode 2 PWM output is generated using one TGR as the cycle register and the others as duty cycle registers. The output specified in TIOR is performed by means of compare matches. Upon counter clearing by a cycle register compare match, the output value of each pin is the initial value set in TIOR. If the set values of the cycle and duty cycle registers are identical, the output value does not change when a compare match occurs. In PWM mode 2, a maximum 15-phase PWM output is possible by combined use with synchronous operation. The correspondence between PWM output pins and registers is shown in table 10.33. Table 10.33 PWM Output Registers and Output Pins Output Pins Channel 0 Registers TGRA_0 TGRB_0 TGRC_0 TGRD_0 1 TGRA_1 TGRB_1 2 TGRA_2 TGRB_2 3 TGRA_3 TGRB_3 TGRC_3 TGRD_3 4 TGRA_4 TGRB_4 5 TGRA_5 TGRB_5 TIOCA5 TIOCA4 TIOCC3 TIOCA3 TIOCA2 TIOCA1 TIOCC0 PWM Mode 1 TIOCA0 PWM Mode 2 TIOCA0 TIOCB0 TIOCC0 TIOCD0 TIOCA1 TIOCB1 TIOCA2 TIOCB2 TIOCA3 TIOCB3 TIOCC3 TIOCD3 TIOCA4 TIOCB4 TIOCA5 TIOCB5 Note: In PWM mode 2, PWM output is not possible for the TGR register in which the cycle is set. Rev. 2.00 Mar. 15, 2006 Page 352 of 754 REJ09B0199-0200 Section 10 16-Bit Timer Pulse Unit (TPU) (1) Example of PWM Mode Setting Procedure Figure 10.21 shows an example of the PWM mode setting procedure. PWM mode [1] Select the counter clock with bits TPSC2 to TPSC0 in TCR. At the same time, select the [1] input clock edge with bits CKEG1 and CKEG0 in TCR. [2] Use bits CCLR2 to CCLR0 in TCR to select the TGR to be used as the TCNT clearing source. [3] Use TIOR to designate TGR as an output Select counter clock Select counter clearing source [2] Select waveform output level [3] compare register, and select the initial value and output value. [4] Set the cycle in TGR selected in [2], and set the duty in the other TGRs. [5] Select the PWM mode with bits MD3 to MD0 in TMDR. [6] Set the CST bit in TSTR to 1 to start the count operation. Set TGR [4] Set PWM mode [5] Start count [6] Figure 10.21 Example of PWM Mode Setting Procedure (2) Examples of PWM Mode Operation Figure 10.22 shows an example of PWM mode 1 operation. In this example, TGRA compare match is set as the TCNT clearing source, 0 is set for the TGRA initial output value and output value, and 1 is set as the TGRB output value. In this case, the value set in TGRA is used as the cycle, and the value set in TGRB register as the duty cycle. Rev. 2.00 Mar. 15, 2006 Page 353 of 754 REJ09B0199-0200 Section 10 16-Bit Timer Pulse Unit (TPU) TCNT value TGRA Counter cleared by TGRA compare match TGRB H'0000 TIOCA Time Figure 10.22 Example of PWM Mode Operation (1) Figure 10.23 shows an example of PWM mode 2 operation. In this example, synchronous operation is designated for channels 0 and 1, TGRB_1 compare match is set as the TCNT clearing source, and 0 is set for the initial output value and 1 for the output value of the other TGR registers (TGRA_0 to TGRD_0, TGRA_1), to output a 5-phase PWM waveform. In this case, the value set in TGRB_1 is used as the cycle, and the values set in the other TGRs as the duty cycle. TCNT value TGRB_1 TGRA_1 TGRD_0 TGRC_0 TGRB_0 TGRA_0 H'0000 TIOCA0 Counter cleared by TGRB_1 compare match Time TIOCB0 TIOCC0 TIOCD0 TIOCA1 Figure 10.23 Example of PWM Mode Operation (2) Rev. 2.00 Mar. 15, 2006 Page 354 of 754 REJ09B0199-0200 Section 10 16-Bit Timer Pulse Unit (TPU) Figure 10.24 shows examples of PWM waveform output with 0% duty cycle and 100% duty cycle in PWM mode. TCNT value TGRB changed TGRA TGRB H'0000 TGRB changed TGRB changed Time TIOCA 0% duty TCNT value TGRB changed TGRA Output does not change when compare matches in cycle register and duty register occur simultaneously TGRB changed TGRB H'0000 100% duty TGRB changed Time TIOCA TCNT value TGRB changed TGRA Output does not change when compare matches in cycle register and duty register occur simultaneously TGRB changed TGRB H'0000 100% duty 0% duty TGRB changed Time TIOCA Figure 10.24 Example of PWM Mode Operation (3) Rev. 2.00 Mar. 15, 2006 Page 355 of 754 REJ09B0199-0200 Section 10 16-Bit Timer Pulse Unit (TPU) 10.4.6 Phase Counting Mode In phase counting mode, the phase difference between two external clock inputs is detected and TCNT is incremented/decremented accordingly. This mode can be set for channels 1, 2, 4, and 5. When phase counting mode is set, an external clock is selected as the counter input clock and TCNT operates as an up/down-counter regardless of the setting of bits TPSC2 to TPSC0 and bits CKEG1 and CKEG0 in TCR. However, the functions of bits CCLR1 and CCLR0 in TCR, and of TIOR, TIER, and TGR are valid, and input capture/compare match and interrupt functions can be used. This can be used for two-phase encoder pulse input. When overflow occurs while TCNT is counting up, the TCFV flag in TSR is set; when underflow occurs while TCNT is counting down, the TCFU flag is set. The TCFD bit in TSR is the count direction flag. Reading the TCFD flag provides an indication of whether TCNT is counting up or down. Table 10.34 shows the correspondence between external clock pins and channels. Table 10.34 Clock Input Pins in Phase Counting Mode External Clock Pins Channels When channel 1 or 5 is set to phase counting mode When channel 2 or 4 is set to phase counting mode A-Phase TCLKA TCLKC B-Phase TCLKB TCLKD (1) Example of Phase Counting Mode Setting Procedure Figure 10.25 shows an example of the phase counting mode setting procedure. [1] Select phase counting mode with bits MD3 to MD0 in TMDR. [2] Set the CST bit in TSTR to 1 to start the count operation. Phase counting mode Select phase counting mode Start count [1] [2] Figure 10.25 Example of Phase Counting Mode Setting Procedure Rev. 2.00 Mar. 15, 2006 Page 356 of 754 REJ09B0199-0200 Section 10 16-Bit Timer Pulse Unit (TPU) (2) Examples of Phase Counting Mode Operation In phase counting mode, TCNT counts up or down according to the phase difference between two external clocks. There are four modes, according to the count conditions. (a) Phase counting mode 1 Figure 10.26 shows an example of phase counting mode 1 operation, and table 10.35 summarizes the TCNT up/down-count conditions. TCLKA (channels 1 and 5) TCLKC (channels 2 and 4) TCLKB (channels 1 and 5) TCLKD (channels 2 and 4) TCNT value Up-count Down-count Time Figure 10.26 Example of Phase Counting Mode 1 Operation Table 10.35 Up/Down-Count Conditions in Phase Counting Mode 1 TCLKA (Channels 1 and 5) TCLKC (Channels 2 and 4) High level Low level Low level High level High level Low level High level Low level [Legend] : Rising edge : Falling edge Down-count TCLKB (Channels 1 and 5) TCLKD (Channels 2 and 4) Operation Up-count Rev. 2.00 Mar. 15, 2006 Page 357 of 754 REJ09B0199-0200 Section 10 16-Bit Timer Pulse Unit (TPU) (b) Phase counting mode 2 Figure 10.27 shows an example of phase counting mode 2 operation, and table 10.36 summarizes the TCNT up/down-count conditions. TCLKA (channels 1 and 5) TCLKC (channels 2 and 4) TCLKB (channels 1 and 5) TCLKD (channels 2 and 4) TCNT value Up-count Down-count Time Figure 10.27 Example of Phase Counting Mode 2 Operation Table 10.36 Up/Down-Count Conditions in Phase Counting Mode 2 TCLKA (Channels 1 and 5) TCLKC (Channels 2 and 4) High level Low level Low level High level High level Low level High level Low level [Legend] : Rising edge : Falling edge TCLKB (Channels 1 and 5) TCLKD (Channels 2 and 4) Operation Don't care Don't care Don't care Up-count Don't care Don't care Don't care Down-count Rev. 2.00 Mar. 15, 2006 Page 358 of 754 REJ09B0199-0200 Section 10 16-Bit Timer Pulse Unit (TPU) (c) Phase counting mode 3 Figure 10.28 shows an example of phase counting mode 3 operation, and table 10.37 summarizes the TCNT up/down-count conditions. TCLKA (channels 1 and 5) TCLKC (channels 2 and 4) TCLKB (channels 1 and 5) TCLKD (channels 2 and 4) TCNT value Up-count Down-count Time Figure 10.28 Example of Phase Counting Mode 3 Operation Table 10.37 Up/Down-Count Conditions in Phase Counting Mode 3 TCLKA (Channels 1 and 5) TCLKC (Channels 2 and 4) High level Low level Low level High level High level Low level High level Low level [Legend] : Rising edge : Falling edge TCLKB (Channels 1 and 5) TCLKD (Channels 2 and 4) Operation Don't care Don't care Don't care Up-count Down-count Don't care Don't care Don't care Rev. 2.00 Mar. 15, 2006 Page 359 of 754 REJ09B0199-0200 Section 10 16-Bit Timer Pulse Unit (TPU) (d) Phase counting mode 4 Figure 10.29 shows an example of phase counting mode 4 operation, and table 10.38 summarizes the TCNT up/down-count conditions. TCLKA (channels 1 and 5) TCLKC (channels 2 and 4) TCLKB (channels 1 and 5) TCLKD (channels 2 and 4) TCNT value Up-count Down-count Time Figure 10.29 Example of Phase Counting Mode 4 Operation Table 10.38 Up/Down-Count Conditions in Phase Counting Mode 4 TCLKA (Channels 1 and 5) TCLKC (Channels 2 and 4) High level Low level Low level High level High level Low level High level Low level [Legend] : Rising edge : Falling edge Don't care Down-count Don't care TCLKB (Channels 1 and 5) TCLKD (Channels 2 and 4) Operation Up-count Rev. 2.00 Mar. 15, 2006 Page 360 of 754 REJ09B0199-0200 Section 10 16-Bit Timer Pulse Unit (TPU) (3) Phase Counting Mode Application Example Figure 10.30 shows an example in which phase counting mode is designated for channel 1, and channel 1 is coupled with channel 0 to input servo motor 2-phase encoder pulses in order to detect the position or speed. Channel 1 is set to phase counting mode 1, and the encoder pulse A-phase and B-phase are input to TCLKA and TCLKB. Channel 0 operates with TCNT counter clearing by TGRC_0 compare match; TGRA_0 and TGRC_0 are used for the compare match function and are set with the speed control cycle and position control cycle. TGRB_0 is used for input capture, with TGRB_0 and TGRD_0 operating in buffer mode. The channel 1 counter input clock is designated as the TGRB_0 input capture source, and the pulse width of 2-phase encoder 4-multiplication pulses is detected. TGRA_1 and TGRB_1 for channel 1 are designated for input capture, channel 0 TGRA_0 and TGRC_0 compare matches are selected as the input capture source, and the up/down-counter values for the control cycles are stored. This procedure enables accurate position/speed detection to be achieved. Channel 1 TCLKA TCLKB Edge detection circuit TCNT_1 TGRA_1 (speed cycle capture) TGRB_1 (position cycle capture) TCNT_0 TGRA_0 (speed control cycle) TGRC_0 (position control cycle) TGRB_0 (pulse width capture) TGRD_0 (buffer operation) Channel 0 + + - Figure 10.30 Phase Counting Mode Application Example Rev. 2.00 Mar. 15, 2006 Page 361 of 754 REJ09B0199-0200 Section 10 16-Bit Timer Pulse Unit (TPU) 10.5 Interrupt Sources There are three kinds of TPU interrupt sources: TGR input capture/compare match, TCNT overflow, and TCNT underflow. Each interrupt source has its own status flag and enable/disable bit, allowing generation of interrupt request signals to be enabled or disabled individually. When an interrupt request is generated, the corresponding status flag in TSR is set to 1. If the corresponding enable/disable bit in TIER is set to 1 at this time, an interrupt is requested. The interrupt request is cleared by clearing the status flag to 0. Relative channel priority levels can be changed by the interrupt controller, but the priority within a channel is fixed. For details, see section 5, Interrupt Controller. Table 10.39 lists the TPU interrupt sources. Table 10.39 TPU Interrupts Channel Name 0 TGI0A TGI0B TGI0C TGI0D TCI0V 1 TGI1A TGI1B TCI1V TCI1U 2 TGI2A TGI2B TCI2V TCI2U 3 TGI3A TGI3B TGI3C TGI3D TCI3V Interrupt Source Interrupt DTC Flag Activation DMAC Activation Possible Not possible Not possible Not possible Possible TGRA_0 input capture/compare match TGFA_0 Possible TGRB_0 input capture/compare match TGFB_0 Possible TGRC_0 input capture/compare match TGFC_0 Possible TGRD_0 input capture/compare match TGFD_0 Possible TCNT_0 overflow TCFV_0 TGRA_1 input capture/compare match TGFA_1 Possible TCNT_1 overflow TCNT_1 underflow TCFV_1 Not possible Not possible TGRB_1 input capture/compare match TGFB_1 Not possible Not possible Not possible Not possible Not possible Possible TCFU_1 Possible TGRA_2 input capture/compare match TGFA_2 Possible TCNT_2 overflow TCNT_2 underflow TCFV_2 TGRB_2 input capture/compare match TGFB_2 Not possible Not possible Not possible Not possible Not possible Possible Not possible Not possible Not possible TCFU_2 Possible TGRA_3 input capture/compare match TGFA_3 Possible TGRB_3 input capture/compare match TGFB_3 Possible TGRC_3 input capture/compare match TGFC_3 Possible TGRD_3 input capture/compare match TGFD_3 Possible TCNT_3 overflow TCFV_3 Not possible Not possible Rev. 2.00 Mar. 15, 2006 Page 362 of 754 REJ09B0199-0200 Section 10 16-Bit Timer Pulse Unit (TPU) Channel Name 4 TGI4A TGI4B TCI4V TCI4U 5 TGI5A TGI5B TCI5V TCI5U 6 TGI6A TGI6B TGI6C TGI6D TCI6V 7 TGI7A TGI7B TCI7V TCI7U 8 TGI8A TGI8B TCI8V TCI8U 9 TGI9A TGI9B TGI9C TGI9D TCI9V 10 Interrupt Source Interrupt DTC Flag Activation DMAC Activation Possible Not possible TGRA_4 input capture/compare match TGFA_4 Possible TGRB_4 input capture/compare match TGFB_4 Possible TCNT_4 overflow TCNT_4 underflow TCFV_4 Not possible Not possible TCFU_4 Not possible Not possible Possible Not possible TGRA_5 input capture/compare match TGFA_5 Possible TGRB_5 input capture/compare match TGFB_5 Possible TCNT_5 overflow TCNT_5 underflow TCFV_5 Not possible Not possible TCFU_5 Not possible Not possible Possible Not possible Not possible Not possible TGRA_0 input capture/compare match TGFA_0 Possible TGRB_0 input capture/compare match TGFB_0 Possible TGRC_0 input capture/compare match TGFC_0 Possible TGRD_0 input capture/compare match TGFD_0 Possible TCNT_0 overflow TCFV_0 Not possible Not possible Possible TGRA_1 input capture/compare match TGFA_1 Possible TGRB_1 input capture/compare match TGFB_1 Not possible Not possible TCNT_1 overflow TCNT_1 underflow TCFV_1 Not possible Not possible Not possible Possible TCFU_1 Possible TGRA_2 input capture/compare match TGFA_2 Possible TGRB_2 input capture/compare match TGFB_2 Not possible Not possible TCNT_2 overflow TCNT_2 underflow TCFV_2 Not possible Not possible Not possible Possible Not possible Not possible Not possible TCFU_2 Possible TGRA_3 input capture/compare match TGFA_3 Possible TGRB_3 input capture/compare match TGFB_3 Possible TGRC_3 input capture/compare match TGFC_3 Possible TGRD_3 input capture/compare match TGFD_3 Possible TCNT_3 overflow TCFV_3 Not possible Not possible Possible Not possible TGI10A TGRA_4 input capture/compare match TGFA_4 Possible TGI10B TGRB_4 input capture/compare match TGFB_4 Possible TCI10V TCNT_4 overflow TCI10U TCNT_4 underflow TCFV_4 Not possible Not possible TCFU_4 Not possible Not possible Rev. 2.00 Mar. 15, 2006 Page 363 of 754 REJ09B0199-0200 Section 10 16-Bit Timer Pulse Unit (TPU) Channel Name 11 Interrupt Source Interrupt DTC Flag Activation DMAC Activation Possible Not possible TGI11A TGRA_5 input capture/compare match TGFA_5 Possible TGI11B TGRB_5 input capture/compare match TGFB_5 Possible TCI11V TCNT_5 overflow TCI11U TCNT_5 underflow TCFV_5 Not possible Not possible TCFU_5 Not possible Not possible Note: This table shows the initial state immediately after a reset. The relative channel priority levels can be changed by the interrupt controller. (1) Input Capture/Compare Match Interrupt An interrupt is requested if the TGIE bit in TIER is set to 1 when the TGF flag in TSR is set to 1 by the occurrence of a TGR input capture/compare match on a channel. The interrupt request is cleared by clearing the TGF flag to 0. The TPU has 16 input capture/compare match interrupts, four each for channels 0 and 3, and two each for channels 1, 2, 4, and 5. (2) Overflow Interrupt An interrupt is requested if the TCIEV bit in TIER is set to 1 when the TCFV flag in TSR is set to 1 by the occurrence of a TCNT overflow on a channel. The interrupt request is cleared by clearing the TCFV flag to 0. The TPU has six overflow interrupts, one for each channel. (3) Underflow Interrupt An interrupt is requested if the TCIEU bit in TIER is set to 1 when the TCFU flag in TSR is set to 1 by the occurrence of a TCNT underflow on a channel. The interrupt request is cleared by clearing the TCFU flag to 0. The TPU has four underflow interrupts, one each for channels 1, 2, 4, and 5. Rev. 2.00 Mar. 15, 2006 Page 364 of 754 REJ09B0199-0200 Section 10 16-Bit Timer Pulse Unit (TPU) 10.6 DTC Activation The DTC can be activated by the TGR input capture/compare match interrupt for a channel. For details, see section 8, Data Transfer Controller (DTC). A total of 16 TPU input capture/compare match interrupts can be used as DTC activation sources, four each for channels 0 and 3, and two each for channels 1, 2, 4, and 5. 10.7 DMAC Activation The DMAC can be activated by the TGR input capture/compare match interrupt for a channel. For details, see section 7, DMA Controller (DMAC). A total of six TPU input capture/compare match interrupts can be used as DMAC activation sources, one for each channel. 10.8 A/D Converter Activation The TGRA input capture/compare match for each channel of unit 0 can activate the A/D converter (this function is not available for unit 1). If the TTGE bit in TIER is set to 1 when the TGFA flag in TSR is set to 1 by the occurrence of a TGRA input capture/compare match on a particular channel, a request to start A/D conversion is sent to the A/D converter. If the TPU conversion start trigger has been selected on the A/D converter side at this time, A/D conversion is started. In the TPU, a total of six TGRA input capture/compare match interrupts can be used as A/D converter conversion start sources, one for each channel. The A/D converter cannot be activated by unit 1. Rev. 2.00 Mar. 15, 2006 Page 365 of 754 REJ09B0199-0200 Section 10 16-Bit Timer Pulse Unit (TPU) 10.9 10.9.1 (1) Operation Timing Input/Output Timing TCNT Count Timing Figure 10.31 shows TCNT count timing in internal clock operation, and figure 10.32 shows TCNT count timing in external clock operation. P Internal clock Falling edge Rising edge Falling edge TCNT input clock TCNT N-1 N N+1 N+2 Figure 10.31 Count Timing in Internal Clock Operation P External clock Falling edge Rising edge Falling edge TCNT input clock TCNT N-1 N N+1 N+2 Figure 10.32 Count Timing in External Clock Operation Rev. 2.00 Mar. 15, 2006 Page 366 of 754 REJ09B0199-0200 Section 10 16-Bit Timer Pulse Unit (TPU) (2) Output Compare Output Timing A compare match signal is generated in the final state in which TCNT and TGR match (the point at which the count value matched by TCNT is updated). When a compare match signal is generated, the output value set in TIOR is output at the output compare output pin (TIOC pin). After a match between TCNT and TGR, the compare match signal is not generated until the TCNT input clock is generated. Figure 10.33 shows output compare output timing. P TCNT input clock TCNT TGR Compare match signal TIOC pin N N N+1 Figure 10.33 Output Compare Output Timing (3) Input Capture Signal Timing Figure 10.34 shows input capture signal timing. P Input capture input Input capture signal TCNT N N+1 N N+2 N+2 TGR Figure 10.34 Input Capture Input Signal Timing Rev. 2.00 Mar. 15, 2006 Page 367 of 754 REJ09B0199-0200 Section 10 16-Bit Timer Pulse Unit (TPU) (4) Timing for Counter Clearing by Compare Match/Input Capture Figure 10.35 shows the timing when counter clearing by compare match occurrence is specified, and figure 10.36 shows the timing when counter clearing by input capture occurrence is specified. P Compare match signal Counter clear signal TCNT TGR N N H'0000 Figure 10.35 Counter Clear Timing (Compare Match) P Input capture signal Counter clear signal TCNT N H'0000 TGR N Figure 10.36 Counter Clear Timing (Input Capture) Rev. 2.00 Mar. 15, 2006 Page 368 of 754 REJ09B0199-0200 Section 10 16-Bit Timer Pulse Unit (TPU) (5) Buffer Operation Timing Figures 10.37 and 10.38 show the timings in buffer operation. P TCNT Compare match signal TGRA, TGRB TGRC, TGRD n N n+1 n N Figure 10.37 Buffer Operation Timing (Compare Match) P Input capture signal TCNT TGRA, TGRB TGRC, TGRD N N+1 N+1 n N n N Figure 10.38 Buffer Operation Timing (Input Capture) Rev. 2.00 Mar. 15, 2006 Page 369 of 754 REJ09B0199-0200 Section 10 16-Bit Timer Pulse Unit (TPU) 10.9.2 (1) Interrupt Signal Timing TGF Flag Setting Timing in Case of Compare Match Figure 10.39 shows the timing for setting of the TGF flag in TSR by compare match occurrence, and the TGI interrupt request signal timing. P TCNT input clock TCNT N N+1 TGR Compare match signal TGF flag N TGI interrupt Figure 10.39 TGI Interrupt Timing (Compare Match) (2) TGF Flag Setting Timing in Case of Input Capture Figure 10.40 shows the timing for setting of the TGF flag in TSR by input capture occurrence, and the TGI interrupt request signal timing. P Input capture signal TCNT N TGR N TGF flag TGI interrupt Figure 10.40 TGI Interrupt Timing (Input Capture) Rev. 2.00 Mar. 15, 2006 Page 370 of 754 REJ09B0199-0200 Section 10 16-Bit Timer Pulse Unit (TPU) (3) TCFV Flag/TCFU Flag Setting Timing Figure 10.41 shows the timing for setting of the TCFV flag in TSR by overflow occurrence, and the TCIV interrupt request signal timing. Figure 10.42 shows the timing for setting of the TCFU flag in TSR by underflow occurrence, and the TCIU interrupt request signal timing. P TCNT input clock TCNT (overflow) Overflow signal TCFV flag TCIV interrupt H'FFFF H'0000 Figure 10.41 TCIV Interrupt Setting Timing P TCNT input clock TCNT (underflow) Underflow signal H'0000 H'FFFF TCFU flag TCIU interrupt Figure 10.42 TCIU Interrupt Setting Timing Rev. 2.00 Mar. 15, 2006 Page 371 of 754 REJ09B0199-0200 Section 10 16-Bit Timer Pulse Unit (TPU) (4) Status Flag Clearing Timing After a status flag is read as 1 by the CPU, it is cleared by writing 0 to it. When the DTC or DMAC is activated, the flag is cleared automatically. Figure 10.43 shows the timing for status flag clearing by the CPU, and figure 10.44 shows the timing for status flag clearing by the DTC or DMAC. TSR write cycle T2 T1 P Address TSR address Write Status flag Interrupt request signal Figure 10.43 Timing for Status Flag Clearing by CPU The status flag and interrupt request signal are cleared in synchronization with P after the DTC or DMAC transfer has started, as shown in figure 10.44. If conflict occurs for clearing the status flag and interrupt request signal due to activation of multiple DTC or DMAC transfers, it will take up to five clock cycles (P) for clearing them, as shown in figure 10.45. The next transfer request is masked for a longer period of either a period until the current transfer ends or a period for five clock cycles (P) from the beginning of the transfer. Note that in the DTC transfer, the status flag may be cleared during outputting the destination address. DTC/DMAC read cycle T1 T2 P Address Status flag Period in which the next transfer request is masked Interrupt request signal Source address Destination address DTC/DMAC write cycle T2 T1 Figure 10.44 Timing for Status Flag Clearing by DMAC Activation (1) Rev. 2.00 Mar. 15, 2006 Page 372 of 754 REJ09B0199-0200 Section 10 16-Bit Timer Pulse Unit (TPU) DTC/DMAC read cycle P Address Source address Period in which the next transfer request is masked Status flag Interrupt request signal Period of flag clearing DTC/DMAC write cycle Destination address Period of interrupt request signal clearing Figure 10.45 Timing for Status Flag Clearing by DMAC Activation (2) 10.10 Usage Notes 10.10.1 Module Stop Mode Setting Operation of the TPU can be disabled or enabled using the module stop control register. The initial setting is for operation of the TPU to be halted. Register access is enabled by clearing module stop mode. For details, refer to section 19, Power-Down Modes. 10.10.2 Input Clock Restrictions The input clock pulse width must be at least 1.5 states in the case of single-edge detection, and at least 2.5 states in the case of both-edge detection. The TPU will not operate properly with a narrower pulse width. In phase counting mode, the phase difference and overlap between the two input clocks must be at least 1.5 states, and the pulse width must be at least 2.5 states. Figure 10.46 shows the input clock conditions in phase counting mode. Phase Phase difference difference Overlap Overlap TCLKA (TCLKC) TCLKB (TCLKD) Pulse width Pulse width Pulse width Pulse width Note: Phase difference, Overlap 1.5 states Pulse width 2.5 states Figure 10.46 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode Rev. 2.00 Mar. 15, 2006 Page 373 of 754 REJ09B0199-0200 Section 10 16-Bit Timer Pulse Unit (TPU) 10.10.3 Caution on Cycle Setting When counter clearing by compare match is set, TCNT is cleared in the final state in which it matches the TGR value (the point at which the count value matched by TCNT is updated). Consequently, the actual counter frequency is given by the following formula: f= f: P (N + 1) Counter frequency P: Operating frequency N: TGR set value 10.10.4 Conflict between TCNT Write and Clear Operations If the counter clearing signal is generated in the T2 state of a TCNT write cycle, TCNT clearing takes precedence and the TCNT write is not performed. Figure 10.47 shows the timing in this case. TCNT write cycle T2 T1 P Address Write Counter clear signal TCNT TCNT address N H'0000 Figure 10.47 Conflict between TCNT Write and Clear Operations Rev. 2.00 Mar. 15, 2006 Page 374 of 754 REJ09B0199-0200 Section 10 16-Bit Timer Pulse Unit (TPU) 10.10.5 Conflict between TCNT Write and Increment Operations If incrementing occurs in the T2 state of a TCNT write cycle, the TCNT write takes precedence and TCNT is not incremented. Figure 10.48 shows the timing in this case. TCNT write cycle T2 T1 P Address Write TCNT input clock TCNT N TCNT write data M TCNT address Figure 10.48 Conflict between TCNT Write and Increment Operations 10.10.6 Conflict between TGR Write and Compare Match If a compare match occurs in the T2 state of a TGR write cycle, the TGR write takes precedence and the compare match signal is disabled. A compare match also does not occur when the same value as before is written. Figure 10.49shows the timing in this case. TGR write cycle T2 T1 P Address Write Compare match signal TCNT TGR N N TGR write data Disabled N+1 M TGR address Figure 10.49 Conflict between TGR Write and Compare Match Rev. 2.00 Mar. 15, 2006 Page 375 of 754 REJ09B0199-0200 Section 10 16-Bit Timer Pulse Unit (TPU) 10.10.7 Conflict between Buffer Register Write and Compare Match If a compare match occurs in the T2 state of a TGR write cycle, the data transferred to TGR by the buffer operation will be the write data. Figure 10.50 shows the timing in this case. TGR write cycle T2 T1 P Address Write Compare match signal Buffer register TGR N Data written to buffer register Buffer register address M M Figure 10.50 Conflict between Buffer Register Write and Compare Match 10.10.8 Conflict between TGR Read and Input Capture If the input capture signal is generated in the T1 state of a TGR read cycle, the data that is read will be the data after input capture transfer. Figure 10.51 shows the timing in this case. TGR read cycle T1 T2 P Address Read Input capture signal TGR Internal data bus X M M TGR address Figure 10.51 Conflict between TGR Read and Input Capture Rev. 2.00 Mar. 15, 2006 Page 376 of 754 REJ09B0199-0200 Section 10 16-Bit Timer Pulse Unit (TPU) 10.10.9 Conflict between TGR Write and Input Capture If the input capture signal is generated in the T2 state of a TGR write cycle, the input capture operation takes precedence and the write to TGR is not performed. Figure 10.52 shows the timing in this case. TGR write cycle T2 T1 P Address Write Input capture signal TCNT TGR M M TGR address Figure 10.52 Conflict between TGR Write and Input Capture 10.10.10 Conflict between Buffer Register Write and Input Capture If the input capture signal is generated in the T2 state of a buffer register write cycle, the buffer operation takes precedence and the write to the buffer register is not performed. Figure 10.53 shows the timing in this case. Rev. 2.00 Mar. 15, 2006 Page 377 of 754 REJ09B0199-0200 Section 10 16-Bit Timer Pulse Unit (TPU) Buffer register write cycle T1 T2 P Address Write Input capture signal TCNT TGR Buffer register M N N M Buffer register address Figure 10.53 Conflict between Buffer Register Write and Input Capture 10.10.11 Conflict between Overflow/Underflow and Counter Clearing If overflow/underflow and counter clearing occur simultaneously, the TCFV/TCFU flag in TSR is not set and TCNT clearing takes precedence. Figure 10.54 shows the operation timing when a TGR compare match is specified as the clearing source, and H'FFFF is set in TGR. P TCNT input clock TCNT Counter clear signal TGF flag Disabled TCFV flag H'FFFF H'0000 Figure 10.54 Conflict between Overflow and Counter Clearing Rev. 2.00 Mar. 15, 2006 Page 378 of 754 REJ09B0199-0200 Section 10 16-Bit Timer Pulse Unit (TPU) 10.10.12 Conflict between TCNT Write and Overflow/Underflow If an overflow/underflow occurs due to increment/decrement in the T2 state of a TCNT write cycle, the TCNT write takes precedence and the TCFV/TCFU flag in TSR is not set. Figure 10.55 shows the operation timing when there is conflict between TCNT write and overflow. TGR write cycle T1 T2 P Address Write TCNT TCFV flag H'FFFF M TCNT address TCNT write data Figure 10.55 Conflict between TCNT Write and Overflow 10.10.13 Multiplexing of I/O Pins In this LSI, the TCLKA input pin is multiplexed with the TIOCC0 I/O pin, the TCLKB input pin with the TIOCD0 I/O pin, the TCLKC input pin with the TIOCB1 I/O pin, and the TCLKD input pin with the TIOCB2 I/O pin. When an external clock is input, compare match output should not be performed from a multiplexed pin. 10.10.14 Interrupts and Module Stop Mode If module stop mode is entered when an interrupt has been requested, it will not be possible to clear the CPU interrupt source, DMAC, or DTC activation source. Interrupts should therefore be disabled before entering module stop mode. Rev. 2.00 Mar. 15, 2006 Page 379 of 754 REJ09B0199-0200 Section 10 16-Bit Timer Pulse Unit (TPU) Rev. 2.00 Mar. 15, 2006 Page 380 of 754 REJ09B0199-0200 Section 11 Programmable Pulse Generator (PPG) Section 11 Programmable Pulse Generator (PPG) The programmable pulse generator (PPG) provides pulse outputs by using the 16-bit timer pulse unit (TPU) as a time base. The PPG pulse outputs are divided into 4-bit groups (groups 3 and 2) that can operate both simultaneously and independently. Figure 11.1 shows a block diagram of the PPG. 11.1 * * * * * * * Features 8-bit output data Two output groups Selectable output trigger signals Non-overlapping mode Can operate together with the data transfer controller (DTC) and DMA controller (DMAC) Inverted output can be set Module stop mode can be set Compare match signals NDERH Control logic PMR NDERL PCR PO15 PO14 PO13 PO12 PO11 PO10 PO9 PO8 Pulse output pins, group 3 PODRH Pulse output pins, group 2 Pulse output pins, group 1 PODRL Pulse output pins, group 0 NDRL NDRH Internal data bus [Legend] PMR: PPG output mode register PCR: PPG output control register NDERH: Next data enable register H NDERL: Next data enable register L NDRH: Next data register H NDRL: Next data register L PODRH:Output data register H PODRL: Output data register L Figure 11.1 Block Diagram of PPG Rev. 2.00 Mar. 15, 2006 Page 381 of 754 REJ09B0199-0200 Section 11 Programmable Pulse Generator (PPG) 11.2 Input/Output Pins Table 11.1 shows the PPG pin configuration. Table 11.1 Pin Configuration Pin Name PO15 PO14 PO13 PO12 PO11 PO10 PO9 PO8 I/O Output Output Output Output Output Output Output Output Group 2 pulse output Function Group 3 pulse output 11.3 Register Descriptions The PPG has the following registers. * * * * * * * * Next data enable register H (NDERH) Next data enable register L (NDERL) Output data register H (PODRH) Output data register L (PODRL) Next data register H (NDRH) Next data register L (NDRL) PPG output control register (PCR) PPG output mode register (PMR) Rev. 2.00 Mar. 15, 2006 Page 382 of 754 REJ09B0199-0200 Section 11 Programmable Pulse Generator (PPG) 11.3.1 Next Data Enable Registers H, L (NDERH, NDERL) NDERH and NDERL enable/disable pulse output on a bit-by-bit basis. * NDERH Bit Bit Name Initial Value R/W 7 NDER15 0 R/W 6 NDER14 0 R/W 5 NDER13 0 R/W 4 NDER12 0 R/W 3 NDER11 0 R/W 2 NDER10 0 R/W 1 NDER9 0 R/W 0 NDER8 0 R/W * NDERL Bit Bit Name Initial Value R/W 7 NDER7 0 R/W 6 NDER6 0 R/W 5 NDER5 0 R/W 4 NDER4 0 R/W 3 NDER3 0 R/W 2 NDER2 0 R/W 1 NDER1 0 R/W 0 NDER0 0 R/W * NDERH Bit 7 6 5 4 3 2 1 0 Bit Name NDER15 NDER14 NDER13 NDER12 NDER11 NDER10 NDER9 NDER8 Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Next Data Enable 15 to 8 When a bit is set to 1, the value in the corresponding NDRH bit is transferred to the PODRH bit by the selected output trigger. Values are not transferred from NDRH to PODRH for cleared bits. Rev. 2.00 Mar. 15, 2006 Page 383 of 754 REJ09B0199-0200 Section 11 Programmable Pulse Generator (PPG) * NDERL Bit 7 6 5 4 3 2 1 0 Bit Name NDER7 NDER6 NDER5 NDER4 NDER3 NDER2 NDER1 NDER0 Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Next Data Enable 7 to 0 When a bit is set to 1, the value in the corresponding NDRL bit is transferred to the PODRL bit by the selected output trigger. Values are not transferred from NDRL to PODRL for cleared bits. 11.3.2 Output Data Registers H, L (PODRH, PODRL) PODRH and PODRL store output data for use in pulse output. A bit that has been set for pulse output by NDER is read-only and cannot be modified. * PODRH Bit Bit Name Initial Value R/W 7 POD15 0 R/W 6 POD14 0 R/W 5 POD13 0 R/W 4 POD12 0 R/W 3 POD11 0 R/W 2 POD10 0 R/W 1 POD9 0 R/W 0 POD8 0 R/W * PODRL Bit Bit Name Initial Value R/W 7 POD7 0 R/W 6 POD6 0 R/W 5 POD5 0 R/W 4 POD4 0 R/W 3 POD3 0 R/W 2 POD2 0 R/W 1 POD1 0 R/W 0 POD0 0 R/W Rev. 2.00 Mar. 15, 2006 Page 384 of 754 REJ09B0199-0200 Section 11 Programmable Pulse Generator (PPG) * PODRH Bit 7 6 5 4 3 2 1 0 Bit Name POD15 POD14 POD13 POD12 POD11 POD10 POD9 POD8 Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Output Data Register 15 to 8 For bits which have been set to pulse output by NDERH, the output trigger transfers NDRH values to this register during PPG operation. While NDERH is set to 1, the CPU cannot write to this register. While NDERH is cleared, the initial output value of the pulse can be set. * PODRL Bit 7 6 5 4 3 2 1 0 Bit Name POD7 POD6 POD5 POD4 POD3 POD2 POD1 POD0 Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Output Data Register 7 to 0 For bits which have been set to pulse output by NDERL, the output trigger transfers NDRL values to this register during PPG operation. While NDERL is set to 1, the CPU cannot write to this register. While NDERL is cleared, the initial output value of the pulse can be set. Rev. 2.00 Mar. 15, 2006 Page 385 of 754 REJ09B0199-0200 Section 11 Programmable Pulse Generator (PPG) 11.3.3 Next Data Registers H, L (NDRH, NDRL) NDRH and NDRL store the next data for pulse output. The NDR addresses differ depending on whether pulse output groups have the same output trigger or different output triggers. * NDRH Bit Bit Name Initial Value R/W 7 NDR15 0 R/W 6 NDR14 0 R/W 5 NDR13 0 R/W 4 NDR12 0 R/W 3 NDR11 0 R/W 2 NDR10 0 R/W 1 NDR9 0 R/W 0 NDR8 0 R/W * NDRL Bit Bit Name Initial Value R/W 7 NDR7 0 R/W 6 NDR6 0 R/W 5 NDR5 0 R/W 4 NDR4 0 R/W 3 NDR3 0 R/W 2 NDR2 0 R/W 1 NDR1 0 R/W 0 NDR0 0 R/W * NDRH If pulse output groups 2 and 3 have the same output trigger, all eight bits are mapped to the same address and can be accessed at one time, as shown below. Bit 7 6 5 4 3 2 1 0 Bit Name NDR15 NDR14 NDR13 NDR12 NDR11 NDR10 NDR9 NDR8 Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Next Data Register 15 to 8 The register contents are transferred to the corresponding PODRH bits by the output trigger specified with PCR. Rev. 2.00 Mar. 15, 2006 Page 386 of 754 REJ09B0199-0200 Section 11 Programmable Pulse Generator (PPG) If pulse output groups 2 and 3 have different output triggers, the upper four bits and lower four bits are mapped to different addresses as shown below. Bit 7 6 5 4 3 to 0 Bit Name NDR15 NDR14 NDR13 NDR12 Initial Value 0 0 0 0 All 1 R/W R/W R/W R/W R/W R Description Next Data Register 15 to 12 The register contents are transferred to the corresponding PODRH bits by the output trigger specified with PCR. Reserved These are read-only bits and cannot be modified. Initial Value All 1 0 0 0 0 Bit 7 to 4 3 2 1 0 Bit Name NDR11 NDR10 NDR9 NDR8 R/W R R/W R/W R/W R/W Description Reserved These are read-only bits and cannot be modified. Next Data Register 11 to 8 The register contents are transferred to the corresponding PODRH bits by the output trigger specified with PCR. * NDRL If pulse output groups 0 and 1 have the same output trigger, all eight bits are mapped to the same address and can be accessed at one time, as shown below. Bit 7 6 5 4 3 2 1 0 Bit Name NDR7 NDR6 NDR5 NDR4 NDR3 NDR2 NDR1 NDR0 Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Next Data Register 7 to 0 The register contents are transferred to the corresponding PODRL bits by the output trigger specified with PCR. Rev. 2.00 Mar. 15, 2006 Page 387 of 754 REJ09B0199-0200 Section 11 Programmable Pulse Generator (PPG) If pulse output groups 0 and 1 have different output triggers, the upper four bits and lower four bits are mapped to different addresses as shown below. Bit 7 6 5 4 3 to 0 Bit Name NDR7 NDR6 NDR5 NDR4 Initial Value 0 0 0 0 All 1 R/W R/W R/W R/W R/W R Description Next Data Register 7 to 4 The register contents are transferred to the corresponding PODRL bits by the output trigger specified with PCR. Reserved These are read-only bits and cannot be modified. Bit 7 to 4 3 2 1 0 Bit Name NDR3 NDR2 NDR1 NDR0 Initial Value All 1 0 0 0 0 R/W R R/W R/W R/W R/W Description Reserved These are read-only bits and cannot be modified. Next Data Register 3 to 0 The register contents are transferred to the corresponding PODRL bits by the output trigger specified with PCR. Rev. 2.00 Mar. 15, 2006 Page 388 of 754 REJ09B0199-0200 Section 11 Programmable Pulse Generator (PPG) 11.3.4 PPG Output Control Register (PCR) PCR selects output trigger signals on a group-by-group basis. For details on output trigger selection, refer to section 11.3.5, PPG Output Mode Register (PMR). Bit Bit Name Initial Value R/W 7 G3CMS1 1 R/W 6 G3CMS0 1 R/W 5 G2CMS1 1 R/W 4 G2CMS0 1 R/W 3 -- 1 R/W 2 -- 1 R/W 1 -- 1 R/W 0 -- 1 R/W Bit 7 6 Bit Name G3CMS1 G3CMS0 Initial Value 1 1 R/W R/W R/W Description Group 3 Compare Match Select 1 and 0 These bits select output trigger of pulse output group 3. 00: Compare match in TPU channel 0 01: Compare match in TPU channel 1 10: Compare match in TPU channel 2 11: Compare match in TPU channel 3 5 4 G2CMS1 G2CMS0 1 1 R/W R/W Group 2 Compare Match Select 1 and 0 These bits select output trigger of pulse output group 2. 00: Compare match in TPU channel 0 01: Compare match in TPU channel 1 10: Compare match in TPU channel 2 11: Compare match in TPU channel 3 3 to 0 All 1 R/W Reserved These bits are always read as 1. The write value should always be 1. Rev. 2.00 Mar. 15, 2006 Page 389 of 754 REJ09B0199-0200 Section 11 Programmable Pulse Generator (PPG) 11.3.5 PPG Output Mode Register (PMR) PMR selects the pulse output mode of the PPG for each group. If inverted output is selected, a low-level pulse is output when PODRH is 1 and a high-level pulse is output when PODRH is 0. If non-overlapping operation is selected, PPG updates its output values at compare match A or B of the TPU that becomes the output trigger. For details, refer to section 11.4.4, Non-Overlapping Pulse Output. Bit Bit Name Initial Value R/W 7 G3INV 1 R/W 6 G2INV 1 R/W 5 -- 1 R/W 4 -- 1 R/W 3 G3NOV 0 R/W 2 G2NOV 0 R/W 1 -- 0 R/W 0 -- 0 R/W Bit 7 Bit Name G3INV Initial Value 1 R/W R/W Description Group 3 Inversion Selects direct output or inverted output for pulse output group 3. 0: Inverted output 1: Direct output 6 G2INV 1 R/W Group 2 Inversion Selects direct output or inverted output for pulse output group 2. 0: Inverted output 1: Direct output 5, 4 All 1 R/W Reserved These bits are always read as 1. The write value should always be 1. 3 G3NOV 0 R/W Group 3 Non-Overlap Selects normal or non-overlapping operation for pulse output group 3. 0: Normal operation (output values updated at compare match A in the selected TPU channel) 1: Non-overlapping operation (output values updated at compare match A or B in the selected TPU channel) Rev. 2.00 Mar. 15, 2006 Page 390 of 754 REJ09B0199-0200 Section 11 Programmable Pulse Generator (PPG) Bit 2 Bit Name G2NOV Initial Value 0 R/W R/W Description Group 2 Non-Overlap Selects normal or non-overlapping operation for pulse output group 2. 0: Normal operation (output values updated at compare match A in the selected TPU channel) 1: Non-overlapping operation (output values updated at compare match A or B in the selected TPU channel) 1, 0 All 0 R/W Reserved These bits are always read as 0. The write value should always be 0. 11.4 Operation Figure 11.2 shows a schematic diagram of the PPG. PPG pulse output is enabled when the corresponding bits in NDER are set to 1. An initial output value is determined by its corresponding PODR initial setting. When the compare match event specified by PCR occurs, the corresponding NDR bit contents are transferred to PODR to update the output values. Sequential output of data of up to eight bits is possible by writing new output data to NDR before the next compare match. NDER Q Output trigger signal C Q PODR D Pulse output pin Normal output/inverted output Q NDR D Internal data bus Figure 11.2 Schematic Diagram of PPG Rev. 2.00 Mar. 15, 2006 Page 391 of 754 REJ09B0199-0200 Section 11 Programmable Pulse Generator (PPG) 11.4.1 Output Timing If pulse output is enabled, the NDR contents are transferred to PODR and output when the specified compare match event occurs. Figure 11.3 shows the timing of these operations for the case of normal output in groups 2 and 3, triggered by compare match A. P TCNT TGRA Compare match A signal NDRH N N+1 N n PODRH m n PO8 to PO15 m n Figure 11.3 Timing of Transfer and Output of NDR Contents (Example) Rev. 2.00 Mar. 15, 2006 Page 392 of 754 REJ09B0199-0200 Section 11 Programmable Pulse Generator (PPG) 11.4.2 Sample Setup Procedure for Normal Pulse Output Figure 11.4 shows a sample procedure for setting up normal pulse output. [1] [2] [3] Set TGRA value TPU setup Set counting operation Select interrupt request Set initial output data Enable pulse output PPG setup Select output trigger Set next pulse output data TPU setup Start counter Compare match? Yes Set next pulse output data [10] [7] [3] [4] [4] [5] [6] [5] [6] [7] [8] [9] [9] No [2] Set TIOR to make TGRA an output compare register (with output disabled). Set the PPG output trigger cycle. Select the counter clock source with bits TPSC2 to TPSC0 in TCR. Select the counter clear source with bits CCLR1 and CCLR0. Enable the TGIA interrupt in TIER. The DTC or DMAC can also be set up to transfer data to NDR. Set the initial output values in PODR. Set the bits in NDER for the pins to be used for pulse output to 1. Select the TPU compare match event to be used as the output trigger in PCR. Set the next pulse output values in NDR. Set the CST bit in TSTR to 1 to start the TCNT counter. Normal PPG output Select TGR functions [1] [8] [10] At each TGIA interrupt, set the next output values in NDR. Figure 11.4 Setup Procedure for Normal Pulse Output (Example) Rev. 2.00 Mar. 15, 2006 Page 393 of 754 REJ09B0199-0200 Section 11 Programmable Pulse Generator (PPG) 11.4.3 Example of Normal Pulse Output (Example of 5-Phase Pulse Output) Figure 11.5 shows an example in which pulse output is used for cyclic 5-phase pulse output. TCNT value TGRA Compare match TCNT H'0000 NDRH 80 C0 40 60 20 30 10 18 08 88 80 C0 40 Time PODRH 00 80 C0 40 60 20 30 10 18 08 88 80 C0 PO15 PO14 PO13 PO12 PO11 Figure 11.5 Normal Pulse Output Example (5-Phase Pulse Output) 1. Set up TGRA in TPU which is used as the output trigger to be an output compare register. Set a cycle in TGRA so the counter will be cleared by compare match A. Set the TGIEA bit in TIER to 1 to enable the compare match/input capture A (TGIA) interrupt. 2. Write H'F8 to NDERH, and set bits G3CMS1, G3CMS0, G2CMS1, and G2CMS0 in PCR to select compare match in the TPU channel set up in the previous step to be the output trigger. Write output data H'80 in NDRH. 3. The timer counter in the TPU channel starts. When compare match A occurs, the NDRH contents are transferred to PODRH and output. The TGIA interrupt handling routine writes the next output data (H'C0) in NDRH. 4. 5-phase pulse output (one or two phases active at a time) can be obtained subsequently by writing H'40, H'60, H'20, H'30, H'10, H'18, H'08, H'88... at successive TGIA interrupts. If the DTC or DMAC is set for activation by the TGIA interrupt, pulse output can be obtained without imposing a load on the CPU. Rev. 2.00 Mar. 15, 2006 Page 394 of 754 REJ09B0199-0200 Section 11 Programmable Pulse Generator (PPG) 11.4.4 Non-Overlapping Pulse Output During non-overlapping operation, transfer from NDR to PODR is performed as follows: * At compare match A, the NDR bits are always transferred to PODR. * At compare match B, the NDR bits are transferred only if their value is 0. The NDR bits are not transferred if their value is 1. Figure 11.6 illustrates the non-overlapping pulse output operation. NDER Q Compare match A Compare match B Pulse output pin C Q PODR D Q NDR D Internal data bus Normal output/inverted output Figure 11.6 Non-Overlapping Pulse Output Therefore, 0 data can be transferred ahead of 1 data by making compare match B occur before compare match A. The NDR contents should not be altered during the interval from compare match B to compare match A (the non-overlapping margin). This can be accomplished by having the TGIA interrupt handling routine write the next data in NDR, or by having the TGIA interrupt activate the DTC or DMAC. Note, however, that the next data must be written before the next compare match B occurs. Rev. 2.00 Mar. 15, 2006 Page 395 of 754 REJ09B0199-0200 Section 11 Programmable Pulse Generator (PPG) Figure 11.7 shows the timing of this operation. Compare match A Compare match B Write to NDR NDR Write to NDR PODR 0 output 0/1 output 0 output 0/1 output Write to NDR here Write to NDR Do not write here to NDR here Do not write to NDR here Figure 11.7 Non-Overlapping Operation and NDR Write Timing Rev. 2.00 Mar. 15, 2006 Page 396 of 754 REJ09B0199-0200 Section 11 Programmable Pulse Generator (PPG) 11.4.5 Sample Setup Procedure for Non-Overlapping Pulse Output Figure 11.8 shows a sample procedure for setting up non-overlapping pulse output. Non-overlapping pulse output Select TGR functions Set TGR values TPU setup Set counting operation Select interrupt request Set initial output data Enable pulse output Select output trigger Set non-overlapping groups Set next pulse output data TPU setup Start counter Compare match A? Yes Set next pulse output data [11] [3] [4] [4] [5] [6] [7] [8] [7] [5] [6] PPG setup [1] [2] [3] [1] Set TIOR to make TGRA and TGRB output compare registers (with output disabled). Set the pulse output trigger cycle in TGRB and the non-overlapping margin in TGRA. Select the counter clock source with bits TPSC2 to TPSC0 in TCR. Select the counter clear source with bits CCLR1 and CCLR0. Enable the TGIA interrupt in TIER. The DTC or DMAC can also be set up to transfer data to NDR. Set the initial output values in PODR. Set the bits in NDER for the pins to be used for pulse output to 1. Select the TPU compare match event to be used as the pulse output trigger in PCR. In PMR, select the groups that will operate in non-overlapping mode. Set the next pulse output values in NDR. [2] [9] [8] [9] [10] No [10] Set the CST bit in TSTR to 1 to start the TCNT counter. [11] At each TGIA interrupt, set the next output values in NDR. Figure 11.8 Setup Procedure for Non-Overlapping Pulse Output (Example) Rev. 2.00 Mar. 15, 2006 Page 397 of 754 REJ09B0199-0200 Section 11 Programmable Pulse Generator (PPG) 11.4.6 Example of Non-Overlapping Pulse Output (Example of 4-Phase Complementary Non-Overlapping Pulse Output) Figure 11.9 shows an example in which pulse output is used for 4-phase complementary nonoverlapping pulse output. TCNT value TGRB TCNT TGRA H'0000 NDRH 95 65 59 56 95 65 Time PODRH 00 95 05 65 41 59 50 56 14 95 05 65 Non-overlapping margin PO15 PO14 PO13 PO12 PO11 PO10 PO9 PO8 Figure 11.9 Non-Overlapping Pulse Output Example (4-Phase Complementary) Rev. 2.00 Mar. 15, 2006 Page 398 of 754 REJ09B0199-0200 Section 11 Programmable Pulse Generator (PPG) 1. Set up the TPU channel to be used as the output trigger channel so that TGRA and TGRB are output compare registers. Set the cycle in TGRB and the non-overlapping margin in TGRA, and set the counter to be cleared by compare match B. Set the TGIEA bit in TIER to 1 to enable the TGIA interrupt. 2. Write H'FF to NDERH, and set bits G3CMS1, G3CMS0, G2CMS1, and G2CMS0 in PCR to select compare match in the TPU channel set up in the previous step to be the output trigger. Set bits G3NOV and G2NOV in PMR to 1 to select non-overlapping pulse output. Write output data H'95 to NDRH. 3. The timer counter in the TPU channel starts. When a compare match with TGRB occurs, outputs change from 1 to 0. When a compare match with TGRA occurs, outputs change from 0 to 1 (the change from 0 to 1 is delayed by the value set in TGRA). The TGIA interrupt handling routine writes the next output data (H'65) to NDRH. 4. 4-phase complementary non-overlapping pulse output can be obtained subsequently by writing H'59, H'56, H'95... at successive TGIA interrupts. If the DTC or DMAC is set for activation by a TGIA interrupt, pulse can be output without imposing a load on the CPU. Rev. 2.00 Mar. 15, 2006 Page 399 of 754 REJ09B0199-0200 Section 11 Programmable Pulse Generator (PPG) 11.4.7 Inverted Pulse Output If the G3INV and G2INV bits in PMR are cleared to 0, values that are the inverse of the PODR contents can be output. Figure 11.10 shows the outputs when the G3INV and G2INV bits are cleared to 0, in addition to the settings of figure 11.9. TCNT value TGRB TCNT TGRA H'0000 NDRH 95 65 59 56 95 65 Time PODRH 00 95 05 65 41 59 50 56 14 95 05 65 PO15 PO14 PO13 PO12 PO11 PO10 PO9 PO8 Figure 11.10 Inverted Pulse Output (Example) Rev. 2.00 Mar. 15, 2006 Page 400 of 754 REJ09B0199-0200 Section 11 Programmable Pulse Generator (PPG) 11.4.8 Pulse Output Triggered by Input Capture Pulse output can be triggered by TPU input capture as well as by compare match. If TGRA functions as an input capture register in the TPU channel selected by PCR, pulse output will be triggered by the input capture signal. Figure 11.11 shows the timing of this output. P TIOC pin Input capture signal NDR N PODR M N PO M N Figure 11.11 Pulse Output Triggered by Input Capture (Example) Rev. 2.00 Mar. 15, 2006 Page 401 of 754 REJ09B0199-0200 Section 11 Programmable Pulse Generator (PPG) 11.5 11.5.1 Usage Notes Module Stop Mode Setting PPG operation can be disabled or enabled using the module stop control register. The initial value is for PPG operation to be halted. Register access is enabled by clearing module stop mode. For details, refer to section 19, Power-Down Modes. 11.5.2 Operation of Pulse Output Pins Pins PO0 to PO8 are also used for other peripheral functions such as the TPU. When output by another peripheral function is enabled, the corresponding pins cannot be used for pulse output. Note, however, that data transfer from NDR bits to PODR bits takes place, regardless of the usage of the pins. Pin functions should be changed only under conditions in which the output trigger event will not occur. Rev. 2.00 Mar. 15, 2006 Page 402 of 754 REJ09B0199-0200 Section 12 Watchdog Timer (WDT) Section 12 Watchdog Timer (WDT) The watchdog timer (WDT) is an 8-bit timer that outputs an internal reset signal if a system crash prevents the CPU from writing to the timer counter, thus allowing it to overflow. When this watchdog function is not needed, the WDT can be used as an interval timer. In interval timer operation, an interval timer interrupt is generated each time the counter overflows. Figure 12.1 shows a block diagram of the WDT. 12.1 Features * Selectable from eight counter input clocks * Switchable between watchdog timer mode and interval timer mode In watchdog timer mode If the counter overflows, this LSI can be initialized internally. In interval timer mode If the counter overflows, the WDT generates an interval timer interrupt (WOVI). Overflow WOVI (interrupt request signal) Interrupt control Clock Clock select Internal reset signal* Reset control P/2 P/64 P/128 P/512 P/2048 P/8192 P/32768 P/131072 Internal clocks RSTCSR TCNT TCSR Bus interface Module bus WDT [Legend] Timer control/status register TCSR: Timer counter TCNT: RSTCSR: Reset control/status register Note: * An internal reset signal can be generated by the register setting. Figure 12.1 Block Diagram of WDT Rev. 2.00 Mar. 15, 2006 Page 403 of 754 REJ09B0199-0200 Internal bus Section 12 Watchdog Timer (WDT) 12.2 Register Descriptions The WDT has the following three registers. To prevent accidental overwriting, TCSR, TCNT, and RSTCSR have to be written to in a method different from normal registers. For details, see section 12.5.1, Notes on Register Access. * Timer counter (TCNT) * Timer control/status register (TCSR) * Reset control/status register (RSTCSR) 12.2.1 Timer Counter (TCNT) TCNT is an 8-bit readable/writable up-counter. TCNT is initialized to H'00 when the TME bit in TCSR is cleared to 0. Bit Bit Name Initial Value R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 7 6 5 4 3 2 1 0 12.2.2 Timer Control/Status Register (TCSR) TCSR selects the clock source to be input to TCNT, and the timer mode. Bit Bit Name Initial Value R/W 7 OVF 0 R/(W)* 6 WT/IT 0 R/W 5 TME 0 R/W 4 -- 1 R 3 -- 1 R 2 CKS2 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W Note: * Only 0 can be written to this bit, to clear the flag. Rev. 2.00 Mar. 15, 2006 Page 404 of 754 REJ09B0199-0200 Section 12 Watchdog Timer (WDT) Bit 7 Bit Name OVF Initial Value 0 R/W Description R/(W)* Overflow Flag Indicates that TCNT has overflowed in interval timer mode. Only 0 can be written to this bit, to clear the flag. [Setting condition] * * When TCNT overflows in interval timer mode (changes from H'FF to H'00) When internal reset request generation is selected in watchdog timer mode, OVF is cleared automatically by the internal reset. Cleared by reading TCSR when OVF = 1, then writing 0 to OVF (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) [Clearing condition] * 6 WT/IT 0 R/W Timer Mode Select Selects whether the WDT is used as a watchdog timer or interval timer. 0: Interval timer mode When TCNT overflows, an interval timer interrupt (WOVI) is requested. 1: Watchdog timer mode When TCNT overflows while RSTE = 1, this LSI is initialized initially. 5 TME 0 R/W Timer Enable When this bit is set to 1, TCNT starts counting. When this bit is cleared, TCNT stops counting and is initialized to H'00. 4, 3 All 1 R Reserved These are read-only bits and cannot be modified. Rev. 2.00 Mar. 15, 2006 Page 405 of 754 REJ09B0199-0200 Section 12 Watchdog Timer (WDT) Bit 2 1 0 Bit Name CKS2 CKS1 CKS0 Initial Value 0 0 0 R/W R/W R/W R/W Description Clock Select 2 to 0 Select the clock source to be input to TCNT. The overflow cycle for P = 20 MHz is indicated in parentheses. Note: * 000: Clock P/2 (cycle: 25.6 s) 001: Clock P/64 (cycle: 819.2 s) 010: Clock P/128 (cycle: 1.6 ms) 011: Clock P/512 (cycle: 6.6 ms) 100: Clock P/2048 (cycle: 26.2 ms) 101: Clock P/8192 (cycle: 104.9 ms) 110: Clock P/32768 (cycle: 419.4 ms) 111: Clock P/131072 (cycle: 1.68 s) Only 0 can be written to this bit, to clear the flag. 12.2.3 Reset Control/Status Register (RSTCSR) RSTCSR controls the generation of the internal reset signal when TCNT overflows, and selects the type of internal reset signal. RSTCSR is initialized to H'1F by a reset signal from the RES pin, but not by the WDT internal reset signal caused by WDT overflows. Bit Bit Name Initial Value R/W 7 WOVF 0 R/(W)* 6 RSTE 0 R/W 5 -- 0 R/W 4 -- 1 R 3 -- 1 R 2 -- 1 R 1 -- 1 R 0 -- 1 R Note: * Only 0 can be written to this bit, to clear the flag. Rev. 2.00 Mar. 15, 2006 Page 406 of 754 REJ09B0199-0200 Section 12 Watchdog Timer (WDT) Bit 7 Bit Name WOVF Initial Value 0 R/W Description R/(W)* Watchdog Timer Overflow Flag This bit is set when TCNT overflows in watchdog timer mode. This bit cannot be set in interval timer mode, and only 0 can be written. [Setting condition] * When TCNT overflows (changed from H'FF to H'00) in watchdog timer mode Reading RSTCSR when WOVF = 1, and then writing 0 to WOVF [Clearing condition] * 6 RSTE 0 R/W Reset Enable Specifies whether or not this LSI is internally reset if TCNT overflows during watchdog timer operation. 0: LSI is not reset even if TCNT overflows (Though this LSI is not reset, TCNT and TCSR in WDT are reset) 1: LSI is reset if TCNT overflows 5 0 R/W Reserved This bit is always read as 0. The write value should always be 0. 4 to 0 Note: * All 1 R Reserved These are read-only bits and cannot be modified. Only 0 can be written to this bit to clear the flag. Rev. 2.00 Mar. 15, 2006 Page 407 of 754 REJ09B0199-0200 Section 12 Watchdog Timer (WDT) 12.3 12.3.1 Operation Watchdog Timer Mode To use the WDT in watchdog timer mode, set both the WT/IT and TME bits in TCSR to 1. When TCNT overflows in watchdog timer mode, the WOVF bit in RSTCSR is set to 1. When the watchdog timer mode is selected and the RSTE bit in RSTCSR is set to 1, if TCNT overflows without being rewritten because of a system crash or other error, this LSI is initialized internally. This ensures that TCNT does not overflow while the system is operating normally. Software must prevent TCNT overflows by rewriting the TCNT value (normally H'00 is written) before overflow occurs. If a reset caused by a signal input to the RES pin occurs at the same time as a reset caused by a WDT overflow (TCNT has overflowed), the RES pin reset has priority and the WOVF bit in RSTCSR is cleared to 0. The internal reset signal is output for 519 cycles of P. When RSTE = 1, a signal to initialize this LSI internally is generated. Since this signal initializes the system click control register (SCKCR), the multiplication ratio of P clock is also initialized. When RSTE = 0, the signal is not generated, meaning that the SCKCR value and multiplication ratio of P clock remain unchanged. TCNT value Overflow H'FF H'00 WT/IT = 1 TME = 1 Internal reset signal* 519 cycles Notes: * Time H'00 written to TCNT WOVF = 1 WT/IT = 1 H'00 written TME = 1 to TCNT If TCNT overflows when the RSTE bit is set to 1, an internal reset signal is generated. Figure 12.2 Operation in Watchdog Timer Mode Rev. 2.00 Mar. 15, 2006 Page 408 of 754 REJ09B0199-0200 Section 12 Watchdog Timer (WDT) 12.3.2 Interval Timer Mode To use the WDT as an interval timer, set the WT/IT bit to 0 and the TME bit to 1 in TCSR. When the WDT is used as an interval timer, an interval timer interrupt (WOVI) is generated each time the TCNT overflows. Therefore, an interrupt can be generated at intervals. When the TCNT overflows in interval timer mode, an interval timer interrupt (WOVI) is requested at the same time the OVF bit in the TCSR is set to 1. TCNT value H'FF Overflow Overflow Overflow Overflow H'00 WT/IT = 0 TME = 1 WOVI WOVI WOVI WOVI Time WOVI: Interval timer interrupt request Figure 12.3 Operation in Interval Timer Mode 12.4 Interrupt Source During interval timer mode operation, an overflow generates an interval timer interrupt (WOVI). The interval timer interrupt is requested whenever the OVF flag is set to 1 in TCSR. The OVF flag must be cleared to 0 in the interrupt handling routine. Table 12.1 WDT Interrupt Source Name WOVI Interrupt Source TCNT overflow Interrupt Flag OVF DTC Activation Impossible DMAC Activation Impossible Rev. 2.00 Mar. 15, 2006 Page 409 of 754 REJ09B0199-0200 Section 12 Watchdog Timer (WDT) 12.5 12.5.1 Usage Notes Notes on Register Access The watchdog timer's TCNT, TCSR, and RSTCSR registers differ from other registers in being more difficult to write to. The procedures for writing to and reading these registers are given below. (1) Writing to TCNT, TCSR, and RSTCSR TCNT and TCSR must be written to by a word transfer instruction. They cannot be written to by a byte transfer instruction. For writing, TCNT and TCSR are assigned to the same address. Accordingly, perform data transfer as shown in figure 12.4. The transfer instruction writes the lower byte data to TCNT or TCSR. To write to RSTCSR, execute a word transfer instruction for address H'FFA6. A byte transfer instruction cannot be used to write to RSTCSR. The method of writing 0 to the WOVF bit in RSTCSR differs from that of writing to the RSTE bit in RSTCSR. Perform data transfer as shown in figure 12.4. At data transfer, the transfer instruction clears the WOVF bit to 0, but has no effect on the RSTE bit. To write to the RSTE bit, perform data transfer as shown in figure 12.4. In this case, the transfer instruction writes the value in bit 6 of the lower byte to the RSTE bit, but has no effect on the WOVF bit. TCNT write or writing to the RSTE bit in RSTCSR: 15 Address: H'FFA4 (TCNT) H'FFA6 (RSTCSR) 8 H'5A 7 Write data 0 TCSR write: Address: H'FFA4 (TCSR) 15 H'A5 8 7 Write data 0 Writing 0 to the WOVF bit in RSTCSR: 15 Address: H'FFA6 (RSTCSR) 8 H'A5 7 H'00 0 Figure 12.4 Writing to TCNT, TCSR, and RSTCSR Rev. 2.00 Mar. 15, 2006 Page 410 of 754 REJ09B0199-0200 Section 12 Watchdog Timer (WDT) (2) Reading from TCNT, TCSR, and RSTCSR These registers can be read from in the same way as other registers. For reading, TCSR is assigned to address H'FFA4, TCNT to address H'FFA5, and RSTCSR to address H'FFA7. 12.5.2 Conflict between Timer Counter (TCNT) Write and Increment If a TCNT clock pulse is generated during the T2 state of a TCNT write cycle, the write takes priority and the timer counter is not incremented. Figure 12.5 shows this operation. TCNT write cycle T1 T2 P Address Internal write signal TCNT input clock TCNT N Counter write data M Figure 12.5 Conflict between TCNT Write and Increment 12.5.3 Changing Values of Bits CKS2 to CKS0 If bits CKS2 to CKS0 in TCSR are written to while the WDT is operating, errors could occur in the incrementation. The watchdog timer must be stopped (by clearing the TME bit to 0) before the values of bits CKS2 to CKS0 are changed. 12.5.4 Switching between Watchdog Timer Mode and Interval Timer Mode If the timer mode is switched from watchdog timer mode to interval timer mode while the WDT is operating, errors could occur in the incrementation. The watchdog timer must be stopped (by clearing the TME bit to 0) before switching the timer mode. Rev. 2.00 Mar. 15, 2006 Page 411 of 754 REJ09B0199-0200 Section 12 Watchdog Timer (WDT) 12.5.5 Transition to Watchdog Timer Mode or Software Standby Mode When the WDT operates in watchdog timer mode, a transition to software standby mode is not made even when the SLEEP instruction is executed when the SSBY bit in SBYCR is set to 1. Instead, a transition to sleep mode is made. To transit to software standby mode, the SLEEP instruction must be executed after halting the WDT (clearing the TME bit to 0). When the WDT operates in interval timer mode, a transition to software standby mode is made through execution of the SLEEP instruction when the SSBY bit in SBYCR is set to 1. Rev. 2.00 Mar. 15, 2006 Page 412 of 754 REJ09B0199-0200 Section 13 Serial Communication Interface (SCI) Section 13 Serial Communication Interface (SCI) This LSI has two independent serial communication interface (SCI) channels. The SCI can handle both asynchronous and clocked synchronous serial communication. Asynchronous serial data communication can be carried out with standard asynchronous communication chips such as a Universal Asynchronous Receiver/Transmitter (UART) or Asynchronous Communication Interface Adapter (ACIA). A function is also provided for serial communication between processors (multiprocessor communication function). The SCI also supports the smart card (IC card) interface conforming to ISO/IEC 7816-3 (Identification Card) as an extended asynchronous communication mode. Figure 13.1 shows a block diagram of the SCI. 13.1 Features * Choice of asynchronous or clocked synchronous serial communication mode * Full-duplex communication capability The transmitter and receiver are mutually independent, enabling transmission and reception to be executed simultaneously. Double-buffering is used in both the transmitter and the receiver, enabling continuous transmission and continuous reception of serial data. * On-chip baud rate generator allows any bit rate to be selected The external clock can be selected as a transfer clock source (except for the smart card interface). * Choice of LSB-first or MSB-first transfer (except in the case of asynchronous mode 7-bit data) * Four interrupt sources The interrupt sources are transmit-end, transmit-data-empty, receive-data-full, and receive error. The transmit-data-empty and receive-data-full interrupt sources can activate the DTC or DMAC. * Module stop mode can be set Asynchronous Mode: * * * * * Data length: 7 or 8 bits Stop bit length: 1 or 2 bits Parity: Even, odd, or none Receive error detection: Parity, overrun, and framing errors Break detection: Break can be detected by reading the RxD pin level directly in case of a framing error Rev. 2.00 Mar. 15, 2006 Page 413 of 754 REJ09B0199-0200 Section 13 Serial Communication Interface (SCI) Clocked Synchronous Mode: * Data length: 8 bits * Receive error detection: Overrun errors Smart Card Interface: * An error signal can be automatically transmitted on detection of a parity error during reception * Data can be automatically re-transmitted on receiving an error signal during transmission * Both direct convention and inverse convention are supported Module data bus RDR TDR SCMR SSR SCR BRR P Baud rate generator P/4 P/16 RxD RSR TSR SMR Transmission/ reception control P/64 Clock TxD Parity check SCK Parity generation External clock TEI TXI RXI ERI SCR: SSR: SCMR: BRR: Serial control register Serial status register Smart card mode register Bit rate register [Legend] RSR: Receive shift register RDR: Receive data register TSR: Transmit shift register TDR: Transmit data register SMR: Serial mode register Figure 13.1 Block Diagram of SCI Rev. 2.00 Mar. 15, 2006 Page 414 of 754 REJ09B0199-0200 Internal data bus Bus interface Section 13 Serial Communication Interface (SCI) 13.2 Input/Output Pins Table 13.1 lists the pin configuration of the SCI. Table 13.1 Pin Configuration Channel 3 Pin Name* SCK3 RxD3 TxD3 4 SCK4 RxD4 TxD4 Note: * I/O I/O Input Output I/O Input Output Function Channel 3 clock input/output Channel 3 receive data input Channel 3 transmit data output Channel 4 clock input/output Channel 4 receive data input Channel 4 transmit data output Pin names SCK, RxD, and TxD are used in the text for all channels, omitting the channel designation. 13.3 Register Descriptions The SCI has the following registers. Some bits in the serial mode register (SMR), serial status register (SSR), and serial control register (SCR) have different functions in different modes: Normal serial communication interface mode and smart card interface mode. The bits, therefore, are described separately for each mode in the corresponding register sections. Channel 3: * * * * * * * * * Receive shift register_3 (RSR_3) Transmit shift register_3 (TSR_3) Receive data register_3 (RDR_3) Transmit data register_3 (TDR_3) Serial mode register_3 (SMR_3) Serial control register_3 (SCR_3) Serial status register_3 (SSR_3) Smart card mode register_3 (SCMR_3) Bit rate register_3 (BRR_3) Rev. 2.00 Mar. 15, 2006 Page 415 of 754 REJ09B0199-0200 Section 13 Serial Communication Interface (SCI) Channel 4: * * * * * * * * * Receive shift register_4 (RSR_4) Transmit shift register_4 (TSR_4) Receive data register_4 (RDR_4) Transmit data register_4 (TDR_4) Serial mode register_4 (SMR_4) Serial control register_4 (SCR_4) Serial status register_4 (SSR_4) Smart card mode register_4 (SCMR_4) Bit rate register_4 (BRR_4) Receive Shift Register (RSR) 13.3.1 RSR is a shift register which is used to receive serial data input from the RxD pin and converts it into parallel data. When one frame of data has been received, it is transferred to RDR automatically. RSR cannot be directly accessed by the CPU. 13.3.2 Receive Data Register (RDR) RDR is an 8-bit register that stores receive data. When the SCI has received one frame of serial data, it transfers the received serial data from RSR to RDR where it is stored. This allows RSR to receive the next data. Since RSR and RDR function as a double buffer in this way, continuous receive operations can be performed. After confirming that the RDRF bit in SSR is set to 1, read RDR only once. RDR cannot be written to by the CPU. Bit Bit Name Initial Value R/W 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 7 6 5 4 3 2 1 0 Rev. 2.00 Mar. 15, 2006 Page 416 of 754 REJ09B0199-0200 Section 13 Serial Communication Interface (SCI) 13.3.3 Transmit Data Register (TDR) TDR is an 8-bit register that stores transmit data. When the SCI detects that TSR is empty, it transfers the transmit data written in TDR to TSR and starts transmission. The double-buffered structures of TDR and TSR enables continuous serial transmission. If the next transmit data has already been written to TDR when one frame of data is transmitted, the SCI transfers the written data to TSR to continue transmission. Although TDR can be read from or written to by the CPU at all times, to achieve reliable serial transmission, write transmit data to TDR for only once after confirming that the TDRE bit in SSR is set to 1. Bit Bit Name Initial Value R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 7 6 5 4 3 2 1 0 13.3.4 Transmit Shift Register (TSR) TSR is a shift register that transmits serial data. To perform serial data transmission, the SCI first automatically transfers transmit data from TDR to TSR, then sends the data to the TxD pin. TSR cannot be directly accessed by the CPU. 13.3.5 Serial Mode Register (SMR) SMR is used to set the SCI's serial transfer format and select the baud rate generator clock source. Some bits in SMR have different functions in normal mode and smart card interface mode. * When SMIF in SCMR = 0 Bit Bit Name Initial Value R/W 7 C/A 0 R/W 6 CHR 0 R/W 5 PE 0 R/W 4 O/E 0 R/W 3 STOP 0 R/W 2 MP 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W * When SMIF in SCMR = 1 Bit Bit Name Initial Value R/W 7 GM 0 R/W 6 BLK 0 R/W 5 PE 0 R/W 4 O/E 0 R/W 3 BCP1 0 R/W 2 BCP0 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W Rev. 2.00 Mar. 15, 2006 Page 417 of 754 REJ09B0199-0200 Section 13 Serial Communication Interface (SCI) Bit Functions in Normal Serial Communication Interface Mode (When SMIF in SCMR = 0): Bit 7 Bit Name C/A Initial Value 0 R/W R/W Description Communication Mode 0: Asynchronous mode 1: Clocked synchronous mode 6 CHR 0 R/W Character Length (valid only in asynchronous mode) 0: Selects 8 bits as the data length. 1: Selects 7 bits as the data length. LSB-first is fixed and the MSB (bit 7) in TDR is not transmitted in transmission. In clocked synchronous mode, a fixed data length of 8 bits is used. 5 PE 0 R/W Parity Enable (valid only in asynchronous mode) When this bit is set to 1, the parity bit is added to transmit data before transmission, and the parity bit is checked in reception. For a multiprocessor format, parity bit addition and checking are not performed regardless of the PE bit setting. 4 O/E 0 R/W Parity Mode (valid only when the PE bit is 1 in asynchronous mode) 0: Selects even parity. 1: Selects odd parity. 3 STOP 0 R/W Stop Bit Length (valid only in asynchronous mode) Selects the stop bit length in transmission. 0: 1 stop bit 1: 2 stop bits In reception, only the first stop bit is checked. If the second stop bit is 0, it is treated as the start bit of the next transmit frame. 2 MP 0 R/W Multiprocessor Mode (valid only in asynchronous mode) When this bit is set to 1, the multiprocessor function is enabled. The PE bit and O/E bit settings are invalid in multiprocessor mode. Rev. 2.00 Mar. 15, 2006 Page 418 of 754 REJ09B0199-0200 Section 13 Serial Communication Interface (SCI) Bit 1 0 Bit Name CKS1 CKS0 Initial Value 0 0 R/W R/W R/W Description Clock Select 1, 0 These bits select the clock source for the baud rate generator. 00: P clock (n = 0) 01: P/4 clock (n = 1) 10: P/16 clock (n = 2) 11: P/64 clock (n = 3) For the relation between the settings of these bits and the baud rate, see section 13.3.9, Bit Rate Register (BRR). n is the decimal display of the value of n in BRR (see section 13.3.9, Bit Rate Register (BRR)). Bit Functions in Smart Card Interface Mode (When SMIF in SCMR = 1): Bit 7 Bit Name GM Initial Value 0 R/W R/W Description GSM Mode Setting this bit to 1 allows GSM mode operation. In GSM mode, the TEND set timing is put forward to 11.0 etu from the start and the clock output control function is appended. For details, see sections 13.7.6, Data Transmission (Except in Block Transfer Mode) and 13.7.8, Clock Output Control. 6 5 BLK PE 0 0 R/W R/W Setting this bit to 1 allows block transfer mode operation. For details, see section 13.7.3, Block Transfer Mode. Parity Enable (valid only in asynchronous mode) When this bit is set to 1, the parity bit is added to transmit data before transmission, and the parity bit is checked in reception. Set this bit to 1 in smart card interface mode. 4 O/E 0 R/W Parity Mode (valid only when the PE bit is 1 in asynchronous mode) 0: Selects even parity 1: Selects odd parity For details on the usage of this bit in smart card interface mode, see section 13.7.2, Data Format (Except in Block Transfer Mode). Rev. 2.00 Mar. 15, 2006 Page 419 of 754 REJ09B0199-0200 Section 13 Serial Communication Interface (SCI) Bit 3 2 Bit Name BCP1 BCP0 Initial Value 0 0 R/W R/W R/W Description Basic Clock Pulse 1,0 These bits select the number of basic clock cycles in a 1bit data transfer time in smart card interface mode. 00: 32 clock cycles (S = 32) 01: 64 clock cycles (S = 64) 10: 372 clock cycles (S = 372) 11: 256 clock cycles (S = 256) For details, see section 13.7.4, Receive Data Sampling Timing and Reception Margin. S is described in section 13.3.9, Bit Rate Register (BRR). 1 0 CKS1 CKS0 0 0 R/W R/W Clock Select 1,0 These bits select the clock source for the baud rate generator. 00: P clock (n = 0) 01: P/4 clock (n = 1) 10: P/16 clock (n = 2) 11: P/64 clock (n = 3) For the relation between the settings of these bits and the baud rate, see section 13.3.9, Bit Rate Register (BRR). n is the decimal display of the value of n in BRR (see section 13.3.9, Bit Rate Register (BRR)). Note: etu (Elementary Time Unit): 1-bit transfer time 13.3.6 Serial Control Register (SCR) SCR is a register that enables/disables the following SCI transfer operations and interrupt requests, and selects the transfer clock source. For details on interrupt requests, see section 13.8, Interrupt Sources. Some bits in SCR have different functions in normal mode and smart card interface mode. * When SMIF in SCMR = 0 Bit Bit Name Initial Value R/W 7 TIE 0 R/W 6 RIE 0 R/W 5 TE 0 R/W 4 RE 0 R/W 3 MPIE 0 R/W 2 TEIE 0 R/W 1 CKE1 0 R/W 0 CKE0 0 R/W Rev. 2.00 Mar. 15, 2006 Page 420 of 754 REJ09B0199-0200 Section 13 Serial Communication Interface (SCI) * When SMIF in SCMR = 1 Bit Bit Name Initial Value R/W 7 TIE 0 R/W 6 RIE 0 R/W 5 TE 0 R/W 4 RE 0 R/W 3 MPIE 0 R/W 2 TEIE 0 R/W 1 CKE1 0 R/W 0 CKE0 0 R/W Bit Functions in Normal Serial Communication Interface Mode (When SMIF in SCMR = 0): Bit 7 Bit Name TIE Initial Value 0 R/W R/W Description Transmit Interrupt Enable When this bit is set to 1, a TXI interrupt request is enabled. A TXI interrupt request can be cancelled by reading 1 from the TDRE flag and then clearing the flag to 0, or by clearing the TIE bit to 0. 6 RIE 0 R/W Receive Interrupt Enable When this bit is set to 1, RXI and ERI interrupt requests are enabled. RXI and ERI interrupt requests can be cancelled by reading 1 from the RDRF, FER, PER, or ORER flag and then clearing the flag to 0, or by clearing the RIE bit to 0. 5 TE 0 R/W Transmit Enable When this bit is set to 1, transmission is enabled. Under this condition, serial transmission is started by writing transmit data to TDR, and clearing the TDRE flag in SSR to 0. Note that SMR should be set prior to setting the TE bit to 1 Sin order to designate the transmission format. If transmission is halted by clearing this bit to 0, the TDRE flag in SSR is fixed 1. 4 RE 0 R/W Receive Enable When this bit is set to 1, reception is enabled. Under this condition, serial reception is started by detecting the start bit in asynchronous mode or the synchronous clock input in clocked synchronous mode. Note that SMR should be set prior to setting the RE bit to 1 in order to designate the reception format. Even if reception is halted by clearing this bit to 0, the RDRF, FER, PER, and ORER flags are not affected and the previous value is retained. Rev. 2.00 Mar. 15, 2006 Page 421 of 754 REJ09B0199-0200 Section 13 Serial Communication Interface (SCI) Bit 3 Bit Name MPIE Initial Value 0 R/W R/W Description Multiprocessor Interrupt Enable (valid only when the MP bit in SMR is 1 in asynchronous mode) When this bit is set to 1, receive data in which the multiprocessor bit is 0 is skipped, and setting of the RDRF, FER, and ORER status flags in SSR is disabled. On receiving data in which the multiprocessor bit is 1, this bit is automatically cleared and normal reception is resumed. For details, see section 13.5, Multiprocessor Communication Function. When receive data including MPB = 0 in SSR is being received, transfer of the received data from RSR to RDR, detection of reception errors, and the settings of RDRF, FER, and ORER flags in SSR are not performed. When receive data including MPB = 1 is received, the MPB bit in SSR is set to 1, the MPIE bit is automatically cleared to 0, and RXI and ERI interrupt requests (in the case where the TIE and RIE bits in SCR are set to 1) and setting of the FER and ORER flags are enabled. Transmit End Interrupt Enable When this bit is set to 1, a TEI interrupt request is enabled. A TEI interrupt request can be cancelled by reading 1 from the TDRE flag and then clearing the flag to 0 in order to clear the TEND flag to 0, or by clearing the TEIE bit to 0. Clock Enable 1, 0 These bits select the clock source and SCK pin function. * Asynchronous mode 00: On-chip baud rate generator (SCK pin functions as I/O port.) 01: On-chip baud rate generator (Outputs a clock with the same frequency as the bit rate from the SCK pin.) 1X: External clock (Inputs a clock with a frequency 16 times the bit rate from the SCK pin.) * Clocked synchronous mode 0X: Internal clock (SCK pin functions as clock output.) 1X: External clock (SCK pin functions as clock input.) 2 TEIE 0 R/W 1 0 CKE1 CKE0 0 0 R/W R/W Note: X: Don't care Rev. 2.00 Mar. 15, 2006 Page 422 of 754 REJ09B0199-0200 Section 13 Serial Communication Interface (SCI) Bit Functions in Smart Card Interface Mode (When SMIF in SCMR = 1): Bit 7 Bit Name TIE Initial Value 0 R/W R/W Description Transmit Interrupt Enable When this bit is set to 1,a TXI interrupt request is enabled. A TXI interrupt request can be cancelled by reading 1 from the TDRE flag and then clearing the flag to 0, or by clearing the TIE bit to 0. 6 RIE 0 R/W Receive Interrupt Enable When this bit is set to 1, RXI and ERI interrupt requests are enabled. RXI and ERI interrupt requests can be cancelled by reading 1 from the RDRF, FER, PER, or ORER flag and then clearing the flag to 0, or by clearing the RIE bit to 0. 5 TE 0 R/W Transmit Enable When this bit is set to 1, transmission is enabled. Under this condition, serial transmission is started by writing transmit data to TDR, and clearing the TDRE flag in SSR to 0. Note that SMR should be set prior to setting the TE bit to 1 in order to designate the transmission format. If transmission is halted by clearing this bit to 0, the TDRE flag in SSR is fixed 1. 4 RE 0 R/W Receive Enable When this bit is set to 1, reception is enabled. Under this condition, serial reception is started by detecting the start bit in asynchronous mode or the synchronous clock input in clocked synchronous mode. Note that SMR should be set prior to setting the RE bit to 1 in order to designate the reception format. Even if reception is halted by clearing this bit to 0, the RDRF, FER, PER, and ORER flags are not affected and the previous value is retained. 3 MPIE 0 R/W Multiprocessor Interrupt Enable (valid only when the MP bit in SMR is 1 in asynchronous mode) Write 0 to this bit in smart card interface mode. 2 TEIE 0 R/W Transmit End Interrupt Enable Write 0 to this bit in smart card interface mode. Rev. 2.00 Mar. 15, 2006 Page 423 of 754 REJ09B0199-0200 Section 13 Serial Communication Interface (SCI) Bit 1 0 Bit Name CKE1 CKE0 Initial Value 0 0 R/W R/W R/W Description Clock Enable 1, 0 These bits control the clock output from the SCK pin. In GSM mode, clock output can be dynamically switched. For details, see section 13.7.8, Clock Output Control. * When GM in SMR = 0 00: Output disabled (SCK pin functions as I/O port.) 01: Clock output 1X: Reserved * When GM in SMR = 1 00: Output fixed low 01: Clock output 10: Output fixed high 11: Clock output 13.3.7 Serial Status Register (SSR) SSR is a register containing status flags of the SCI and multiprocessor bits for transfer. TDRE, RDRF, ORER, PER, and FER can only be cleared. Some bits in SSR have different functions in normal mode and smart card interface mode. * When SMIF in SCMR = 0 Bit Bit Name Initial Value R/W 7 TDRE 1 R/(W)* 6 RDRF 0 R/(W)* 5 ORER 0 R/(W)* 4 FER 0 R/(W)* 3 PER 0 R/(W)* 2 TEND 1 R 1 MPB 0 R 0 MPBT 0 R/W Note: * Only 0 can be written, to clear the flag. * When SMIF in SCMR = 1 Bit Bit Name Initial Value R/W 7 TDRE 1 R/(W)* 6 RDRF 0 R/(W)* 5 ORER 0 R/(W)* 4 ERS 0 R/(W)* 3 PER 0 R/(W)* 2 TEND 1 R 1 MPB 0 R 0 MPBT 0 R/W Note: * Only 0 can be written, to clear the flag. Rev. 2.00 Mar. 15, 2006 Page 424 of 754 REJ09B0199-0200 Section 13 Serial Communication Interface (SCI) Bit Functions in Normal Serial Communication Interface Mode (When SMIF in SCMR = 0): Bit 7 Bit Name TDRE Initial Value 1 R/W Description R/(W)* Transmit Data Register Empty Indicates whether TDR contains transmit data. [Setting conditions] * * * When the TE bit in SCR is 0 When data is transferred from TDR to TSR When 0 is written to TDRE after reading TDRE = 1 (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) * When a TXI interrupt request is issued allowing DTC or DMAC to write data to TDR [Clearing conditions] 6 RDRF 0 R/(W)* Receive Data Register Full Indicates whether receive data is stored in RDR. [Setting condition] * When serial reception ends normally and receive data is transferred from RSR to RDR When 0 is written to RDRF after reading RDRF = 1 (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) * When an RXI interrupt request is issued allowing DTC or DMAC to read data from RDR [Clearing conditions] * The RDRF flag is not affected and retains its previous value when the RE bit in SCR is cleared to 0. Note that when the next serial reception is completed while the RDRF flag is being set to 1, an overrun error occurs and the received data is lost. Rev. 2.00 Mar. 15, 2006 Page 425 of 754 REJ09B0199-0200 Section 13 Serial Communication Interface (SCI) Bit 5 Bit Name ORER Initial Value 0 R/W Description 4 FER 0 R/(W)* Overrun Error Indicates that an overrun error has occurred during reception and the reception ends abnormally. [Setting condition] * When the next serial reception is completed while RDRF = 1 In RDR, receive data prior to an overrun error occurrence is retained, but data received after the overrun error occurrence is lost. When the ORER flag is set to 1, subsequent serial reception cannot be performed. Note that, in clocked synchronous mode, serial transmission also cannot continue. [Clearing condition] * When 0 is written to ORER after reading ORER = 1 (When the CPU is used to clear this flag by writing 0while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) Even when the RE bit in SCR is cleared, the ORER flag is not affected and retains its previous value. R/(W)* Framing Error Indicates that a framing error has occurred during reception in asynchronous mode and the reception ends abnormally. [Setting condition] * When the stop bit is 0 In 2-stop-bit mode, only the first stop bit is checked whether it is 1 but the second stop bit is not checked. Note that receive data when the framing error occurs is transferred to RDR, however, the RDRF flag is not set. In addition, when the FER flag is being set to 1, the subsequent serial reception cannot be performed. In clocked synchronous mode, serial transmission also cannot continue. [Clearing condition] * When 0 is written to FER after reading FER = 1 (When the CPU is used to clear this flag by writing 0while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) Even when the RE bit in SCR is cleared, the FER flag is not affected and retains its previous value. Rev. 2.00 Mar. 15, 2006 Page 426 of 754 REJ09B0199-0200 Section 13 Serial Communication Interface (SCI) Bit 3 Bit Name PER Initial Value 0 R/W Description R/(W)* Parity Error Indicates that a parity error has occurred during reception in asynchronous mode and the reception ends abnormally. [Setting condition] * When a parity error is detected during reception Receive data when the parity error occurs is transferred to RDR, however, the RDRF flag is not set. Note that when the PER flag is being set to 1, the subsequent serial reception cannot be performed. In clocked synchronous mode, serial transmission also cannot continue. [Clearing condition] * When 0 is written to PER after reading PER = 1 (When the CPU is used to clear this flag by writing 0while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) Even when the RE bit in SCR is cleared, the PER bit is not affected and retains its previous value. 2 TEND 1 R Transmit End [Setting conditions] * * When the TE bit in SCR is 0 When TDRE = 1 at transmission of the last bit of a transmit character When 0 is written to TDRE after reading TDRE = 1 When a TXI interrupt request is issued allowing DMAC to write data to TDR [Clearing conditions] * * 1 MPB 0 R Multiprocessor Bit Stores the multiprocessor bit value in the receive frame. When the RE bit in SCR is cleared to 0 its previous state is retained. 0 MPBT 0 R/W Multiprocessor Bit Transfer Sets the multiprocessor bit value to be added to the transmit frame. Note: * Only 0 can be written, to clear the flag. Rev. 2.00 Mar. 15, 2006 Page 427 of 754 REJ09B0199-0200 Section 13 Serial Communication Interface (SCI) Bit Functions in Smart Card Interface Mode (When SMIF in SCMR = 1): Bit 7 Bit Name TDRE Initial Value 1 R/W Description R/(W)* Transmit Data Register Empty Indicates whether TDR contains transmit data. [Setting conditions] * * * When the TE bit in SCR is 0 When data is transferred from TDR to TSR When 0 is written to TDRE after reading TDRE = 1 (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) * When a TXI interrupt request is issued allowing DTC or DMAC to write data to TDR [Clearing conditions] 6 RDRF 0 R/(W)* Receive Data Register Full Indicates whether receive data is stored in RDR. [Setting condition] * When serial reception ends normally and receive data is transferred from RSR to RDR When 0 is written to RDRF after reading RDRF = 1 (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) * When an RXI interrupt request is issued allowing DTC or DMAC to read data from RDR [Clearing conditions] * The RDRF flag is not affected and retains its previous value even when the RE bit in SCR is cleared to 0. Note that when the next reception is completed while the RDRF flag is being set to 1, an overrun error occurs and the received data is lost. Rev. 2.00 Mar. 15, 2006 Page 428 of 754 REJ09B0199-0200 Section 13 Serial Communication Interface (SCI) Bit 5 Bit Name ORER Initial Value 0 R/W Description R/(W)* Overrun Error Indicates that an overrun error has occurred during reception and the reception ends abnormally. [Setting condition] * When the next serial reception is completed while RDRF = 1 In RDR, the receive data prior to an overrun error occurrence is retained, but data received following the overrun error occurrence is lost. When the ORER flag is set to 1, subsequent serial reception cannot be performed. Note that, in clocked synchronous mode, serial transmission also cannot continue. [Clearing condition] * When 0 is written to ORER after reading ORER = 1 (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) Even when the RE bit in SCR is cleared, the ORER flag is not affected and retains its previous value. 4 ERS 0 R/(W)* Error Signal Status [Setting condition] * * When a low error signal is sampled When 0 is written to ERS after reading ERS = 1 (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) [Clearing condition] Rev. 2.00 Mar. 15, 2006 Page 429 of 754 REJ09B0199-0200 Section 13 Serial Communication Interface (SCI) Bit 3 Bit Name PER Initial Value 0 2 TEND 1 R/W Description R/(W)* Parity Error Indicates that a parity error has occurred during reception in asynchronous mode and the reception ends abnormally. [Setting condition] * When a parity error is detected during reception Receive data when the parity error occurs is transferred to RDR, however, the RDRF flag is not set. Note that when the PER flag is being set to 1, the subsequent serial reception cannot be performed. In clocked synchronous mode, serial transmission also cannot continue. [Clearing condition] * When 0 is written to PER after reading PER = 1 (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) Even when the RE bit in SCR is cleared, the PER flag is not affected and retains its previous value. R Transmit End This bit is set to 1 when no error signal is sent from the receiving side and the next transmit data is ready to be transferred to TDR. [Setting conditions] * When both the TE and ERS bits in SCR are 0 * When ERS = 0 and TDRE = 1 after a specified time passed after completion of 1-byte data transfer. The set timing depends on the register setting as follows: When GM = 0 and BLK = 0, 2.5 etu after transmission start When GM = 0 and BLK = 1, 1.5 etu after transmission start When GM = 1 and BLK = 0, 1.0 etu after transmission start When GM = 1 and BLK = 1, 1.0 etu after transmission start [Clearing conditions] * When 0 is written to TEND after reading TEND = 1 * When a TXI interrupt request is issued allowing DTC or DMAC to write the next data to TDR Rev. 2.00 Mar. 15, 2006 Page 430 of 754 REJ09B0199-0200 Section 13 Serial Communication Interface (SCI) Bit 1 0 Note: * Bit Name MPB MPBT Initial Value 0 0 R/W R R/W Description Multiprocessor Bit Not used in smart card interface mode. Multiprocessor Bit Transfer Write 0 to this bit in smart card interface mode. Only 0 can be written, to clear the flag. 13.3.8 Smart Card Mode Register (SCMR) SCMR selects smart card interface mode and its format. Bit Bit Name Initial Value R/W 7 -- 1 R 6 -- 1 R 5 -- 1 R 4 -- 1 R 3 SDIR 0 R/W 2 SINV 0 R/W 1 -- 1 R 0 SMIF 0 R/W Bit 7 to 4 3 Bit Name SDIR Initial Value All 1 0 R/W R R/W Description Reserved These are read-only bits and cannot be modified. Smart Card Data Transfer Direction Selects the serial/parallel conversion format. 0: Transfer with LSB-first 1: Transfer with MSB-first This bit is valid only when the 8-bit data format is used for transmission/reception; when the 7-bit data format is used, data is always transmitted/received with LSB-first. 2 SINV 0 R/W Smart Card Data Invert Inverts the transmit/receive data logic level. This bit does not affect the logic level of the parity bit. To invert the parity bit, invert the O/E bit in SMR. 0: TDR contents are transmitted as they are. Receive data is stored as it is in RDR. 1: TDR contents are inverted before being transmitted. Receive data is stored in inverted form in RDR. Rev. 2.00 Mar. 15, 2006 Page 431 of 754 REJ09B0199-0200 Section 13 Serial Communication Interface (SCI) Bit 1 0 Bit Name SMIF Initial Value 1 0 R/W R R/W Description Reserved This is a read-only bit and cannot be modified. Smart Card Interface Mode Select When this bit is set to 1, smart card interface mode is selected. 0: Normal asynchronous or clocked synchronous mode 1: Smart card interface mode 13.3.9 Bit Rate Register (BRR) BRR is an 8-bit register that adjusts the bit rate. As the SCI performs baud rate generator control independently for each channel, different bit rates can be set for each channel. Table 13.2 shows the relationships between the N setting in BRR and bit rate B for normal asynchronous mode and clocked synchronous mode, and smart card interface mode. The initial value of BRR is H'FF, and it can be read from or written to by the CPU at all times. Table 13.2 Relationships between N Setting in BRR and Bit Rate B Mode Asynchronous mode Clocked synchronous mode Smart card interface mode Bit Rate N= P x 10 64 x 2 N= 6 2n - 1 Error -1 Error (%) = { P x 106 B x 64 x 2 -1 P x 106 Error (%) = { BxSx2 2n + 1 xB 2n - 1 - 1 } x 100 x (N + 1) P x 106 8x2 2n - 1 xB -1 - 1 } x 100 x (N + 1) N= P x 106 Sx2 2n + 1 xB [Legend] B: Bit rate (bit/s) N: BRR setting for baud rate generator (0 N 255) P: Operating frequency (MHz) n and S: Determined by the SMR settings shown in the following table. Rev. 2.00 Mar. 15, 2006 Page 432 of 754 REJ09B0199-0200 Section 13 Serial Communication Interface (SCI) SMR Setting CKS1 0 0 1 1 CKS0 0 1 0 1 n 0 1 2 3 BCP1 0 0 1 1 SMR Setting BCP0 0 1 0 1 S 32 64 372 256 Table 13.3 shows sample N settings in BRR in normal asynchronous mode. Table 13.4 shows the maximum bit rate settable for each operating frequency. Tables 13.6 and 13.8 show sample N settings in BRR in clocked synchronous mode and smart card interface mode, respectively. In smart card interface mode, the number of basic clock cycles S in a 1-bit data transfer time can be selected. For details, see section 13.7.4, Receive Data Sampling Timing and Reception Margin. Tables 13.5 and 13.7 show the maximum bit rates with external clock input. Table 13.3 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (1) Operating Frequency P (MHz) Bit Rate (bit/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 8 n 2 2 1 1 0 0 0 0 0 0 N 141 103 207 103 207 103 51 25 12 7 Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.00 n 2 2 1 1 0 0 0 0 0 0 0 9.8304 N 174 127 255 127 255 127 63 31 15 9 7 Error (%) -0.26 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -1.70 0.00 n 2 2 2 1 1 0 0 0 0 0 0 N 177 129 64 129 64 129 64 32 15 9 7 10 Error (%) -0.25 0.16 0.16 0.16 0.16 0.16 0.16 -1.36 1.73 0.00 1.73 n 2 2 2 1 1 0 0 0 0 0 0 N 212 155 77 155 77 155 77 38 19 11 9 12 Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 -2.34 0.00 -2.34 Rev. 2.00 Mar. 15, 2006 Page 433 of 754 REJ09B0199-0200 Section 13 Serial Communication Interface (SCI) Operating Frequency P (MHz) Bit Rate (bit/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 12.288 n 2 2 2 1 1 0 0 0 0 0 0 N 217 159 79 159 79 159 79 39 19 11 9 Error (%) 0.08 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 2.40 0.00 n 2 2 2 1 1 0 0 0 0 0 N 248 181 90 181 90 181 90 45 22 13 14 Error (%) -0.17 0.16 0.16 0.16 0.16 0.16 0.16 -0.93 -0.93 0.00 n 3 2 2 1 1 0 0 0 0 0 0 14.7456 N 64 191 95 191 95 191 95 47 23 14 11 Error (%) 0.70 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -1.70 0.00 n 3 2 2 1 1 0 0 0 0 0 0 N 70 207 103 207 103 207 103 51 25 15 12 16 Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.00 0.16 Table 13.3 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (2) Operating Frequency P (MHz) Bit Rate (bit/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 17.2032 n 3 2 2 1 1 0 0 0 0 0 0 N 75 223 111 223 111 223 111 55 27 16 13 Error (%) 0.48 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 1.20 0.00 n 3 2 2 1 1 0 0 0 0 0 0 N 79 233 116 233 116 233 116 58 28 17 14 18 Error (%) -0.12 0.16 0.16 0.16 0.16 0.16 0.16 -0.69 1.02 0.00 -2.34 n 3 2 2 1 1 0 0 0 0 0 0 19.6608 N 86 255 127 255 127 255 127 63 31 19 15 Error (%) 0.31 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -1.70 0.00 n 3 3 2 2 1 1 0 0 0 0 0 N 88 64 129 64 129 64 129 64 32 19 15 20 Error (%) -0.25 0.16 0.16 0.16 0.16 0.16 0.16 0.16 -1.36 0.00 1.73 Rev. 2.00 Mar. 15, 2006 Page 434 of 754 REJ09B0199-0200 Section 13 Serial Communication Interface (SCI) Operating Frequency P (MHz) Bit Rate (bit/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 25 n 3 3 2 2 1 1 0 0 0 0 0 N 110 80 162 80 162 80 162 80 40 24 19 Error (%) -0.02 -0.47 0.15 -0.47 0.15 -0.47 0.15 -0.47 -0.76 0.00 1.73 n 3 3 2 2 1 1 0 0 0 0 0 N 132 97 194 97 194 97 194 97 48 29 23 30 Error (%) 0.13 -0.35 0.16 -0.35 0.16 -0.35 0.16 -0.35 -0.35 0 1.73 n 3 3 2 2 1 1 0 0 0 0 0 N 145 106 214 106 214 106 214 106 53 32 26 33 Error (%) 0.33 0.39 -0.07 0.39 -0.07 0.39 -0.07 0.39 -0.54 0 -0.54 n 3 3 2 2 1 1 0 0 0 0 0 N 154 113 227 113 227 113 227 113 56 34 28 35 Error (%) 0.23 -0.06 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -1.78 Table 13.4 Maximum Bit Rate for Each Operating Frequency (Asynchronous Mode) Maximum Bit Rate (bit/s) 250000 307200 312500 375000 384000 437500 460800 500000 Maximum Bit Rate (bit/s) 537600 562500 614400 625000 781250 937500 1031250 1093750 P (MHz) 8 9.8304 10 12 12.288 14 14.7456 16 n 0 0 0 0 0 0 0 0 N 0 0 0 0 0 0 0 0 P (MHz) 17.2032 18 19.6608 20 25 30 33 35 n 0 0 0 0 0 0 0 0 N 0 0 0 0 0 0 0 0 Rev. 2.00 Mar. 15, 2006 Page 435 of 754 REJ09B0199-0200 Section 13 Serial Communication Interface (SCI) Table 13.5 Maximum Bit Rate with External Clock Input (Asynchronous Mode) P (MHz) 8 9.8304 10 12 12.288 14 14.7456 16 External Input Clock (MHz) 2.0000 2.4576 2.5000 3.0000 3.0720 3.5000 3.6864 4.0000 Maximum Bit Rate (bit/s) 125000 153600 156250 187500 192000 218750 230400 250000 P (MHz) 17.2032 18 19.6608 20 25 30 33 35 External Input Clock (MHz) 4.3008 4.5000 4.9152 5.0000 6.2500 7.5000 8.2500 8.7500 Maximum Bit Rate (bit/s) 268800 281250 307200 312500 390625 468750 515625 546875 Table 13.6 BRR Settings for Various Bit Rates (Clocked Synchronous Mode) Operating Frequency P (MHz) Bit Rate (bit/s) n 110 250 500 1k 2.5k 5k 10k 25k 50k 100k 250k 500k 1M 2.5M 5M 3 2 2 1 1 0 0 0 0 0 0 0 124 249 124 199 99 199 79 39 19 7 3 1 0 0* 1 1 0 0 0 0 0 0 249 124 249 99 49 24 9 4 3 3 2 2 1 1 0 0 0 0 0 0 249 124 249 99 199 99 159 79 39 15 7 3 2 1 1 0 0 0 0 0 0 0 0 124 249 124 199 99 49 19 9 4 1 0* 8 N n 10 N n 16 N n 20 N Rev. 2.00 Mar. 15, 2006 Page 436 of 754 REJ09B0199-0200 Section 13 Serial Communication Interface (SCI) Operating Frequency P (MHz) Bit Rate (bit/s) n 110 250 500 1k 2.5k 5k 10k 25k 50k 100k 250k 500k 1M 2.5M 5M 3 2 2 1 0 0 0 0 97 155 77 155 249 124 62 24 3 3 2 2 1 1 0 0 0 0 0 233 116 187 93 187 74 149 74 29 14 2 3 2 2 1 1 0 0 0 128 205 102 205 82 164 82 32 3 2 2 1 1 0 0 0 136 218 108 218 87 174 87 34 25 N n 30 N n 33 N n 35 N [Legend] Space : Setting prohibited. : Can be set, but there will be error. * : Continuous transmission or reception is not possible. Table 13.7 Maximum Bit Rate with External Clock Input (Clocked Synchronous Mode) P (MHz) 8 10 12 14 16 18 External Input Clock (MHz) 1.3333 1.6667 2.0000 2.3333 2.6667 3.0000 Maximum Bit Rate (bit/s) 1333333.3 1666666.7 2000000.0 2333333.3 2666666.7 3000000.0 P (MHz) 20 25 30 33 35 External Input Clock (MHz) 3.3333 4.1667 5.0000 5.5000 5.8336 Maximum Bit Rate (bit/s) 3333333.3 4166666.7 5000000.0 5500000.0 5833625.0 Rev. 2.00 Mar. 15, 2006 Page 437 of 754 REJ09B0199-0200 Section 13 Serial Communication Interface (SCI) Table 13.8 BRR Settings for Various Bit Rates (Smart Card Interface Mode, n = 0, S = 372) Operating Frequency P (MHz) Bit Rate (bit/s) 9600 n 0 N 0 7.1424 Error (%) n 0.00 0 N 1 10.00 Error (%) n 30 0 10.7136 N 1 Error (%) n 25 0 N 1 13.00 Error (%) 8.99 Operating Frequency P (MHz) Bit Rate (bit/s) 9600 n 0 N 1 14.2848 Error (%) n 0.00 0 N 1 16.00 Error (%) n 12.01 0 N 2 18.00 Error (%) n 15.99 0 N 2 20.00 Error (%) 6.60 Operating Frequency P (MHz) Bit Rate (bit/s) 9600 n 0 N 3 25.00 Error (%) n 12.49 0 N 3 30.00 Error (%) n 5.01 0 N 4 33.00 Error (%) n 7.59 0 N 4 35.00 Error (%) 1.99 Table 13.9 Maximum Bit Rate for Each Operating Frequency (Smart Card Interface Mode, S = 372) P (MHz) 7.1424 10.00 10.7136 13.00 14.2848 16.00 Maximum Bit Rate (bit/s) 9600 13441 14400 17473 19200 21505 n 0 0 0 0 0 0 N 0 0 0 0 0 0 P (MHz) 18.00 20.00 25.00 30.00 33.00 35.00 Maximum Bit Rate (bit/s) 24194 26882 33602 40323 44355 47043 n 0 0 0 0 0 0 N 0 0 0 0 0 0 Rev. 2.00 Mar. 15, 2006 Page 438 of 754 REJ09B0199-0200 Section 13 Serial Communication Interface (SCI) 13.4 Operation in Asynchronous Mode Figure 13.2 shows the general format for asynchronous serial communication. One frame consists of a start bit (low level), followed by transmit/receive data, a parity bit, and finally stop bits (high level). In asynchronous serial communication, the communication line is usually held in the mark state (high level). The SCI monitors the communication line, and when it goes to the space state (low level), recognizes a start bit and starts serial communication. Inside the SCI, the transmitter and receiver are independent units, enabling full-duplex communication. Both the transmitter and the receiver also have a double-buffered structure, so that data can be read or written during transmission or reception, enabling continuous data transmission and reception. Idle state (mark state) 1 Serial data 0 Start bit 1 bit LSB D0 D1 D2 D3 D4 D5 D6 MSB D7 0/1 Parity bit 1 bit or none 1 1 1 Stop bit Transmit/receive data 7 or 8 bits One unit of transfer data (character or frame) 1 or 2 bits Figure 13.2 Data Format in Asynchronous Communication (Example with 8-Bit Data, Parity, Two Stop Bits) Rev. 2.00 Mar. 15, 2006 Page 439 of 754 REJ09B0199-0200 Section 13 Serial Communication Interface (SCI) 13.4.1 Data Transfer Format Table 13.10 shows the data transfer formats that can be used in asynchronous mode. Any of 12 transfer formats can be selected according to the SMR setting. For details on the multiprocessor bit, see section 13.5, Multiprocessor Communication Function. Table 13.10 Serial Transfer Formats (Asynchronous Mode) SMR Settings CHR 0 PE 0 MP 0 STOP 0 1 S Serial Transmit/Receive Format and Frame Length 2 3 4 5 6 7 8 9 10 STOP 11 12 8-bit data 0 0 0 1 S 8-bit data STOP STOP 0 1 0 0 S 8-bit data P STOP 0 1 0 1 S 8-bit data P STOP STOP 1 0 0 0 S 7-bit data STOP 1 0 0 1 S 7-bit data STOP STOP 1 1 0 0 S 7-bit data P STOP 1 1 0 1 S 7-bit data P STOP STOP 0 -- 1 0 S 8-bit data MPB STOP 0 -- 1 1 S 8-bit data MPB STOP STOP 1 -- 1 0 S 7-bit data MPB STOP 1 -- 1 1 S 7-bit data MPB STOP STOP [Legend] S: Start bit STOP: Stop bit P: Parity bit MPB: Multiprocessor bit Rev. 2.00 Mar. 15, 2006 Page 440 of 754 REJ09B0199-0200 Section 13 Serial Communication Interface (SCI) 13.4.2 Receive Data Sampling Timing and Reception Margin in Asynchronous Mode In asynchronous mode, the SCI operates on a basic clock with a frequency of 16 times the bit rate. In reception, the SCI samples the falling edge of the start bit using the basic clock, and performs internal synchronization. Since receive data is sampled at the rising edge of the 8th pulse of the basic clock, data is latched at the middle of each bit, as shown in figure 13.3. Thus the reception margin in asynchronous mode is determined by formula (1) below. M = | (0.5 - M: N: D: L: F: 1 ) - (L - 0.5) F - 2N | D - 0.5 | (1 + F ) | x 100 N [%] ... Formula (1) Reception margin Ratio of bit rate to clock (N = 16) Duty cycle of clock (D = 0.5 to 1.0) Frame length (L = 9 to 12) Absolute value of clock frequency deviation Assuming values of F = 0 and D = 0.5 in formula (1), the reception margin is determined by the formula below. M = ( 0.5 - 1 ) x 100 2 x 16 [%] = 46.875% However, this is only the computed value, and a margin of 20% to 30% should be allowed in system design. 16 clocks 8 clocks 0 Internal basic clock 7 15 0 7 15 0 Receive data (RxD) Synchronization sampling timing Start bit D0 D1 Data sampling timing Figure 13.3 Receive Data Sampling Timing in Asynchronous Mode Rev. 2.00 Mar. 15, 2006 Page 441 of 754 REJ09B0199-0200 Section 13 Serial Communication Interface (SCI) 13.4.3 Clock Either an internal clock generated by the on-chip baud rate generator or an external clock input to the SCK pin can be selected as the SCI's transfer clock, according to the setting of the C/A bit in SMR and the CKE1 and CKE0 bits in SCR. When an external clock is input to the SCK pin, the clock frequency should be 16 times the bit rate used. When the SCI is operated on an internal clock, the clock can be output from the SCK pin. The frequency of the clock output in this case is equal to the bit rate, and the phase is such that the rising edge of the clock is in the middle of the transmit data, as shown in figure 13.4. SCK TxD 0 D0 D1 D2 D3 D4 D5 D6 D7 0/1 1 1 1 frame Figure 13.4 Phase Relation between Output Clock and Transmit Data (Asynchronous Mode) Rev. 2.00 Mar. 15, 2006 Page 442 of 754 REJ09B0199-0200 Section 13 Serial Communication Interface (SCI) 13.4.4 SCI Initialization (Asynchronous Mode) Before transmitting and receiving data, first clear the TE and RE bits in SCR to 0, then initialize the SCI as described in a sample flowchart in figure 13.5. When the operating mode, transfer format, etc., is changed, the TE and RE bits must be cleared to 0 before making the change. When the TE bit is cleared to 0, the TDRE flag is set to 1. Note that clearing the RE bit to 0 does not initialize the RDRF, PER, FER, and ORER flags, or RDR. When the external clock is used in asynchronous mode, the clock must be supplied even during initialization. Start initialization [1] Clear TE and RE bits in SCR to 0 Set corresponding bit in ICR to 1 [1] [2] Set the bit in ICR for the corresponding pin when receiving data or using an external clock. Set the clock selection in SCR. Be sure to clear bits RIE, TIE, TEIE, and MPIE, and bits TE and RE, to 0. When the clock output is selected in asynchronous mode, the clock is output immediately after SCR settings are made. [3] [4] Set the data transfer format in SMR and SCMR. Write a value corresponding to the bit rate to BRR. This step is not necessary if an external clock is used. Wait at least one bit interval, then set the TE bit or RE bit in SCR to 1. Also set the RIE, TIE, TEIE, and MPIE bits. Setting the TE and RE bits enables the TxD and RxD pins to be used. Set CKE1 and CKE0 bits in SCR (TE and RE bits are 0) [2] Set data transfer format in SMR and SCMR Set value in BRR Wait [3] [4] [5] No 1-bit interval elapsed Yes Set TE or RE bit in SCR to 1, and set RIE, TIE, TEIE, and MPIE bits [5] Figure 13.5 Sample SCI Initialization Flowchart Rev. 2.00 Mar. 15, 2006 Page 443 of 754 REJ09B0199-0200 Section 13 Serial Communication Interface (SCI) 13.4.5 Serial Data Transmission (Asynchronous Mode) Figure 13.6 shows an example of the operation for transmission in asynchronous mode. In transmission, the SCI operates as described below. 1. The SCI monitors the TDRE flag in SSR, and if it is cleared to 0, recognizes that data has been written to TDR, and transfers the data from TDR to TSR. 2. After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts transmission. If the TIE bit in SCR is set to 1 at this time, a TXI interrupt request is generated. Because the TXI interrupt processing routine writes the next transmit data to TDR before transmission of the current transmit data has finished, continuous transmission can be enabled. 3. Data is sent from the TxD pin in the following order: start bit, transmit data, parity bit or multiprocessor bit (may be omitted depending on the format), and stop bit. 4. The SCI checks the TDRE flag at the timing for sending the stop bit. 5. If the TDRE flag is 0, the next transmit data is transferred from TDR to TSR, the stop bit is sent, and then serial transmission of the next frame is started. 6. If the TDRE flag is 1, the TEND flag in SSR is set to 1, the stop bit is sent, and then the mark state is entered in which 1 is output. If the TEIE bit in SCR is set to 1 at this time, a TEI interrupt request is generated. Figure 13.7 shows a sample flowchart for transmission in asynchronous mode. Start bit 0 D0 D1 Data D7 Parity Stop Start bit bit bit 0/1 1 0 D0 D1 Data D7 Parity Stop bit bit 0/1 1 1 1 Idle state (mark state) TDRE TEND TXI interrupt Data written to TDR and request generated TDRE flag cleared to 0 in TXI interrupt processing routine 1 frame TXI interrupt request generated TEI interrupt request generated Figure 13.6 Example of Operation for Transmission in Asynchronous Mode (Example with 8-Bit Data, Parity, One Stop Bit) Rev. 2.00 Mar. 15, 2006 Page 444 of 754 REJ09B0199-0200 Section 13 Serial Communication Interface (SCI) Initialization Start transmission [1] Read TDRE flag in SSR No [2] [1] SCI initialization: The TxD pin is automatically designated as the transmit data output pin. After the TE bit is set to 1, a 1 is output for a frame, and transmission is enabled. [2] SCI state check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR and clear the TDRE flag to 0. [3] Serial transmission continuation procedure: To continue serial transmission, read 1 from the TDRE flag to confirm that writing is possible, then write data to TDR, and clear the TDRE flag to 0. However, the TDRE flag is checked and cleared automatically when the DTC or DMAC is initiated by a transmit data empty interrupt (TXI) request and writes data to TDR. [4] Break output at the end of serial transmission: To output a break in serial transmission, set DDR for the port corresponding to the TxD pin to 1, clear DR to 0, then clear the TE bit in SCR to 0. TDRE = 1 Yes Write transmit data to TDR and clear TDRE flag in SSR to 0 All data transmitted? Yes No [3] Read TEND flag in SSR No TEND = 1 Yes Break output Yes Clear DR to 0 and set DDR to 1 No [4] Clear TE bit in SCR to 0 Figure 13.7 Sample Serial Transmission Flowchart 13.4.6 Serial Data Reception (Asynchronous Mode) Figure 13.8 shows an example of the operation for reception in asynchronous mode. In serial reception, the SCI operates as described below. 1. The SCI monitors the communication line, and if a start bit is detected, performs internal synchronization, stores receive data in RSR, and checks the parity bit and stop bit. Rev. 2.00 Mar. 15, 2006 Page 445 of 754 REJ09B0199-0200 Section 13 Serial Communication Interface (SCI) 2. If an overrun error (when reception of the next data is completed while the RDRF flag in SSR is still set to 1) occurs, the ORER bit in SSR is set to 1. If the RIE bit in SCR is set to 1 at this time, an ERI interrupt request is generated. Receive data is not transferred to RDR. The RDRF flag remains to be set to 1. 3. If a parity error is detected, the PER bit in SSR is set to 1 and receive data is transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an ERI interrupt request is generated. 4. If a framing error (when the stop bit is 0) is detected, the FER bit in SSR is set to 1 and receive data is transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an ERI interrupt request is generated. 5. If reception finishes successfully, the RDRF bit in SSR is set to 1, and receive data is transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an RXI interrupt request is generated. Because the RXI interrupt processing routine reads the receive data transferred to RDR before reception of the next receive data has finished, continuous reception can be enabled. Start bit 0 D0 D1 Data D7 Parity Stop Start bit bit bit 0/1 1 0 D0 D1 Data D7 Parity Stop bit bit 0/1 0 1 1 Idle state (mark state) RDRF FER RXI interrupt request generated RDR data read and RDRF flag cleared to 0 in RXI interrupt processing routine ERI interrupt request generated by framing error 1 frame Figure 13.8 Example of SCI Operation for Reception (Example with 8-Bit Data, Parity, One Stop Bit) Table 13.11 shows the states of the SSR status flags and receive data handling when a receive error is detected. If a receive error is detected, the RDRF flag retains its state before receiving data. Reception cannot be resumed while a receive error flag is set to 1. Accordingly, clear the ORER, FER, PER, and RDRF bits to 0 before resuming reception. Figure 13.9 shows a sample flowchart for serial data reception. Rev. 2.00 Mar. 15, 2006 Page 446 of 754 REJ09B0199-0200 Section 13 Serial Communication Interface (SCI) Table 13.11 SSR Status Flags and Receive Data Handling SSR Status Flag RDRF* 1 0 0 1 1 0 1 Note: * ORER 1 0 0 1 1 0 1 FER 0 1 0 1 0 1 1 PER 0 0 1 0 1 1 1 Receive Data Lost Transferred to RDR Transferred to RDR Lost Lost Transferred to RDR Lost Receive Error Type Overrun error Framing error Parity error Overrun error + framing error Overrun error + parity error Framing error + parity error Overrun error + framing error + parity error The RDRF flag retains the state it had before data reception. Initialization Start reception [1] [1] SCI initialization: The RxD pin is automatically designated as the receive data input pin. No [2] [3] Receive error processing and break detection: Read ORER, PER, and If a receive error occurs, read the ORER, [2] FER flags in SSR PER, and FER flags in SSR to identify the error. After performing the appropriate error processing, ensure that the ORER, Yes PER, and FER flags are all cleared to 0. PER FER ORER = 1 [3] Reception cannot be resumed if any of these flags are set to 1. In the case of a No Error processing framing error, a break can be detected by (Continued on next page) reading the value of the input port corresponding to the RxD pin. [4] Read RDRF flag in SSR [4] SCI state check and receive data read: Read SSR and check that RDRF = 1, then read the receive data in RDR and clear the RDRF = 1 RDRF flag to 0. Transition of the RDRF flag from 0 to 1 can also be identified by an Yes RXI interrupt. Read receive data in RDR, and [5] Serial reception continuation procedure: clear RDRF flag in SSR to 0 To continue serial reception, before the stop bit for the current frame is received, read the RDRF flag and RDR, and clear the RDRF flag to 0. However, the RDRF flag is cleared automatically when the DTC or DMAC is initiated by an RXI interrupt and reads data from RDR. No All data received? Yes Clear RE bit in SCR to 0 [5] Figure 13.9 Sample Serial Reception Flowchart (1) Rev. 2.00 Mar. 15, 2006 Page 447 of 754 REJ09B0199-0200 Section 13 Serial Communication Interface (SCI) [3] Error processing No ORER = 1 Yes Overrun error processing No FER = 1 Yes Break? No Framing error processing Clear RE bit in SCR to 0 Yes No PER = 1 Yes Parity error processing Clear ORER, PER, and FER flags in SSR to 0 Figure 13.9 Sample Serial Reception Flowchart (2) Rev. 2.00 Mar. 15, 2006 Page 448 of 754 REJ09B0199-0200 Section 13 Serial Communication Interface (SCI) 13.5 Multiprocessor Communication Function Use of the multiprocessor communication function enables data transfer to be performed among a number of processors sharing communication lines by means of asynchronous serial communication using the multiprocessor format, in which a multiprocessor bit is added to the transfer data. When multiprocessor communication is carried out, each receiving station is addressed by a unique ID code. The serial communication cycle consists of two component cycles: an ID transmission cycle which specifies the receiving station, and a data transmission cycle for the specified receiving station. The multiprocessor bit is used to differentiate between the ID transmission cycle and the data transmission cycle. If the multiprocessor bit is 1, the cycle is an ID transmission cycle, and if the multiprocessor bit is 0, the cycle is a data transmission cycle. Figure 13.10 shows an example of inter-processor communication using the multiprocessor format. The transmitting station first sends data which includes the ID code of the receiving station and a multiprocessor bit set to 1. It then transmits transmit data added with the multiprocessor bit cleared to 0. The receiving station skips data until data with the multiprocessor bit set to 1 is sent. When data with the multiprocessor bit set to 1 is received, the receiving station compares that data with its own ID. The station whose ID matches then receives the data sent next. Stations whose ID does not match continue to skip data until data with the multiprocessor bit set to 1 is again received. The SCI uses the MPIE bit in SCR to implement this function. When the MPIE bit is set to 1, transfer of receive data from RSR to RDR, error flag detection, and setting the SSR status flags, RDRF, FER, and ORER in SSR to 1 are prohibited until data with the multiprocessor bit set to 1 is received. On reception of a receive character with the multiprocessor bit set to 1, the MPBR bit in SSR is set to 1 and the MPIE bit is automatically cleared, thus normal reception is resumed. If the RIE bit in SCR is set to 1 at this time, an RXI interrupt is generated. When the multiprocessor format is selected, the parity bit setting is invalid. All other bit settings are the same as those in normal asynchronous mode. The clock used for multiprocessor communication is the same as that in normal asynchronous mode. Rev. 2.00 Mar. 15, 2006 Page 449 of 754 REJ09B0199-0200 Section 13 Serial Communication Interface (SCI) Transmitting station Communication line Receiving station A (ID = 01) Serial data Receiving station B (ID = 02) Receiving station C (ID = 03) Receiving station D (ID = 04) H'01 (MPB = 1) H'AA (MPB = 0) ID transmission cycle = receiving station specification [Legend] MPB: Multiprocessor bit Data transmission cycle = Data transmission to receiving station specified by ID Figure 13.10 Example of Communication Using Multiprocessor Format (Transmission of Data H'AA to Receiving Station A) Rev. 2.00 Mar. 15, 2006 Page 450 of 754 REJ09B0199-0200 Section 13 Serial Communication Interface (SCI) 13.5.1 Multiprocessor Serial Data Transmission Figure 13.11 shows a sample flowchart for multiprocessor serial data transmission. For an ID transmission cycle, set the MPBT bit in SSR to 1 before transmission. For a data transmission cycle, clear the MPBT bit in SSR to 0 before transmission. All other SCI operations are the same as those in asynchronous mode. Initialization Start transmission Read TDRE flag in SSR No [1] [2] [1] SCI initialization: The TxD pin is automatically designated as the transmit data output pin. After the TE bit is set to 1, a 1 is output for one frame, and transmission is enabled. [2] SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR. Set the MPBT bit in SSR to 0 or 1. Finally, clear the TDRE flag to 0. [3] Serial transmission continuation procedure: To continue serial transmission, be sure to read 1 from the TDRE flag to confirm that writing is possible, then write data to TDR, and then clear the TDRE flag to 0. However, the TDRE flag is checked and cleared automatically when the DTC or DMAC is initiated by a transmit data empty interrupt (TXI) request and writes data to TDR. [4] Break output at the end of serial transmission: To output a break in serial transmission, set DDR for the port to 1, clear DR to 0, and then clear the TE bit in SCR to 0. TDRE = 1 Yes Write transmit data to TDR and set MPBT bit in SSR Clear TDRE flag to 0 All data transmitted? Yes Read TEND flag in SSR No [3] TEND = 1 Yes Break output? Yes Clear DR to 0 and set DDR to 1 No No [4] Clear TE bit in SCR to 0 Figure 13.11 Sample Multiprocessor Serial Transmission Flowchart Rev. 2.00 Mar. 15, 2006 Page 451 of 754 REJ09B0199-0200 Section 13 Serial Communication Interface (SCI) 13.5.2 Multiprocessor Serial Data Reception Figure 13.13 shows a sample flowchart for multiprocessor serial data reception. If the MPIE bit in SCR is set to 1, data is skipped until data with a 1 multiprocessor bit is sent. On receiving data with a 1 multiprocessor bit, the receive data is transferred to RDR. An RXI interrupt request is generated at this time. All other SCI operations are the same as in asynchronous mode. Figure 13.12 shows an example of SCI operation for multiprocessor format reception. Start bit 0 D0 D1 Data (ID1) MPB D7 1 Stop bit 1 Start bit 0 D0 Data (Data 1) MPB D1 D7 0 Stop bit 1 1 1 Idle state (mark state) MPIE RDRF RDR value MPIE = 0 RXI interrupt request (multiprocessor interrupt) generated RDR data read and RDRF flag cleared to 0 in RXI interrupt processing routine ID1 If not this station's ID, MPIE bit is set to 1 again RXI interrupt request is not generated, and RDR retains its state (a) Data does not match station's ID 1 Start bit 0 D0 D1 Data (ID2) MPB D7 1 Stop bit 1 Start bit 0 D0 Data (Data 2) Stop MPB bit 0 1 D1 D7 1 Idle state (mark state) MPIE RDRF RDR value ID1 MPIE = 0 RXI interrupt request (multiprocessor interrupt) generated RDR data read and RDRF flag cleared to 0 in RXI interrupt processing routine ID2 Matches this station's ID, so reception continues, and data is received in RXI interrupt processing routine Data 2 MPIE bit set to 1 again (b) Data matches station's ID Figure 13.12 Example of SCI Operation for Reception (Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit) Rev. 2.00 Mar. 15, 2006 Page 452 of 754 REJ09B0199-0200 Section 13 Serial Communication Interface (SCI) Initialization Start reception Set MPIE bit in SCR to 1 Read ORER and FER flags in SSR FER ORER = 1 No Read RDRF flag in SSR No [1] [1] SCI initialization: The RxD pin is automatically designated as the receive data input pin. [2] ID reception cycle: Set the MPIE bit in SCR to 1. [3] SCI state check, ID reception and comparison: Read SSR and check that the RDRF flag is set to 1, then read the receive data in RDR and compare it with this station's ID. If the data is not this station's ID, set the MPIE bit to 1 again, and clear the RDRF flag to 0. If the data is this station's ID, clear the RDRF flag to 0. [4] SCI state check and data reception: Read SSR and check that the RDRF flag is set to 1, then read the data in RDR. [5] Receive error processing and break detection: If a receive error occurs, read the ORER and FER flags in SSR to identify the error. After performing the appropriate error processing, ensure that the ORER and FER flags are both cleared to 0. Reception cannot be resumed if either of these flags is set to 1. In the case of a framing error, a break can be detected by reading the RxD pin value. [4] [2] Yes [3] RDRF = 1 Yes Read receive data in RDR No This station's ID? Yes Read ORER and FER flags in SSR FER ORER = 1 No Read RDRF flag in SSR No Yes RDRF = 1 Yes Read receive data in RDR No All data received? Yes Clear RE bit in SCR to 0 [5] Error processing (Continued on next page) Figure 13.13 Sample Multiprocessor Serial Reception Flowchart (1) Rev. 2.00 Mar. 15, 2006 Page 453 of 754 REJ09B0199-0200 Section 13 Serial Communication Interface (SCI) [5] Error processing No ORER = 1 Yes Overrun error processing No FER = 1 Yes Break? No Framing error processing Clear RE bit in SCR to 0 Yes Clear ORER, PER, and FER flags in SSR to 0 Figure 13.13 Sample Multiprocessor Serial Reception Flowchart (2) Rev. 2.00 Mar. 15, 2006 Page 454 of 754 REJ09B0199-0200 Section 13 Serial Communication Interface (SCI) 13.6 Operation in Clocked Synchronous Mode Figure 13.14 shows the general format for clocked synchronous communication. In clocked synchronous mode, data is transmitted or received in synchronization with clock pulses. One character in transfer data consists of 8-bit data. In data transmission, the SCI outputs data from one falling edge of the synchronization clock to the next. In data reception, the SCI receives data in synchronization with the rising edge of the synchronization clock. After 8-bit data is output, the transmission line holds the MSB output state. In clocked synchronous mode, no parity bit or multiprocessor bit is added. Inside the SCI, the transmitter and receiver are independent units, enabling full-duplex communication by use of a common clock. Both the transmitter and the receiver also have a double-buffered structure, so that the next transmit data can be written during transmission or the previous receive data can be read during reception, enabling continuous data transfer. One unit of transfer data (character or frame) * Synchronization clock LSB Serial data Don't care Note: * Holds a high level except during continuous transfer. Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 MSB Bit 7 Don't care * Figure 13.14 Data Format in Clocked Synchronous Communication (LSB-First) 13.6.1 Clock Either an internal clock generated by the on-chip baud rate generator or an external synchronization clock input at the SCK pin can be selected, according to the setting of the CKE1 and CKE0 bits in SCR. When the SCI is operated on an internal clock, the synchronization clock is output from the SCK pin. Eight synchronization clock pulses are output in the transfer of one character, and when no transfer is performed the clock is fixed high. Note that in the case of reception only, the synchronization clock is output until an overrun error occurs or until the RE bit is cleared to 0. Rev. 2.00 Mar. 15, 2006 Page 455 of 754 REJ09B0199-0200 Section 13 Serial Communication Interface (SCI) 13.6.2 SCI Initialization (Clocked Synchronous Mode) Before transmitting and receiving data, first clear the TE and RE bits in SCR to 0, then initialize the SCI as described in a sample flowchart in figure 13.15. When the operating mode, transfer format, etc., is changed, the TE and RE bits must be cleared to 0 before making the change. When the TE bit is cleared to 0, the TDRE flag is set to 1. However, clearing the RE bit to 0 does not initialize the RDRF, PER, FER, and ORER flags, or RDR. Start initialization [1] Clear TE and RE bits in SCR to 0 Set corresponding bit in ICR to 1 [1] Set the bit in ICR for the corresponding pin when receiving data or using an external clock. Set CKE1 and CKE0 bits in SCR (TE and RE bits are 0) [2] Set the clock selection in SCR. Be sure to clear bits RIE, TIE, TEIE, and MPIE, and bits TE and RE, to 0. [3] Set the data transfer format in SMR and SCMR. [4] Write a value corresponding to the bit rate to BRR. This step is not necessary if an external clock is used. [5] Wait at least one bit interval, then set the TE bit or RE bit in SCR to 1. Also set the RIE, TIE TEIE, and MPIE bits. Setting the TE and RE bits enables the TxD and RxD pins to be used. [2] Set data transfer format in SMR and SCMR Set value in BRR Wait [3] [4] 1-bit interval elapsed? Yes No Set TE or RE bit in SCR to 1, and set RIE, TIE, TEIE, and MPIE bits [5] Figure 13.15 Sample SCI Initialization Flowchart Rev. 2.00 Mar. 15, 2006 Page 456 of 754 REJ09B0199-0200 Section 13 Serial Communication Interface (SCI) 13.6.3 Serial Data Transmission (Clocked Synchronous Mode) Figure 13.16 shows an example of the operation for transmission in clocked synchronous mode. In transmission, the SCI operates as described below. 1. The SCI monitors the TDRE flag in SSR, and if it is 0, recognizes that data has been written to TDR, and transfers the data from TDR to TSR. 2. After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts transmission. If the TIE bit in SCR is set to 1 at this time, a TXI interrupt request is generated. Because the TXI interrupt processing routine writes the next transmit data to TDR before transmission of the current transmit data has finished, continuous transmission can be enabled. 3. 8-bit data is sent from the TxD pin synchronized with the output clock when clock output mode has been specified and synchronized with the input clock when use of an external clock has been specified. 4. The SCI checks the TDRE flag at the timing for sending the last bit. 5. If the TDRE flag is cleared to 0, the next transmit data is transferred from TDR to TSR, and serial transmission of the next frame is started. 6. If the TDRE flag is set to 1, the TEND flag in SSR is set to 1, and the TxD pin retains the output state of the last bit. If the TEIE bit in SCR is set to 1 at this time, a TEI interrupt request is generated. The SCK pin is fixed high. Figure 13.17 shows a sample flowchart for serial data transmission. Even if the TDRE flag is cleared to 0, transmission will not start while a receive error flag (ORER, FER, or PER) is set to 1. Make sure to clear the receive error flags to 0 before starting transmission. Note that clearing the RE bit to 0 does not clear the receive error flags. Rev. 2.00 Mar. 15, 2006 Page 457 of 754 REJ09B0199-0200 Section 13 Serial Communication Interface (SCI) Transfer direction Synchronization clock Serial data TDRE TEND TXI interrupt request generated Data written to TDR and TDRE flag cleared to 0 in TXI interrupt processing routine 1 frame TXI interrupt request generated TEI interrupt request generated Bit 0 Bit 1 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 Figure 13.16 Example of Operation for Transmission in Clocked Synchronous Mode [1] SCI initialization: The TxD pin is automatically designated as the transmit data output pin. [2] SCI state check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR and clear the TDRE flag to 0. [3] Serial transmission continuation procedure: To continue serial transmission, be sure to read 1 from the TDRE flag to confirm that writing is possible, then write data to TDR, and then clear the TDRE flag to 0. However, the TDRE flag is checked and cleared automatically when the DTC or DMAC is initiated by a transmit data empty interrupt (TXI) request and writes data to TDR. Initialization Start transmission [1] Read TDRE flag in SSR No [2] TDRE = 1 Yes Write transmit data to TDR and clear TDRE flag in SSR to 0 All data transmitted Yes Read TEND flag in SSR No [3] TEND = 1 Yes Clear TE bit in SCR to 0 No Figure 13.17 Sample Serial Transmission Flowchart Rev. 2.00 Mar. 15, 2006 Page 458 of 754 REJ09B0199-0200 Section 13 Serial Communication Interface (SCI) 13.6.4 Serial Data Reception (Clocked Synchronous Mode) Figure 13.18 shows an example of SCI operation for reception in clocked synchronous mode. In serial reception, the SCI operates as described below. 1. The SCI performs internal initialization in synchronization with a synchronization clock input or output, starts receiving data, and stores the receive data in RSR. 2. If an overrun error (when reception of the next data is completed while the RDRF flag in SSR is still set to 1) occurs, the ORER bit in SSR is set to 1. If the RIE bit in SCR is set to 1 at this time, an ERI interrupt request is generated. Receive data is not transferred to RDR. The RDRF flag remains to be set to 1. 3. If reception finishes successfully, the RDRF bit in SSR is set to 1, and receive data is transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an RXI interrupt request is generated. Because the RXI interrupt processing routine reads the receive data transferred to RDR before reception of the next receive data has finished, continuous reception can be enabled. Synchronization clock Serial data RDRF ORER RXI interrupt request generated RDR data read and RDRF flag cleared to 0 in RXI interrupt processing routine 1 frame RXI interrupt request generated ERI interrupt request generated by overrun error Bit 7 Bit 0 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 Figure 13.18 Example of Operation for Reception in Clocked Synchronous Mode Transfer cannot be resumed while a receive error flag is set to 1. Accordingly, clear the ORER, FER, PER, and RDRF bits to 0 before resuming reception. Figure 13.19 shows a sample flowchart for serial data reception. Rev. 2.00 Mar. 15, 2006 Page 459 of 754 REJ09B0199-0200 Section 13 Serial Communication Interface (SCI) Initialization Start reception [1] [1] SCI initialization: The RxD pin is automatically designated as the receive data input pin. [2] [3] Receive error processing: If a receive error occurs, read the ORER flag in SSR, and after performing the appropriate error processing, clear the ORER flag to 0. Reception cannot be resumed if the ORER flag is set to 1. [4] SCI state check and receive data read: Read SSR and check that the RDRF flag is set to 1, then read the receive data in RDR and clear the RDRF flag to 0. Transition of the RDRF flag from 0 to 1 can also be identified by an RXI interrupt. [5] Serial reception continuation procedure: To continue serial reception, before the MSB (bit 7) of the current frame is received, reading the RDRF flag, reading RDR, and clearing the RDRF flag to 0 should be finished. However, the RDRF flag is cleared automatically when the DTC or DMAC is initiated by a receive data full interrupt (RXI) and reads data from RDR. Read ORER flag in SSR Yes [2] ORER = 1 No [3] Error processing (Continued below) Read RDRF flag in SSR No [4] RDRF = 1 Yes Read receive data in RDR and clear RDRF flag in SSR to 0 No All data received Yes Clear RE bit in SCR to 0 [5] [3] Error processing Overrun error processing Clear ORER flag in SSR to 0 Figure 13.19 Sample Serial Reception Flowchart Rev. 2.00 Mar. 15, 2006 Page 460 of 754 REJ09B0199-0200 Section 13 Serial Communication Interface (SCI) 13.6.5 Simultaneous Serial Data Transmission and Reception (Clocked Synchronous Mode) Figure 13.20 shows a sample flowchart for simultaneous serial transmit and receive operations. After initializing the SCI, the following procedure should be used for simultaneous serial data transmit and receive operations. To switch from transmit mode to simultaneous transmit and receive mode, after checking that the SCI has finished transmission and the TDRE and TEND flags are set to 1, clear the TE bit to 0. Then simultaneously set both the TE and RE bits to 1 with a single instruction. To switch from receive mode to simultaneous transmit and receive mode, after checking that the SCI has finished reception, clear the RE bit to 0. Then after checking that the RDRF bit and receive error flags (ORER, FER, and PER) are cleared to 0, simultaneously set both the TE and RE bits to 1 with a single instruction. Rev. 2.00 Mar. 15, 2006 Page 461 of 754 REJ09B0199-0200 Section 13 Serial Communication Interface (SCI) Initialization Start transmission/reception [1] [1] SCI initialization: The TxD pin is designated as the transmit data output pin, and the RxD pin is designated as the receive data input pin, enabling simultaneous transmit and receive operations. [2] SCI state check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR and clear the TDRE flag to 0. Transition of the TDRE flag from 0 to 1 can also be identified by a TXI interrupt. [3] Receive error processing: If a receive error occurs, read the ORER flag in SSR, and after performing the appropriate error processing, clear the ORER flag to 0. Reception cannot be resumed if the ORER flag is set to 1. Read TDRE flag in SSR No TDRE = 1 Yes Write transmit data to TDR and clear TDRE flag in SSR to 0 [2] Read ORER flag in SSR ORER = 1 No Read RDRF flag in SSR No Yes [3] Error processing [4] [4] SCI state check and receive data read: Read SSR and check that the RDRF flag is set to 1, then read the receive data in RDR and clear the RDRF flag to 0. Transition of the RDRF flag from 0 to 1 can also be identified by an RXI interrupt. [5] Serial transmission/reception continuation procedure: To continue serial transmission/ reception, before the MSB (bit 7) of the current frame is received, finish reading the RDRF flag, reading RDR, and clearing the RDRF flag to 0. Also, before the MSB (bit 7) of the current frame is transmitted, read 1 from the TDRE flag to confirm that writing is possible. Then write data to TDR and clear the TDRE flag to 0. However, the TDRE flag is checked and cleared automatically when the DTC or DMAC is initiated by a transmit data empty interrupt (TXI) request and writes data to TDR. Similarly, the RDRF flag is cleared automatically when the DTC or DMAC is initiated by a receive data full interrupt (RXI) and reads data from RDR. RDRF = 1 Yes Read receive data in RDR, and clear RDRF flag in SSR to 0 No All data received? Yes Clear TE and RE bits in SCR to 0 [5] Note: Figure 13.20 Sample Flowchart of Simultaneous Serial Transmission and Reception Rev. 2.00 Mar. 15, 2006 Page 462 of 754 REJ09B0199-0200 Section 13 Serial Communication Interface (SCI) 13.7 Operation in Smart Card Interface Mode The SCI supports the IC card (smart card) interface, conforming to ISO/IEC 7816-3 (Identification Card) standard, as an extended serial communication interface function. Smart card interface mode can be selected using the appropriate register. 13.7.1 Sample Connection Figure 13.21 shows a sample connection between the smart card and this LSI. As in the figure, since this LSI communicates with the IC card using a single transmission line, interconnect the TxD and RxD pins and pull up the data transmission line to VCC using a resistor. Setting the RE and TE bits to 1 with the IC card not connected enables closed transmission/reception allowing self diagnosis. To supply the IC card with the clock pulses generated by the SCI, input the SCK pin output to the CLK pin of the IC card. A reset signal can be supplied via the output port of this LSI. VCC TxD RxD SCK Rx (port) This LSI Main unit of the device to be connected Data line Clock line Reset line I/O CLK RST IC card Figure 13.21 Pin Connection for Smart Card Interface Rev. 2.00 Mar. 15, 2006 Page 463 of 754 REJ09B0199-0200 Section 13 Serial Communication Interface (SCI) 13.7.2 Data Format (Except in Block Transfer Mode) Figure 13.22 shows the data transfer formats in smart card interface mode. * One frame contains 8-bit data and a parity bit in asynchronous mode. * During transmission, at least 2 etu (elementary time unit: time required for transferring one bit) is secured as a guard time after the end of the parity bit before the start of the next frame. * If a parity error is detected during reception, a low error signal is output for 1 etu after 10.5 etu has passed from the start bit. * If an error signal is sampled during transmission, the same data is automatically re-transmitted after at least 2 etu. In normal transmission/reception Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp Output from the transmitting station When a parity error is generated Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE Output from the transmitting station [Legend] Ds: Start bit D0 to D7: Data bits Output from the receiving station Dp: Parity bit DE: Error signal Figure 13.22 Data Formats in Normal Smart Card Interface Mode For communication with the IC cards of the direct convention and inverse convention types, follow the procedure below. (Z) A Ds Z D0 Z D1 A D2 Z D3 Z D4 Z D5 A D6 A D7 Z Dp (Z) state Figure 13.23 Direct Convention (SDIR = SINV = O/E = 0) Rev. 2.00 Mar. 15, 2006 Page 464 of 754 REJ09B0199-0200 Section 13 Serial Communication Interface (SCI) For the direct convention type, logic levels 1 and 0 correspond to states Z and A, respectively, and data is transferred with LSB-first as the start character, as shown in figure 13.23. Therefore, data in the start character in the figure is H'3B. When using the direct convention type, write 0 to both the SDIR and SINV bits in SCMR. Write 0 to the O/E bit in SMR in order to use even parity, which is prescribed by the smart card standard. (Z) A Ds Z D7 Z D6 A D5 A D4 A D3 A D2 A D1 A D0 Z Dp (Z) state Figure 13.24 Inverse Convention (SDIR = SINV = O/E = 1) For the inverse convention type, logic levels 1 and 0 correspond to states A and Z, respectively and data is transferred with MSB-first as the start character, as shown in figure 13.24. Therefore, data in the start character in the figure is H'3F. When using the inverse convention type, write 1 to both the SDIR and SINV bits in SCMR. The parity bit is logic level 0 to produce even parity, which is prescribed by the smart card standard, and corresponds to state Z. Since the SNIV bit of this LSI only inverts data bits D7 to D0, write 1 to the O/E bit in SMR to invert the parity bit in both transmission and reception. 13.7.3 Block Transfer Mode Block transfer mode is different from normal smart card interface mode in the following respects. * Even if a parity error is detected during reception, no error signal is output. Since the PER bit in SSR is set by error detection, clear the PER bit before receiving the parity bit of the next frame. * During transmission, at least 1 etu is secured as a guard time after the end of the parity bit before the start of the next frame. * Since the same data is not re-transmitted during transmission, the TEND flag is set 11.5 etu after transmission start. * Although the ERS flag in block transfer mode displays the error signal status as in normal smart card interface mode, the flag is always read as 0 because no error signal is transferred. Rev. 2.00 Mar. 15, 2006 Page 465 of 754 REJ09B0199-0200 Section 13 Serial Communication Interface (SCI) 13.7.4 Receive Data Sampling Timing and Reception Margin Only the internal clock generated by the on-chip baud rate generator can be used as a transfer clock in smart card interface mode. In this mode, the SCI can operate on a basic clock with a frequency of 32, 64, 372, or 256 times the bit rate according to the BCP1 and BCP0 bit settings (the frequency is always 16 times the bit rate in normal asynchronous mode). At reception, the falling edge of the start bit is sampled using the basic clock in order to perform internal synchronization. Receive data is sampled on the 16th, 32nd, 186th and 128th rising edges of the basic clock so that it can be latched at the middle of each bit as shown in figure 13.25. The reception margin here is determined by the following formula. | D - 0.5 | M = | (0.5 - 1 ) - (L - 0.5) F - (1 + F ) | x 100% 2N N M: N: D: L: F: Reception margin (%) Ratio of bit rate to clock (N = 32, 64, 372, 256) Duty cycle of clock (D = 0 to 1.0) Frame length (L = 10) Absolute value of clock frequency deviation Assuming values of F = 0, D = 0.5, and N = 372 in the above formula, the reception margin is determined by the formula below. M= ( 0.5 - 1 ) x 100% = 49.866% 2 x 372 372 clock cycles 186 clock cycles 0 Internal basic clock Receive data (RxD) Synchronization sampling timing Data sampling timing 185 371 0 185 371 0 Start bit D0 D1 Figure 13.25 Receive Data Sampling Timing in Smart Card Interface Mode (When Clock Frequency is 372 Times the Bit Rate) Rev. 2.00 Mar. 15, 2006 Page 466 of 754 REJ09B0199-0200 Section 13 Serial Communication Interface (SCI) 13.7.5 Initialization Before transmitting and receiving data, initialize the SCI using the following procedure. Initialization is also necessary before switching from transmission to reception and vice versa. 1. 2. 3. 4. 5. Clear the TE and RE bits in SCR to 0. Set the ICR bit of the corresponding pin to 1. Clear the error flags ERS, PER, and ORER in SSR to 0. Set the GM, BLK, O/E, BCP1, BCP0, CKS1, and CKS0 bits in SMR appropriately. Also set the PE bit to 1. Set the SMIF, SDIR, and SINV bits in SCMR appropriately. When the DDR corresponding to the TxD pin is cleared to 0, the TxD and RxD pins are changed from port pins to SCI pins, placing the pins into high impedance state. Set the value corresponding to the bit rate in BRR. Set the CKE1 and CKE0 bits in SCR appropriately. Clear the TIE, RIE, TE, RE, MPIE, and TEIE bits to 0 simultaneously. When the CKE0 bit is set to 1, the SCK pin is allowed to output clock pulses. Set the TIE, RIE, TE, and RE bits in SCR appropriately after waiting for at least a 1-bit interval. Setting the TE and RE bits to 1 simultaneously is prohibited except for self diagnosis. 6. 7. 8. To switch from reception to transmission, first verify that reception has completed, then initialize the SCI. At the end of initialization, RE and TE should be set to 0 and 1, respectively. Reception completion can be verified by reading the RDRF, PER, or ORER flag. To switch from transmission to reception, first verify that transmission has completed, then initialize the SCI. At the end of initialization, TE and RE should be set to 0 and 1, respectively. Transmission completion can be verified by reading the TEND flag. Rev. 2.00 Mar. 15, 2006 Page 467 of 754 REJ09B0199-0200 Section 13 Serial Communication Interface (SCI) 13.7.6 Data Transmission (Except in Block Transfer Mode) Data transmission in smart card interface mode (except in block transfer mode) is different from that in normal serial communication interface mode in that an error signal is sampled and data can be re-transmitted. Figure 13.26 shows the data re-transfer operation during transmission. 1. If an error signal from the receiving end is sampled after one frame of data has been transmitted, the ERS bit in SSR is set to 1. Here, an ERI interrupt request is generated if the RIE bit in SCR is set to 1. Clear the ERS bit to 0 before the next parity bit is sampled. 2. For the frame in which an error signal is received, the TEND bit in SSR is not set to 1. Data is re-transferred from TDR to TSR allowing automatic data retransmission. 3. If no error signal is returned from the receiving end, the ERS bit in SSR is not set to 1. 4. In this case, one frame of data is determined to have been transmitted including re-transfer, and the TEND bit in SSR is set to 1. Here, a TXI interrupt request is generated if the TIE bit in SCR is set to 1. Writing transmit data to TDR starts transmission of the next data. Figure 13.28 shows a sample flowchart for transmission. All the processing steps are automatically performed using a TXI interrupt request to activate the DTC or DMAC. In transmission, the TEND and TDRE flags in SSR are simultaneously set to 1, thus generating a TXI interrupt request if the TIE bit in SCR has been set to 1. This activates the DTC or DMAC by a TXI request thus allowing transfer of transmit data if the TXI interrupt request is specified as a source of DTC or DMAC activation beforehand. The TDRE and TEND flags are automatically cleared to 0 at data transfer by the DTC or DMAC. If an error occurs, the SCI automatically retransmits the same data. During re-transmission, TEND remains as 0, thus not activating the DTC or DMAC. Therefore, the SCI and DTC or DMAC automatically transmit the specified number of bytes, including re-transmission in the case of error occurrence. However, the ERS flag is not automatically cleared; the ERS flag must be cleared by previously setting the RIE bit to 1 to enable an ERI interrupt request to be generated at error occurrence. When transmitting/receiving data using the DTC or DMAC, be sure to set and enable the DMAC or DTC prior to making SCI settings. For DMAC or DTC settings, see section 7, DMA Controller (DMAC), and see section 8, Data Transfer Controller (DTC). Rev. 2.00 Mar. 15, 2006 Page 468 of 754 REJ09B0199-0200 Section 13 Serial Communication Interface (SCI) nth transfer frame Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE Retransfer frame Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp (DE) (n + 1) th transfer frame Ds D0 D1 D2 D3 D4 TDRE Transfer from TDR to TSR TEND [2] Transfer from TDR to TSR Transfer from TDR to TSR [4] FER/ERS [1] [3] Figure 13.26 Data Re-Transfer Operation in SCI Transmission Mode Note that the TEND flag is set in different timings depending on the GM bit setting in SMR. Figure 13.27 shows the TEND flag set timing. I/O data TXI (TEND interrupt) Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE Guard time 12.5 etu GM = 0 11.0 etu GM = 1 [Legend] Ds: D0 to D7: Dp: DE: Start bit Data bits Parity bit Error signal Figure 13.27 TEND Flag Set Timing during Transmission Rev. 2.00 Mar. 15, 2006 Page 469 of 754 REJ09B0199-0200 Section 13 Serial Communication Interface (SCI) Start Initialization Start transmission ERS = 0? Yes No Error processing No TEND = 1? Yes Write data to TDR and clear TDRE flag in SSR to 0 No All data transmitted? Yes No ERS = 0? Yes Error processing No TEND = 1? Yes Clear TE bit in SCR to 0 End Figure 13.28 Sample Transmission Flowchart Rev. 2.00 Mar. 15, 2006 Page 470 of 754 REJ09B0199-0200 Section 13 Serial Communication Interface (SCI) 13.7.7 Serial Data Reception (Except in Block Transfer Mode) Data reception in smart card interface mode is similar to that in normal serial communication interface mode. Figure 13.29 shows the data re-transfer operation during reception. 1. If a parity error is detected in receive data, the PER bit in SSR is set to 1. Here, an ERI interrupt request is generated if the RIE bit in SCR is set to 1. Clear the PER bit to 0 before the next parity bit is sampled. 2. For the frame in which a parity error is detected, the RDRF bit in SSR is not set to 1. 3. If no parity error is detected, the PER bit in SSR is not set to 1. 4. In this case, data is determined to have been received successfully, and the RDRF bit in SSR is set to 1. Here, an RXI interrupt request is generated if the RIE bit in SCR is set to 1. Figure 13.30 shows a sample flowchart for reception. All the processing steps are automatically performed using an RXI interrupt request to activate the DTC or DMAC. In reception, setting the RIE bit to 1 allows an RXI interrupt request to be generated when the RDRF flag is set to 1. This activates the DTC or DMAC by an RXI request thus allowing transfer of receive data if the RXI interrupt request is specified as a source of DTC or DMAC activation beforehand. The RDRF flag is automatically cleared to 0 at data transfer by the DTC or DMAC. If an error occurs during reception, i.e., either the ORER or PER flag is set to 1, a transmit/receive error interrupt (ERI) request is generated and the error flag must be cleared. If an error occurs, the DTC or DMAC is not activated and receive data is skipped, therefore, the number of bytes of receive data specified in the DTC or DMAC is transferred. Even if a parity error occurs and the PER bit is set to 1 in reception, receive data is transferred to RDR, thus allowing the data to be read. Note: For operations in block transfer mode, see section 13.4, Operation in Asynchronous Mode. (n + 1) th transfer frame (DE) Ds D0 D1 D2 D3 D4 nth transfer frame Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE RDRF [2] PER [1] Retransfer frame Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp [4] [3] Figure 13.29 Data Re-Transfer Operation in SCI Reception Mode Rev. 2.00 Mar. 15, 2006 Page 471 of 754 REJ09B0199-0200 Section 13 Serial Communication Interface (SCI) Start Initialization Start reception ORER = 0 and PER = 0? Yes No RDRF = 1? Yes Read data from RDR and clear RDRF flag in SSR to 0 No No Error processing All data received? Yes Clear RE bit in SCR to 0 Figure 13.30 Sample Reception Flowchart 13.7.8 Clock Output Control Clock output can be fixed using the CKE1 and CKE0 bits in SCR when the GM bit in SMR is set to 1. Specifically, the minimum width of a clock pulse can be specified. Figure 13.31 shows an example of clock output fixing timing when the CKE0 bit is controlled with GM = 1 and CKE1 = 0. CKE0 SCK Given pulse width Given pulse width Figure 13.31 Clock Output Fixing Timing Rev. 2.00 Mar. 15, 2006 Page 472 of 754 REJ09B0199-0200 Section 13 Serial Communication Interface (SCI) At power-on and transitions to/from software standby mode, use the following procedure to secure the appropriate clock duty cycle. * At power-on To secure the appropriate clock duty cycle simultaneously with power-on, use the following procedure. 1. Initially, port input is enabled in the high-impedance state. To fix the potential level, use a pull-up or pull-down resistor. 2. Fix the SCK pin to the specified output using the CKE1 bit in SCR. 3. Set SMR and SCMR to enable smart card interface mode. Set the CKE0 bit in SCR to 1 to start clock output. * At mode switching At transition from smart card interface mode to software standby mode 1. Set the data register (DR) and data direction register (DDR) corresponding to the SCK pin to the values for the output fixed state in software standby mode. 2. Write 0 to the TE and RE bits in SCR to stop transmission/reception. Simultaneously, set the CKE1 bit to the value for the output fixed state in software standby mode. 3. Write 0 to the CKE0 bit in SCR to stop the clock. 4. Wait for one cycle of the serial clock. In the mean time, the clock output is fixed to the specified level with the duty cycle retained. 5. Make the transition to software standby mode. At transition from smart card interface mode to software standby mode 6. Clear software standby mode. 7. Write 1 to the CKE0 bit in SCR to start clock output. A clock signal with the appropriate duty cycle is then generated. Software standby Normal operation Normal operation [1] [2] [3] [4] [5] [6] [7] Figure 13.32 Clock Stop and Restart Procedure Rev. 2.00 Mar. 15, 2006 Page 473 of 754 REJ09B0199-0200 Section 13 Serial Communication Interface (SCI) 13.8 13.8.1 Interrupt Sources Interrupts in Normal Serial Communication Interface Mode Table 13.12 shows the interrupt sources in normal serial communication interface mode. A different interrupt vector is assigned to each interrupt source, and individual interrupt sources can be enabled or disabled using the enable bits in SCR. When the TDRE flag in SSR is set to 1, a TXI interrupt request is generated. When the TEND flag in SSR is set to 1, a TEI interrupt request is generated. A TXI interrupt request can activate the DTC or DMAC to allow data transfer. The TDRE flag is automatically cleared to 0 at data transfer by the DTC or DMAC. When the RDRF flag in SSR is set to 1, an RXI interrupt request is generated. When the ORER, PER, or FER flag in SSR is set to 1, an ERI interrupt request is generated. An RXI interrupt can activate the DTC or DMAC to allow data transfer. The RDRF flag is automatically cleared to 0 at data transfer by the DTC or DMAC. A TEI interrupt is requested when the TEND flag is set to 1 while the TEIE bit is set to 1. If a TEI interrupt and a TXI interrupt are requested simultaneously, the TXI interrupt has priority for acceptance. However, note that if the TDRE and TEND flags are cleared to 0 simultaneously by the TXI interrupt processing routine, the SCI cannot branch to the TEI interrupt processing routine later. Table 13.12 SCI Interrupt Sources Name ERI RXI TXI TEI Interrupt Source Receive error Receive data full Interrupt Flag DTC Activation DMAC Activation Priority Not possible Possible Possible Not possible Low High ORER, FER, or PER Not possible RDRF Possible Possible Not possible Transmit data empty TDRE Transmit end TEND Rev. 2.00 Mar. 15, 2006 Page 474 of 754 REJ09B0199-0200 Section 13 Serial Communication Interface (SCI) 13.8.2 Interrupts in Smart Card Interface Mode Table 13.13 shows the interrupt sources in smart card interface mode. A transmit end (TEI) interrupt request cannot be used in this mode. Table 13.13 SCI Interrupt Sources Name Interrupt Source ERI RXI TXI Interrupt Flag DTC Activation DMAC Activation Priority Not possible Possible Possible Low High Receive error or ORER, PER, or ERS Not possible error signal detection Receive data full RDRF Possible Possible Transmit data empty TDRE Data transmission/reception using the DTC or DMAC is also possible in smart card interface mode, similar to in the normal SCI mode. In transmission, the TEND and TDRE flags in SSR are simultaneously set to 1, thus generating a TXI interrupt. This activates the DTC or DMAC by a TXI request thus allowing transfer of transmit data if the TXI request is specified as a source of DTC or DMAC activation beforehand. The TDRE and TEND flags are automatically cleared to 0 at data transfer by the DTC or DMAC. If an error occurs, the SCI automatically re-transmits the same data. During re-transmission, the TEND flag remains as 0, thus not activating the DTC or DMAC. Therefore, the SCI and DTC or DMAC automatically transmit the specified number of bytes, including re-transmission in the case of error occurrence. However, the ERS flag in SSR, which is set at error occurrence, is not automatically cleared; the ERS flag must be cleared by previously setting the RIE bit in SCR to 1 to enable an ERI interrupt request to be generated at error occurrence. When transmitting/receiving data using the DTC or DMAC, be sure to set and enable the DTC or DMAC prior to making SCI settings. For DTC or DMAC settings, see section 7, DMA Controller (DMAC), and see section 8, Data Transfer Controller (DTC). In reception, an RXI interrupt request is generated when the RDRF flag in SSR is set to 1. This activates the DTC or DMAC by an RXI request thus allowing transfer of receive data if the RXI request is specified as a source of DTC or DMAC activation beforehand. The RDRF flag is automatically cleared to 0 at data transfer by the DTC or DMAC. If an error occurs, the RDRF flag is not set but the error flag is set. Therefore, the DTC or DMAC is not activated and an ERI interrupt request is issued to the CPU instead; the error flag must be cleared. Rev. 2.00 Mar. 15, 2006 Page 475 of 754 REJ09B0199-0200 Section 13 Serial Communication Interface (SCI) 13.9 13.9.1 Usage Notes Module Stop Mode Setting Operation of the SCI can be disabled or enabled using the module stop control register. The initial setting is for operation of the SCI to be halted. Register access is enabled by clearing module stop mode. For details, refer to section 19, Power-Down Modes. 13.9.2 Break Detection and Processing When framing error detection is performed, a break can be detected by reading the RxD pin value directly. In a break, the input from the RxD pin becomes all 0s, and so the FER flag is set, and the PER flag may also be set. Note that, since the SCI continues the receive operation even after receiving a break, even if the FER flag is cleared to 0, it will be set to 1 again. 13.9.3 Mark State and Break Detection When the TE bit is 0, the TxD pin is used as an I/O port whose direction (input or output) and level are determined by DR and DDR. This can be used to set the TxD pin to mark state (high level) or send a break during serial data transmission. To maintain the communication line in mark state (the state of 1) until TE is set to 1, set both DDR and DR to 1. Since the TE bit is cleared to 0 at this point, the TxD pin becomes an I/O port, and 1 is output from the TxD pin. To send a break during serial transmission, first set DDR to 1 and DR to 0, and then clear the TE bit to 0. When the TE bit is cleared to 0, the transmitter is initialized regardless of the current transmission state, the TxD pin becomes an I/O port, and 0 is output from the TxD pin. 13.9.4 Receive Error Flags and Transmit Operations (Clocked Synchronous Mode Only) Transmission cannot be started when a receive error flag (ORER, FER, or RER) is set to 1, even if the TDRE flag is cleared to 0. Be sure to clear the receive error flags to 0 before starting transmission. Note also that the receive error flags cannot be cleared to 0 even if the RE bit is cleared to 0. Rev. 2.00 Mar. 15, 2006 Page 476 of 754 REJ09B0199-0200 Section 13 Serial Communication Interface (SCI) 13.9.5 Relation between Writing to TDR and TDRE Flag The TDRE flag in SSR is a status flag which indicates that transmit data has been transferred from TDR to TSR. When the SCI transfers data from TDR to TSR, the TDRE flag is set to 1. Data can be written to TDR irrespective of the TDRE flag status. However, if new data is written to TDR when the TDRE flag is 0, that is, when the previous data has not been transferred to TSR yet, the previous data in TDR is lost. Be sure to write transmit data to TDR after verifying that the TDRE flag is set to 1. 13.9.6 Restrictions on Using DTC or DMAC * When the external clock source is used as a synchronization clock, update TDR by the DTC or DMAC and wait for at least five P clock cycles before allowing the transmit clock to be input. If the transmit clock is input within four clock cycles after TDR modification, the SCI may malfunction (figure 13.33). * When using the DTC or DMAC to read RDR, be sure to set the receive end interrupt (RXI) as the DMAC activation source. SCK t TDRE LSB Serial data D0 D1 D2 D3 D4 D5 D6 D7 Note: When external clock is supplied, t must be more than four clock cycles. Figure 13.33 Sample Transmission using DTC or DMAC in Clocked Synchronous Mode Rev. 2.00 Mar. 15, 2006 Page 477 of 754 REJ09B0199-0200 Section 13 Serial Communication Interface (SCI) 13.9.7 (1) SCI Operations during Mode Transitions Transmission Before making the transition to module stop mode or software standby mode, stop the transmit operations (TE = TIE = TEIE = 0). TSR, TDR, and SSR are reset. The states of the output pins during module stop mode or software standby mode depend on the port settings, and the pins output a high-level signal after mode cancellation. If the transition is made during data transmission, the data being transmitted will be undefined. To transmit data in the same transmission mode after mode cancellation, set the TE bit to 1, read SSR, write to TDR, clear TDRE in this order, and then start transmission. To transmit data in a different transmission mode, initialize the SCI first. Figure 13.34 shows a sample flowchart for mode transition during transmission. Figures 13.35 and 13.36 show the port pin states during mode transition. Before making the transition from the transmission mode using DTC transfer to module stop mode or software standby mode, stop all transmit operations (TE = TIE = TEIE = 0). Setting the TE and TIE bits to 1 after mode cancellation sets the TXI flag to start transmission using the DTC. (2) Reception Before making the transition to module stop mode or software standby mode, stop the receive operations (RE = 0). RSR, RDR, and SSR are reset. If transition is made during data reception, the data being received will be invalid. To receive data in the same reception mode after mode cancellation, set the RE bit to 1, and then start reception. To receive data in a different reception mode, initialize the SCI first. Figure 13.37 shows a sample flowchart for mode transition during reception. Rev. 2.00 Mar. 15, 2006 Page 478 of 754 REJ09B0199-0200 Section 13 Serial Communication Interface (SCI) Transmission All data transmitted? Yes Read TEND flag in SSR No [1] TEND = 1 Yes TE = 0 [2] No [1] Data being transmitted is lost halfway. Data can be normally transmitted from the CPU by setting the TE bit to 1, reading SSR, writing to TDR, and clearing the TDRE bit to 0 after clearing software standby mode; however, if the DTC has been activated, the data remaining in the RAM of the DTC will be transmitted when both TE and TIE bits are set to 1. [2] Clear the TIE and TEIE bits to 0 when they are 1. Make transition to software standby mode Cancel software standby mode [3] [3] Module stop mode is included. Change operating mode? Yes Initialization No TE = 1 Start transmission Figure 13.34 Sample Flowchart for Mode Transition during Transmission Transition to Software standby Transmission end software standby mode canceled mode Transmission start TE bit SCK output pin TxD output pin Port input/output Port input/output High output Start SCI TxD output Stop Port input/output Port High output SCI TxD output Port Figure 13.35 Port Pin States during Mode Transition (Internal Clock, Asynchronous Transmission) Rev. 2.00 Mar. 15, 2006 Page 479 of 754 REJ09B0199-0200 Section 13 Serial Communication Interface (SCI) Transmission start Transmission end Transition to Software standby software standby mode canceled mode TE bit SCK output pin TxD output pin Port input/output Port input/output Marking output SCI TxD output Last TxD bit retained Port input/output Port High output* SCI TxD output Port Note: * Initialized in software standby mode Figure 13.36 Port Pin States during Mode Transition (Internal Clock, Clocked Synchronous Transmission) Reception Read RDRF flag in SSR RDRF = 1 Yes Read receive data in RDR No [1] [1] Data being received will be invalid. [2] Module stop mode is included. RE = 0 Make transition to software standby mode Cancel software standby mode [2] Change operating mode? Yes Initialization No RE = 1 Start reception Figure 13.37 Sample Flowchart for Mode Transition during Reception Rev. 2.00 Mar. 15, 2006 Page 480 of 754 REJ09B0199-0200 Section 14 Synchronous Serial Communication Unit (SSU) Section 14 Synchronous Serial Communication Unit (SSU) This LSI has three independent synchronous serial communication unit (SSU) channels. The SSU has master mode in which this LSI outputs clocks as a master device for synchronous serial communication and slave mode in which clocks are input from an external device for synchronous serial communication. Synchronous serial communication can be performed with devices having different clock polarity and clock phase. Figure 14.1 is a block diagram of the SSU. 14.1 * * * * * * Features * * * * * Choice of SSU mode and clock synchronous mode Choice of master mode and slave mode Choice of standard mode and bidirectional mode Synchronous serial communication with devices with different clock polarity and clock phase Choice of 8/16/32-bit width of transmit/receive data Full-duplex communication capability The shift register is incorporated, enabling transmission and reception to be executed simultaneously. Consecutive serial communication Choice of LSB-first or MSB-first transfer Choice of a clock source P/4, P/8, P/16, P/32, P/64, P/128, P/256, or an external clock Five interrupt sources transmit-end, transmit-data-register-empty, receive-data-full, overrun-error, and conflict error Module stop mode can be set* Note: * Module stop mode has usage notes. For details, see section 14.6.2, Note on Clearing Module Stop Mode. Rev. 2.00 Mar. 15, 2006 Page 481 of 754 REJ09B0199-0200 Section 14 Synchronous Serial Communication Unit (SSU) Figure 14.1 shows a block diagram of the SSU. Module data bus Bus interface Internal data bus SSCRH SSTDR 0 SSTDR 1 SSTDR 2 SSTDR 3 SSRDR 0 SSRDR 1 SSRDR 2 SSRDR 3 SSCRL SSMR SSER SSSR Control circuit OEI CEI RXI TXI TEI SSTRSR Shiftout Shiftin Clock Clock selector P P/4 P/8 P/16 P/32 P/64 P/128 P/256 Selector SSI [Legend] SSCRH: SSCRL: SSCR2: SSMR: SSER: SSSR: SSTDR0 to SSTDR3: SSRDR0 to SSRDR3: SSTRSR: SSO SCS SSCK (External clock) SS control register H SS control register L SS control register 2 SS mode register SS enable register SS status register SS transmit data registers 0 to 3 SS receive data registers 0 to 3 SS shift register Figure 14.1 Block Diagram of SSU Rev. 2.00 Mar. 15, 2006 Page 482 of 754 REJ09B0199-0200 Section 14 Synchronous Serial Communication Unit (SSU) 14.2 Input/Output Pins Table 14.1 shows the SSU pin configuration. Table 14.1 Pin Configuration Channel 0 Abbr.* SSCK0 SSI0 SSO0 SCS0 1 SSCK1 SSI1 SSO1 SCS1 2 SSCK2 SSI2 SSO2 SCS2 Note: * I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Function Channel 0 SSU clock input/output Channel 0 SSU data input/output Channel 0 SSU data input/output Channel 0 SSU chip select input/output Channel 1 SSU clock input/output Channel 1 SSU data input/output Channel 1 SSU data input/output Channel 1 SSU chip select input/output Channel 2 SSU clock input/output Channel 2 SSU data input/output Channel 2 SSU data input/output Channel 2 SSU chip select input/output Because channel numbers are omitted in later descriptions, these are shown SSCK, SSI, SSO, and SCS. Rev. 2.00 Mar. 15, 2006 Page 483 of 754 REJ09B0199-0200 Section 14 Synchronous Serial Communication Unit (SSU) 14.3 Register Descriptions The SSU has the following registers. Channel 0: * * * * * * * * * * * * * * * SS control register H_0 (SSCRH_0) SS control register L_0 (SSCRL_0) SS mode register_0 (SSMR_0) SS enable register_0 (SSER_0) SS status register_0 (SSSR_0) SS control register 2_0 (SSCR2_0) SS transmit data register 0_0 (SSTDR0_0) SS transmit data register 1_0 (SSTDR1_0) SS transmit data register 2_0 (SSTDR2_0) SS transmit data register 3_0 (SSTDR3_0) SS receive data register 0_0 (SSRDR0_0) SS receive data register 1_0 (SSRDR1_0) SS receive data register 2_0 (SSRDR2_0) SS receive data register 3_0 (SSRDR3_0) SS shift register_0 (SSTRSR_0) Rev. 2.00 Mar. 15, 2006 Page 484 of 754 REJ09B0199-0200 Section 14 Synchronous Serial Communication Unit (SSU) Channel 1: * * * * * * * * * * * * * * * SS control register H_1 (SSCRH_1) SS control register L_1 (SSCRL_1) SS mode register_1 (SSMR_1) SS enable register_1 (SSER_1) SS status register_1 (SSSR_1) SS control register 2_1 (SSCR2_1) SS transmit data register 0_1 (SSTDR0_1) SS transmit data register 1_1 (SSTDR1_1) SS transmit data register 2_1 (SSTDR2_1) SS transmit data register 3_1 (SSTDR3_1) SS receive data register 0_1 (SSRDR0_1) SS receive data register 1_1 (SSRDR1_1) SS receive data register 2_1 (SSRDR2_1) SS receive data register 3_1 (SSRDR3_1) SS shift register_1 (SSTRSR_1) Channel 2: * * * * * * * * * * * * * * * SS control register H_2 (SSCRH_2) SS control register L_2 (SSCRL_2) SS mode register_2 (SSMR_2) SS enable register_2 (SSER_2) SS status register_2 (SSSR_2) SS control register 2_2 (SSCR2_2) SS transmit data register 0_2 (SSTDR0_2) SS transmit data register 1_2 (SSTDR1_2) SS transmit data register 2_2 (SSTDR2_2) SS transmit data register 3_2 (SSTDR3_2) SS receive data register 0_2 (SSRDR0_2) SS receive data register 1_2 (SSRDR1_2) SS receive data register 2_2 (SSRDR2_2) SS receive data register 3_2 (SSRDR3_2) SS shift register_2 (SSTRSR_2) Rev. 2.00 Mar. 15, 2006 Page 485 of 754 REJ09B0199-0200 Section 14 Synchronous Serial Communication Unit (SSU) 14.3.1 SS Control Register H (SSCRH) SSCRH specifies master/slave device selection, bidirectional mode enable, SSO pin output value selection, SSCK pin selection, and SCS pin selection. Bit Bit Name Initial Value R/W 7 MSS 0 R/W 6 BIDE 0 R/W 5 -- 0 R/W 4 SOL 0 R/W 3 SOLP 1 R/W 2 SCKS 0 R/W 1 CSS1 0 R/W 0 CSS0 0 R/W Bit 7 Bit Name MSS Initial Value 0 R/W R/W Description Master/Slave Device Select Selects that this module is used in master mode or slave mode. When master mode is selected, transfer clocks are output from the SSCK pin. When the CE bit in SSSR is set, this bit is automatically cleared. 0: Slave mode is selected. 1: Master mode is selected. 6 BIDE 0 R/W Bidirectional Mode Enable Selects that both serial data input pin and output pin are used or one of them is used. However, transmission and reception are not performed simultaneously when bidirectional mode is selected. For details, section 14.4.3, Relationship between Data Input/Output Pins and Shift Register. 0: Standard mode (two pins are used for data input and output) 1: Bidirectional mode (one pin is used for data input and output) 5 0 R/W Reserved This bit is always read as 0. The write value should always be 0. Rev. 2.00 Mar. 15, 2006 Page 486 of 754 REJ09B0199-0200 Section 14 Synchronous Serial Communication Unit (SSU) Bit 4 Bit Name SOL Initial Value 0 R/W R/W Description Serial Data Output Value Select The serial data output retains its level of the last bit after completion of transmission. The output level before or after transmission can be specified by setting this bit. When specifying the output level, use the MOV instruction after clearing the SOLP bit to 0. Since writing to this bit during data transmission causes malfunctions, this bit should not be changed. 0: Serial data output is changed to low. 1: Serial data output is changed to high. 3 SOLP 1 R/W SOL Bit Write Protect When changing the output level of serial data, set the SOL bit to 1 or clear the SOL bit to 0 after clearing the SOLP bit to 0 using the MOV instruction. 0: Output level can be changed by the SOL bit 1: Output level cannot be changed by the SOL bit. This bit is always read as 1. 2 SCKS 0 R/W SSCK Pin Select Selects that the SSCK pin functions as a port or a serial clock pin. When the SSCK pin is used as a serial clock pin, this bit must be set to 1. 0: Functions as an I/O port. 1: Functions as a serial clock. 1 0 CSS1 CSS0 0 0 R/W R/W SCS Pin Select Select that the SCS pin functions as a port or SCS input or output. However, when MSS = 0, the SCS pin functions as an input pin regardless of the CSS1 and CSS0 settings. 00: I/O port 01: Function as SCS input 10: Function as SCS automatic input/output (function as SCS input before and after transfer and output a low level during transfer) 11: Function as SCS automatic output (outputs a high level before and after transfer and outputs a low level during transfer) Rev. 2.00 Mar. 15, 2006 Page 487 of 754 REJ09B0199-0200 Section 14 Synchronous Serial Communication Unit (SSU) 14.3.2 SS Control Register L (SSCRL) SSCRL selects operating mode, software reset, and transmit/receive data length. Bit Bit Name Initial Value R/W 7 -- 0 R/W 6 SSUMS 0 R/W 5 SRES 0 R/W 4 -- 0 R/W 3 -- 0 R/W 2 -- 0 R/W 1 DATS1 0 R/W 0 DATS0 0 R/W Bit 7 Bit Name Initial Value 0 R/W R/W Description Reserved This bit is always read as 0. The write value should always be 0. 6 SSUMS 0 R/W Selects transfer mode from SSU mode and clock synchronous mode. 0: SSU mode 1: Clock synchronous mode 5 SRES 0 R/W Software Reset Setting this bit to 1 forcibly resets the SSU internal sequencer. After that, this bit is automatically cleared. The ORER, TEND, TDRE, RDRF, and CE bits in SSSR and the TE and RE bits in SSER are also initialized. Values of other bits for SSU registers are held. To stop transfer, set this bit to 1 to reset the SSU internal sequencer. 4 to 2 All 0 R/W Reserved These bits are always read as 0. The write value should always be 0. 1 0 DATS1 DATS0 0 0 R/W R/W Transmit/Receive Data Length Select Select serial data length. 00: 8 bits 01: 16 bits 10: 32 bits 11: Setting prohibited Rev. 2.00 Mar. 15, 2006 Page 488 of 754 REJ09B0199-0200 Section 14 Synchronous Serial Communication Unit (SSU) 14.3.3 SS Mode Register (SSMR) SSMR selects the MSB first/LSB first, clock polarity, clock phase, and clock rate of synchronous serial communication. Bit Bit Name Initial Value R/W 7 MLS 0 R/W 6 CPOS 0 R/W 5 CPHS 0 R/W 4 -- 0 R/W 3 -- 0 R/W 2 CKS2 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W Bit 7 Bit Name MLS Initial Value 0 R/W R/W Description MSB First/LSB First Select Selects that the serial data is transmitted in MSB first or LSB first. 0: LSB first 1: MSB first 6 CPOS 0 R/W Clock Polarity Select Selects the SSCK clock polarity. 0: High output in idle mode, and low output in active mode 1: Low output in idle mode, and high output in active mode 5 CPHS 0 R/W Clock Phase Select (Only for SSU Mode) Selects the SSCK clock phase. 0: Data changes at the first edge. 1: Data is latched at the first edge. 4, 3 All 0 R/W Reserved These bits are always read as 0. The write value should always be 0. Rev. 2.00 Mar. 15, 2006 Page 489 of 754 REJ09B0199-0200 Section 14 Synchronous Serial Communication Unit (SSU) Bit 2 1 0 Bit Name CKS2 CKS1 CKS0 Initial Value 0 0 0 R/W R/W R/W R/W Description Transfer Clock Rate Select Select the transfer clock rate (prescaler division rate) when an internal clock is selected. 000: Reserved 001: P/4 010: P/8 011: P/16 100: P/32 101: P/64 110: P/128 111: P/256 14.3.4 SS Enable Register (SSER) SSER performs transfer/receive control of synchronous serial communication and setting of interrupt enable. Bit Bit Name Initial Value R/W 7 TE 0 R/W 6 RE 0 R/W 5 -- 0 R/W 4 -- 0 R/W 3 TEIE 0 R/W 2 TIE 0 R/W 1 RIE 0 R/W 0 CEIE 0 R/W Bit 7 6 5, 4 Bit Name TE RE Initial Value 0 0 All 0 R/W R/W R/W R/W Description Transmit Enable When this bit is set to 1, transmission is enabled. Receive Enable When this bit is set to 1, reception is enabled. Reserved These bits are always read as 0. The write value should always be 0. 3 TEIE 0 R/W Transmit End Interrupt Enable When this bit is set to 1, a TEI interrupt request is enabled. Rev. 2.00 Mar. 15, 2006 Page 490 of 754 REJ09B0199-0200 Section 14 Synchronous Serial Communication Unit (SSU) Bit 2 Bit Name TIE Initial Value 0 R/W R/W Description Transmit Interrupt Enable When this bit is set to 1, a TXI interrupt request is enabled. 1 RIE 0 R/W Receive Interrupt Enable When this bit is set to 1, an RXI interrupt request and an OEI interrupt request are enabled. 0 CEIE 0 R/W Conflict Error Interrupt Enable When this bit is set to 1, a CEI interrupt request is enabled. 14.3.5 SS Status Register (SSSR) SSSR is a status flag register for interrupts. Bit Bit Name Initial Value R/W 7 -- 0 R/W 6 ORER 0 R/W 5 -- 0 R/W 4 -- 0 R/W 3 TEND 0 R/W 2 TDRE 1 R/W 1 RDRF 0 R/W 0 CE 0 R/W Bit 7 Bit Name Initial Value 0 R/W Description Reserved This bit is always read as 0. The write value should always be 0. Rev. 2.00 Mar. 15, 2006 Page 491 of 754 REJ09B0199-0200 Section 14 Synchronous Serial Communication Unit (SSU) Bit 6 Bit Name ORER Initial Value 0 R/W R/W Description Overrun Error If the next data is received while RDRF = 1, an overrun error occurs, indicating abnormal termination. SSRDR stores 1-frame receive data before an overrun error occurs and loses data to be received later. While ORER = 1, consecutive serial reception cannot be continued. Serial transmission cannot be continued, either. [Setting condition] * When one byte of the next reception is completed with RDRF = 1 When writing 0 after reading ORER = 1 (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) [Clearing condition] * 5, 4 All 0 R/W Reserved These bits are always read as 0. The write value should always be 0. 3 TEND 1 R Transmit End [Setting condition] * When the last bit of transmit data is transmitted while the TENDSTS bit in SSCR2 is cleared to 0 and the TDRE bit is set to 1 After the last bit of transmit data is transmitted while the TENDSTS bit in SSCR2 is set to 1 and the TDRE bit is set to 1 When writing 0 after reading TEND = 1 (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) * When writing data to SSTDR * [Clearing conditions] * Rev. 2.00 Mar. 15, 2006 Page 492 of 754 REJ09B0199-0200 Section 14 Synchronous Serial Communication Unit (SSU) Bit 2 Bit Name TDRE Initial Value 1 R/W R/W Description Transmit Data Empty Indicates whether or not SSTDR contains transmit data. [Setting conditions] * * When the TE bit in SSER is 0 When data is transferred from SSTDR to SSTRSR and SSTDR is ready to be written to. When writing 0 after reading TDRE = 1 (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) * When writing data to SSTDR with TE = 1 [Clearing conditions] * 1 RDRF 0 R/W Receive Data Register Full Indicates whether or not SSRDR contains receive data. [Setting condition] * When receive data is transferred from SSTRSR to SSRDR after successful serial data reception When writing 0 after reading RDRF = 1 (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) * When reading receive data from SSRDR [Clearing conditions] * Rev. 2.00 Mar. 15, 2006 Page 493 of 754 REJ09B0199-0200 Section 14 Synchronous Serial Communication Unit (SSU) Bit 0 Bit Name CE Initial Value 0 R/W R/W Description Conflict/Incomplete Error Indicates that a conflict error has occurred when 0 is externally input to the SCS pin with SSUMS = 0 (SSU mode) and MSS = 1 (master mode). If the SCS pin level changes to 1 with SSUMS = 0 (SSU mode) and MSS = 0 (slave mode), an incomplete error occurs because it is determined that a master device has terminated the transfer. Data reception does not continue while the CE bit is set to 1. Serial transmission also does not continue. Reset the SSU internal sequencer by setting the SRES bit in SSCRL to 1 before resuming transfer after incomplete error. [Setting condition] * * When a low level is input to the SCS pin in master mode (the MSS bit in SSCRH is set to 1) When the SCS pin is changed to 1 during transfer in slave mode (the MSS bit in SSCRH is cleared to 0) When writing 0 after reading CE = 1 (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) [Clearing condition] * Rev. 2.00 Mar. 15, 2006 Page 494 of 754 REJ09B0199-0200 Section 14 Synchronous Serial Communication Unit (SSU) 14.3.6 SS Control Register 2 (SSCR2) SSCR2 is a register that enables/disables the open-drain outputs of the SSO, SSI, SSCK, and SCS pins, selects the assert timing of the SCS pin, data output timing of the SSO pin, and set timing of the TEND bit. Bit Bit Name Initial Value R/W 7 SDOS 0 R/W 6 SSCKOS 0 R/W 5 SCSOS 0 R/W 4 TENDSTS 0 R/W 3 SCSATS 0 R/W 2 SSODTS 0 R/W 1 -- 0 R/W 0 -- 0 R/W Bit 7 Bit Name SDOS Initial Value 0 R/W R/W Description Serial Data Pin Open Drain Select Selects whether the serial data output pin is used as a CMOS or an NMOS open drain output. Pins to output serial data differ according to the register setting. For details, 14.4.3, Relationship between Data Input/Output Pins and Shift Register. 0: CMOS output 1: NMOS open drain output 6 SSCKOS 0 R/W SSCK Pin Open Drain Select Selects whether the SSCK pin is used as a CMOS or an NMOS open drain output. 0: CMOS output 1: NMOS open drain output 5 SCSOS 0 R/W SCS Pin Open Drain Select Selects whether the SCS pin is used as a CMOS or an NMOS open drain output. 0: CMOS output 1: NMOS open drain output 4 TENDSTS 0 R/W Selects the timing of setting the TEND bit (valid in SSU and master mode). 0: Sets the TEND bit when the last bit is being transmitted 1: Sets the TEND bit after the last bit is transmitted Rev. 2.00 Mar. 15, 2006 Page 495 of 754 REJ09B0199-0200 Section 14 Synchronous Serial Communication Unit (SSU) Bit 3 Bit Name SCSATS Initial Value 0 R/W R/W Description Selects the assertion timing of the SCS pin (valid in SSU and master mode). 0: Min. values of tLEAD and tLAG are 1/2 x tSUcyc 1: Min. values of tLEAD and tLAG are 3/2 x tSUcyc 2 SSODTS 0 R/W Selects the data output timing of the SSO pin (valid in SSU and master mode) 0: While BIDE = 0, MSS = 1, and TE = 1 or while BIDE = 1, TE = 1, and RE = 0, the SSO pin outputs data 1: While BIDE = 0, MSS = 1, and TE = 1 or while BIDE = 1, TE = 1, and RE = 0, the SSO pin outputs data while the SCS pin is driven low 1, 0 All 0 R/W Reserved These bits are always read as 0. The write value should always be 0. 14.3.7 SS Transmit Data Registers 0 to 3 (SSTDR0 to SSTDR3) SSTDR is an 8-bit register that stores transmit data. When 8-bit data length is selected by bits DATS1 and DATS0 in SSCRL, SSTDR0 is valid. When 16-bit data length is selected, SSTDR0 and SSTDR1 are valid. When 32-bit data length is selected, SSTDR0 to SSTDR3 are valid. Be sure not to access invalid SSTDRs. When the SSU detects that SSTRSR is empty, it transfers the transmit data written in SSTDR to SSTRSR and starts serial transmission. If the next transmit data has already been written to SSTDR during serial transmission, the SSU performs consecutive serial transmission. Although SSTDR can always be read from or written to by the CPU, DTC, or DMAC, to achieve reliable serial transmission, write transmit data to SSTDR after confirming that the TDRE bit in SSSR is set to 1. Rev. 2.00 Mar. 15, 2006 Page 496 of 754 REJ09B0199-0200 Section 14 Synchronous Serial Communication Unit (SSU) Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 7 6 5 4 3 2 1 0 Table 14.2 Correspondence Between DATS Bit Setting and SSTDR DATS[1:0] (SSCRL[1:0]) SSTDR 0 1 2 3 00 Valid Invalid Invalid Invalid 01 Valid Valid Invalid Invalid 10 Valid Valid Valid Valid 11 (Setting Invalid) Invalid Invalid Invalid Invalid Rev. 2.00 Mar. 15, 2006 Page 497 of 754 REJ09B0199-0200 Section 14 Synchronous Serial Communication Unit (SSU) 14.3.8 SS Receive Data Registers 0 to 3 (SSRDR0 to SSRDR3) SSRDR is an 8-bit register that stores receive data. When 8-bit data length is selected by bits DATS1 and DATS0 in SSCRL, SSRDR0 is valid. When 16-bit data length is selected, SSRDR0 and SSRDR1 are valid. When 32-bit data length is selected, SSRDR0 to SSRDR3 are valid. Be sure not to access invalid SSRDRs. When the SSU has received 1-byte data, it transfers the received serial data from SSTRSR to SSRDR where it is stored. After this, SSTRSR is ready for reception. Since SSTRSR and SSRDR function as a double buffer in this way, consecutive receive operations can be performed. Read SSRDR after confirming that the RDRF bit in SSSR is set to 1. SSRDR is a read-only register, therefore, cannot be written to by the CPU. Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 7 0 R 6 0 R 5 0 R 4 0 R 3 0 R 2 0 R 1 0 R 0 0 R 7 0 R 6 0 R 5 0 R 4 0 R 3 0 R 2 0 R 1 0 R 0 0 R 7 0 R 6 0 R 5 0 R 4 0 R 3 0 R 2 0 R 1 0 R 0 7 6 5 4 3 2 1 0 Rev. 2.00 Mar. 15, 2006 Page 498 of 754 REJ09B0199-0200 Section 14 Synchronous Serial Communication Unit (SSU) Table 14.3 Correspondence Between DATS Bit Setting and SSRDR DATS[1:0] (SSCRL[1:0]) SSRDR 0 1 2 3 00 Valid Invalid Invalid Invalid 01 Valid Valid Invalid Invalid 10 Valid Valid Valid Valid 11 (Setting Invalid) Invalid Invalid Invalid Invalid 14.3.9 SS Shift Register (SSTRSR) SSTRSR is a shift register that transmits and receives serial data. When data is transferred from SSTDR to SSTRSR, bit 0 of transmit data is bit 0 in the SSTDR contents (MLS = 0: LSB first communication) and is bit 7 in the SSTDR contents (MLS = 1: MSB first communication). The SSU transfers data from the LSB (bit 0) in SSTRSR to the SSO pin to perform serial data transmission. In reception, the SSU sets serial data that has been input via the SSI pin in SSTRSR from the LSB (bit 0). When 1-byte data has been received, the SSTRSR contents are automatically transferred to SSRDR. SSTRSR cannot be directly accessed by the CPU. Rev. 2.00 Mar. 15, 2006 Page 499 of 754 REJ09B0199-0200 Section 14 Synchronous Serial Communication Unit (SSU) 14.4 14.4.1 Operation Transfer Clock A transfer clock can be selected from eight internal clocks and an external clock. When using this module, set the SCKS bit in SSCRH to 1 to select the SSCK pin as a serial clock. When the MSS bit in SSCRH is 1, an internal clock is selected and the SSCK pin is used as an output pin. When transfer is started, the clock with the transfer rate set by bits CKS2 to CKS0 in SSMR is output from the SSCK pin. When MSS = 0, an external clock is selected and the SSCK pin is used as an input pin. 14.4.2 Relationship of Clock Phase, Polarity, and Data The relationship of clock phase, polarity, and transfer data depends on the combination of the CPOS and CPHS bits in SSMR. Figure 14.2 shows the relationship. When SSUMS = 1, the CPHS setting is invalid although the CPOS setting is valid. Setting the MLS bit in SSMR selects that MSB or LSB first communication. When MLS = 0, data is transferred from the LSB to the MSB. When MLS = 1, data is transferred from the MSB to the LSB. (1) When CPHS = 0 SCS SSCK (CPOS = 0) SSCK (CPOS = 1) SSI, SSO (2) When CPHS = 1 SCS SSCK (CPOS = 0) SSCK (CPOS = 1) SSI, SSO Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Figure 14.2 Relationship of Clock Phase, Polarity, and Data Rev. 2.00 Mar. 15, 2006 Page 500 of 754 REJ09B0199-0200 Section 14 Synchronous Serial Communication Unit (SSU) 14.4.3 Relationship between Data Input/Output Pins and Shift Register The connection between data input/output pins and the SS shift register (SSTRSR) depends on the combination of the MSS and BIDE bits in SSCRH and the SSUMS bit in SSCRL. Figure 14.3 shows the relationship. The SSU transmits serial data from the SSO pin and receives serial data from the SSI pin when operating with BIDE = 0 and MSS = 1 (standard, master mode) (see figure 14.3 (1)). The SSU transmits serial data from the SSI pin and receives serial data from the SSO pin when operating with BIDE = 0 and MSS = 0 (standard, slave mode) (see figure 14.3 (2)). The SSU transmits and receives serial data from the SSO pin regardless of master or slave mode when operating with BIDE = 1 (bidirectional mode) (see figures 14.3 (3) and (4)). However, even if both the TE and RE bits are set to 1, transmission and reception are not performed simultaneously. Either the TE or RE bit must be selected. The SSU transmits serial data from the SSO pin and receives serial data from the SSI pin when operating with SSUMS = 1. The SSCK pin outputs the internal clock when MSS = 1 and function as an input pin when MSS = 0 (see figures 14.3 (5) and (6)). (1) When SSUMS = 0, BIDE = 0 (standard mode), MSS = 1, TE = 1, and RE = 1 SSCK Shift register (SSTRSR) SSO SSI (4) When SSUMS = 0, BIDE = 1 (bidirectional mode), MSS = 1, and either TE or RE = 1 SSCK Shift register (SSTRSR) SSO SSI (5) When SSUMS = 1 and MSS = 1 SSCK Shift register (SSTRSR) SSO SSI Shift register (SSTRSR) (6) When SSUMS = 1 and MSS = 0 SSCK SSO SSI (2) When SSUMS = 0, BIDE = 0 (standard mode), MSS = 0, TE = 1, and RE = 1 SSCK Shift register (SSTRSR) SSO SSI (3) When SSUMS = 0, BIDE = 1 (bidirectional mode), MSS = 0, and either TE or RE = 1 SSCK Shift register (SSTRSR) SSO SSI Figure 14.3 Relationship between Data Input/Output Pins and the Shift Register Rev. 2.00 Mar. 15, 2006 Page 501 of 754 REJ09B0199-0200 Section 14 Synchronous Serial Communication Unit (SSU) 14.4.4 Communication Modes and Pin Functions The SSU switches the input/output pin (SSI, SSO, SSCK, and SCS) functions according to the communication modes and register settings. When a pin is used as an input pin, set the corresponding bit in the input buffer control register (ICR) to 1. The relationship of communication modes and input/output pin functions are shown in tables 14.4 to 14.6. Table 14.4 Communication Modes and Pin States of SSI and SSO Pins Communication Mode SSU communication mode Register Setting SSUMS 0 BIDE 0 MSS 0 TE 0 1 RE 1 0 1 1 0 1 1 0 1 SSU (bidirectional) 0 communication mode 1 0 0 1 1 0 1 Clock synchronous 1 communication mode 0 0 0 1 1 0 1 0 1 0 1 1 0 1 [Legend] : Not used as SSU pin (can be used as I/O port) 1 0 1 SSI Output Output Input Input Input Input Input Input Pin State SSO Input Input Output Output Input Output Input Output Output Output Output Output Rev. 2.00 Mar. 15, 2006 Page 502 of 754 REJ09B0199-0200 Section 14 Synchronous Serial Communication Unit (SSU) Table 14.5 Communication Modes and Pin States of SSCK Pin Communication Mode SSU communication mode Register Setting SSUMS 0 MSS 0 SCKS 0 1 1 0 1 Clock synchronous 1 communication mode 0 0 1 1 [Legend] : Not used as SSU pin (can be used as I/O port) 0 1 Pin State SSCK Input Output Input Output Table 14.6 Communication Modes and Pin States of SCS Pin Communication Mode SSU communication mode Register Setting SSUMS 0 MSS 0 1 CSS1 x 0 0 1 1 Clock synchronous 1 communication mode x x CSS0 x 0 1 0 1 x Pin State SCS Input Input Automatic input/output Output [Legend] x: Don't care : Not used as SSU pin (can be used as I/O port) Rev. 2.00 Mar. 15, 2006 Page 503 of 754 REJ09B0199-0200 Section 14 Synchronous Serial Communication Unit (SSU) 14.4.5 SSU Mode In SSU mode, data communications are performed via four lines: clock line (SSCK), data input line (SSI or SSO), data output line (SSI or SSO), and chip select line (SCS). In addition, the SSU supports bidirectional mode in which a single pin functions as data input and data output lines. (1) Initial Settings in SSU Mode Figure 14.4 shows an example of the initial settings in SSU mode. Before data transfer, clear both the TE and RE bits in SSER to 0 to set the initial values. Note: Before changing operating modes and communications formats, clear both the TE and RE bits to 0. Although clearing the TE bit to 0 sets the TDRE bit to 1, clearing the RE bit to 0 does not change the values of the RDRF and ORER bits and SSRDR. Those bits retain the previous values. Start setting initial values Clear TE and RE bits in SSER to 0 [1] Set a bit in ICR to 1 Specify MSS, BIDE, SOL, SCKS, CSS1, and CSS0 bits in SSCRH Clear SSUMS in SSCRH to 0 and specify bits DATS1 and DATS0 Specify MLS, CPOS, CPHS, CKS2, CKS1, and CKS0 bits in SSMR Specify SDOS, SSCKOS, SCSOS, TENDSTS, SCSATS and SSODTS bits in SSCR2 [5] Specify TE, RE, TEIE, TIE, RIE, and CEIE bits in SSER smulataneously [1] When the pin is used as an input. [2] Specify master/slave mode selection, bidirectional mode enable, SSO pin output value selection, SSCK pin selection, and SCS pin selection. [3] Selects SSU mode and specify transmit/receive data length. [4] Specify MSB first/LSB first selection, clock polarity selection, clock phase selection, and transfer clock rate selection. [5] Enables/disables interrupt request to the CPU. [2] [3] [4] End Figure 14.4 Example of Initial Settings in SSU Mode Rev. 2.00 Mar. 15, 2006 Page 504 of 754 REJ09B0199-0200 Section 14 Synchronous Serial Communication Unit (SSU) (2) Data Transmission Figure 14.5 shows an example of transmission operation, and figure 14.6 shows a flowchart example of data transmission. When transmitting data, the SSU operates as shown below. In master mode, the SSU outputs a transfer clock and data. In slave mode, when a low level signal is input to the SCS pin and a transfer clock is input to the SSCK pin, the SSU outputs data in synchronization with the transfer clock. Writing transmit data to SSTDR after the TE bit is set to 1 clears the TDRE bit in SSSR to 0, and the SSTDR contents are transferred to SSTRSR. After that, the SSU sets the TDRE bit to 1 and starts transmission. At this time, if the TIE bit in SSER is set to 1, a TXI interrupt is generated. When 1-frame data has been transferred with TDRE = 0, the SSTDR contents are transferred to SSTRSR to start the next frame transmission. When the 8th bit of transmit data has been transferred with TDRE = 1, the TEND bit in SSSR is set to 1 and the state is retained. At this time, if the TEIE bit is set to 1, a TEI interrupt is generated. After transmission, the output level of the SSCK pin is fixed high when CPOS = 0 and low when CPOS = 1. While the ORER bit in SSSR is set to 1, transmission is not performed. Check that the ORER bit is cleared to 0. Rev. 2.00 Mar. 15, 2006 Page 505 of 754 REJ09B0199-0200 Section 14 Synchronous Serial Communication Unit (SSU) (1) When 8-bit data length is selected (SSTDR0 is valid) with CPOS = 0 and CPHS = 0 SCS SSCK SSO Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 1 frame 1 frame SSTDR0 (LSB first transmission) SSTDR0 (MSB first transmission) TDRE TEND LSI operation generated User operation Data written to SSTDR0 TXI interrupt TEI interrupt generated TXI interrupt generated Data written to SSTDR0 TEI interrupt generated (2) When 16-bit data length is selected (SSTDR0 and SSTDR1 are valid) with CPOS = 0 and CPHS = 0 SCS SSCK SSO (LSB first) SSO (MSB first) TDRE TEND LSI operation TXI interrupt generated User operation Data written to SSTDR0 and SSTDR1 TEI interrupt generated Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 1 frame SSTDR1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 SSTDR0 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SSTDR0 SSTDR1 (3) When 32-bit data length is selected (SSTDR0 and SSTDR3 are valid) with CPOS = 0 and CPHS = 0 SCS SSCK SSO (LSB first) SSO (MSB first) TDRE TEND LSI operation TXI interrupt generated TEI interrupt generated User operation Data written to SSTDR0 to SSTDR1 Bit 0 to Bit 7 Bit 0 to SSTDR Bit 0 Bit 7 to Bit 0 Bit 7 Bit 7 Bit 0 to SSTDR to Bit 0 Bit 7 Bit 7 Bit 0 to SSTDR to Bit 0 Bit 7 1 frame SSTDR Bit 7 to SSTDR SSTDR SSTDR SSTDR Figure 14.5 Example of Transmission Operation (SSU Mode) Rev. 2.00 Mar. 15, 2006 Page 506 of 754 REJ09B0199-0200 Section 14 Synchronous Serial Communication Unit (SSU) Start [1] [2] Initial setting Read TDRE in SSSR TDRE = 1? Yes Write transmit data to SSTDR TDRE automatically cleared Data transferred from SSTDR to SSTRSR [1] Initial setting: Specify the transmit data format. [2] Check that the SSU state and write transmit data: Write transmit data to SSTDR after reading and confirming that the TDRE bit is 1. The TDRE bit is automatically cleared to 0 and transmission is started by writing data to SSTDR. [3] Procedure for consecutive data transmission: To continue data transmission, confirm that the TDRE bit is 1 meaning that SSTDR is ready to be written to. After that, data can be written to SSTDR. The TDRE bit is automatically cleared to 0 by writing data to SSTDR. [4] Procedure for data transmission end: To end data transmission, confirm that the TEND bit is cleared to 0. After completion of transmitting the last bit, clear the TE bit to 0. Yes No Set TDRE to 1 to start transmission [3] Consecutive data transmission? No Read TEND in SSSR TEND = 1? Yes Clear TEND to 0 Confirm that TEND is cleared to 0 [4] One bit time quantum elapsed? Yes Clear TE in SSER to 0 End transmission Note: Hatching boxes represent SSU internal operations. No No Figure 14.6 Flowchart Example of Data Transmission (SSU Mode) Rev. 2.00 Mar. 15, 2006 Page 507 of 754 REJ09B0199-0200 Section 14 Synchronous Serial Communication Unit (SSU) (3) Data Reception Figure 14.7 shows an example of reception operation, and figure 14.8 shows a flowchart example of data reception. When receiving data, the SSU operates as shown below. After setting the RE bit to 1 and dummy-reading SSRDR, the SSU starts data reception. In master mode, the SSU outputs a transfer clock and receives data. In slave mode, when a low level signal is input to the SCS pin and a transfer clock is input to the SSCK pin, the SSU receives data in synchronization with the transfer clock. When 1-frame data has been received, the RDRF bit in SSSR is set to 1 and the receive data is stored in SSRDR. At this time, if the RIE bit in SSER is set to 1, an RXI interrupt is generated. The RDRF bit is automatically cleared to 0 by reading SSRDR. When the RDRF bit has been set to 1 at the 8th rising edge of the transfer clock, the ORER bit in SSSR is set to 1. This indicates that an overrun error (OEI) has occurred. At this time, data reception is stopped. While the ORER bit in SSSR is set to 1, reception is not performed. To resume the reception, clear the ORER bit to 0. Rev. 2.00 Mar. 15, 2006 Page 508 of 754 REJ09B0199-0200 Section 14 Synchronous Serial Communication Unit (SSU) (1) When 8-bit data length is selected (SSRDR0 is valid) with CPOS = 0 and CPHS = 0 SCS 1 frame 1 frame SSCK SSI Bit Bit Bit Bit Bit Bit Bit Bit 0 1 2 3 4 5 6 7 SSTDR0 (LSB first transmission) Bit Bit Bit Bit Bit Bit Bit Bit 7 6 5 4 3 2 1 0 SSTDR0 (MSB first transmission) RDRF LSI operation User operation Dummy-read SSRDR0 RXI interrupt generated RXI interrupt generated Read SSRDR0 (2) When 16-bit data length is selected (SSRDR0 and SSRDR1 are valid) with CPOS = 0 and CPHS = 0 SCS 1 frame SSCK SSI (LSB first) SSI (MSB first) Bit Bit Bit Bit Bit Bit Bit Bit 0 1 2 3 4 5 6 7 SSRDR1 Bit Bit Bit Bit Bit Bit Bit Bit 0 1 2 3 4 5 6 7 SSRDR0 Bit Bit Bit Bit Bit Bit Bit Bit 7 6 5 4 3 2 1 0 SSRDR0 Bit Bit Bit Bit Bit Bit Bit Bit 7 6 5 4 3 2 1 0 SSRDR1 RDRF LSI operation User operation Dummy-readSSRDR0 (3) When 32-bit data length is selected (SSRDR0 to SSRDR3 are valid) with CPOS = 0 and CPHS = 0 SCS 1 frame RXI interrupt generated SSCK SSI (LSB first) SSI (MSB first) RDRF LSI operation User operation Dummy-readSSRDR0 RXI interrupt generated Bit 0 to Bit Bit 7 0 to Bit Bit 7 0 to Bit 7 Bit 0 to Bit 7 SSRDR3 SSRDR2 SSRDR1 SSRDR0 Bit 7 to Bit Bit 0 7 to Bit 0 Bit 7 to Bit Bit 0 7 to Bit 0 SSRDR0 SSRDR1 SSRDR2 SSRDR3 Figure 14.7 Example of Reception Operation (SSU Mode) Rev. 2.00 Mar. 15, 2006 Page 509 of 754 REJ09B0199-0200 Section 14 Synchronous Serial Communication Unit (SSU) Start [1] [2] [1] Initial setting Dummy-read SSRDR [2] Initial setting: Specify the receive data format. Start reception: When SSRDR is dummy-read with RE = 1, reception is started. Read SSSR No RDRF = 1? Yes ORER = 1? No [4] Consecutive data reception? Yes Read received data in SSRDR RDRF automatically cleared [5] No Yes [3] [3], [6] Receive error processing: When a receive error occurs, execute the designated error processing after reading the ORER bit in SSSR. After that, clear the ORER bit to 0. While the ORER bit is set to 1, transmission or reception is not resumed. [4] To continue single reception: When continuing single reception, wait for time of tSUcyc while the RDRF flag is set to 1 and then read receive data in SSRDR. The next single reception starts after reading receive data in SSRDR. To complete reception: To complete reception, read receive data after clearing the RE bit to 0. When reading SSRDR without clearing the RE bit, reception is resumed. [5] RE = 0 Read receive data in SSRDR End reception Note: Hatching boxes represent SSU internal operations. [6] Overrun error processing Clear ORER in SSSR End reception Figure 14.8 Flowchart Example of Data Reception (SSU Mode) Rev. 2.00 Mar. 15, 2006 Page 510 of 754 REJ09B0199-0200 Section 14 Synchronous Serial Communication Unit (SSU) (4) Data Transmission/Reception Figure 14.9 shows a flowchart example of simultaneous transmission/reception. The data transmission/reception is performed combining the data transmission and data reception as mentioned above. The data transmission/reception is started by writing transmit data to SSTDR with TE = RE = 1. Before switching transmission mode (TE = 1) or reception mode (RE = 1) to transmission/reception mode (TE = RE = 1), clear the TE and RE bits to 0. When starting the transfer, confirm that the TEND, RDRF, and ORER bits are cleared to 0 before setting the TE or RE bit to 1. Start [1] [2] Initial setting Read TDRE in SSSR No [1] Initial setting: Specify the transmit/receive data format. [2] Check the SSU state and write transmit data: Write transmit data to SSTDR after reading and confirming that the TDRE bit in SSSR is 1. The TDRE bit is automatically cleared to 0 and transmission/ reception is started by writing data to SSTDR. [3] Check the SSU state: Read SSSR confirming that the RDRF bit is 1. A change of the RDRF bit (from 0 to 1) can be notified by RXI interrupt. [4] Receive error processing: When a receive error occurs, execute the designated error processing after reading the ORER bit in SSSR. After that, clear the ORER bit to 0. While the ORER bit is set to 1, transmission or reception is not resumed. [5] Procedure for consecutive data transmission/reception: To continue serial data transmission/reception, confirm that the TDRE bit is 1 meaning that SSTDR is ready to be written to. After that, data can be written to SSTDR. The TDRE bit is automatically cleared to 0 by writing data to SSTDR. TDRE = 1? Yes Write transmit data to SSTDR TDRE automatically cleared Data transferred from SSTDR to SSTRSR TDRE set to 1 to start transmission Read SSSR [3] No RDRF = 1? Yes Yes [4] ORER = 1? No Read receive data in SSRDR Note: Hatching boxes represent SSU internal operations. RDRF automatically cleared Consecutive data transmission/reception? No Read TEND in SSSR No TEND = 1? Yes Clear TEND in SSSR to 0 Yes [5] Error processing No Has the 1 bit transfer period elapsed? Yes Clear TE and RE in SSER to 0 End transmission/reception Figure 14.9 Flowchart Example of Simultaneous Transmission/Reception (SSU Mode) Rev. 2.00 Mar. 15, 2006 Page 511 of 754 REJ09B0199-0200 Section 14 Synchronous Serial Communication Unit (SSU) 14.4.6 SCS Pin Control and Conflict Error When bits CSS1 and CSS0 in SSCRH are specified to B'10 and the SSUMS bit in SSCRL is cleared to 0, the SCS pin functions as an input (Hi-Z) to detect a conflict error. The conflict error detection period is from setting the MSS bit in SSCRH to 1 to starting serial transfer and after transfer ends. When a low level signal is input to the SCS pin within the period, a conflict error occurs. At this time, the CE bit in SSSR is set to 1 and the MSS bit is cleared to 0. Note: While the CE bit is set to 1, transmission or reception is not resumed. Clear the CE bit to 0 before resuming the transmission or reception. External input to SCS Internal-clocked SCS MSS Internal signal for transfer enable CE SCS output (Hi-Z) Data written to SSTDR Conflict error detection period Worst time for internally clocking SCS Figure 14.10 Conflict Error Detection Timing (Before Transfer) P SCS (Hi-Z) MSS Internal signal for transfer enable CE Transfer end Conflict error detection period Figure 14.11 Conflict Error Detection Timing (After Transfer End) Rev. 2.00 Mar. 15, 2006 Page 512 of 754 REJ09B0199-0200 Section 14 Synchronous Serial Communication Unit (SSU) 14.4.7 Clock Synchronous Communication Mode In clock synchronous communication mode, data communications are performed via three lines: clock line (SSCK), data input line (SSI), and data output line (SSO). (1) Initial Settings in Clock Synchronous Communication Mode Figure 14.12 shows an example of the initial settings in clock synchronous communication mode. Before data transfer, clear both the TE and RE bits in SSER to 0 to set the initial values. Note: Before changing operating modes and communications formats, clear both the TE and RE bits to 0. Although clearing the TE bit to 0 sets the TDRE bit to 1, clearing the RE bit to 0 does not change the values of the RDRF and ORER bits and SSRDR. Those bits retain the previous values. Start setting initial values Clear TE and RE bits in SSER to 0 [1] When the pin is used as an input. [2] Specify master/slave mode selection and SSCK pin selection. [3] Selects clock synchronous communication mode and specify transmit/receive data length. [4] Specify clock polarity selection and transfer clock rate selection. [5] Enables/disables interrupt request to the CPU. [1] Set a bit in ICR to 1 [2] Specify MSS and SCKS in SSCRH [3] Set SSUMS in SSCRL to 1 and specify bits DATS1 and DATS0 [4] Specify CPOS, CKS2, CKS1, and CKS0 bits in SSMR Specify SDOS, SSCKOS, SCSOS, TENDSTS, SCSATS, and SSODTS bits in SSCR2 [5] Specify TE, RE, TEIE, TIE, RIE, and CEIE bits in SSER simultaneously End Figure 14.12 Example of Initial Settings in Clock Synchronous Communication Mode Rev. 2.00 Mar. 15, 2006 Page 513 of 754 REJ09B0199-0200 Section 14 Synchronous Serial Communication Unit (SSU) (2) Data Transmission Figure 14.13 shows an example of transmission operation, and figure 14.14 shows a flowchart example of data transmission. When transmitting data in clock synchronous communication mode, the SSU operates as shown below. In master mode, the SSU outputs a transfer clock and data. In slave mode, when a transfer clock is input to the SSCK pin, the SSU outputs data in synchronization with the transfer clock. Writing transmit data to SSTDR after the TE bit is set to 1 clears the TDRE bit in SSSR to 0, and the SSTDR contents are transferred to SSTRSR. After that, the SSU sets the TDRE bit to 1 and starts transmission. At this time, if the TIE bit in SSER is set to 1, a TXI interrupt is generated. When 1-frame data has been transferred with TDRE = 0, the SSTDR contents are transferred to SSTRSR to start the next frame transmission. When the 8th bit of transmit data has been transferred with TDRE = 1, the TEND bit in SSSR is set to 1 and the state is retained. At this time, if the TEIE bit is set to 1, a TEI interrupt is generated. While the ORER bit in SSSR is set to 1, transmission is not performed. Check that the ORER bit is cleared to 0. SSCK SSO Bit 0 Bit 1 1 frame Bit 7 Bit 0 Bit 1 1 frame Bit 7 TDRE TEND LSI operation User operation TXI interrupt generated Data written to SSTDR Data written to SSTDR TXI interrupt generated TEI interrupt generated Figure 14.13 Example of Transmission Operation (Clock Synchronous Communication Mode) Rev. 2.00 Mar. 15, 2006 Page 514 of 754 REJ09B0199-0200 Section 14 Synchronous Serial Communication Unit (SSU) Start [1] [2] Initial setting Read TDRE in SSSR TDRE = 1? Yes Write transmit data to SSTDR TDRE automatically cleared Data transferred from SSTDR to SSTRSR [4][1] Initial setting: Specify the transmit data format. [2] Check that the SSU state and write transmit data: Write transmit data to SSTDR after reading and confirming that the TDRE bit is 1. The TDRE bit is automatically cleared to 0 and transmission is started by writing data to SSTDR. [3] Procedure for consecutive data transmission: To continue data transmission, confirm that the TDRE bit is 1 meaning that SSTDR is ready to be written to. After that, data can be written to SSTDR. The TDRE bit is automatically cleared to 0 by writing data to SSTDR. [4] Procedure for data transmission end: To end data transmission, confirm that the TEND bit is cleared to 0. After completion of transmitting the last bit, clear the TE bit to 0. Yes No Set TDRE to 1 to start transmission [3] Consecutive data transmission? No Read TEND in SSSR TEND = 1? Yes Clear TEND to 0 Confirm that TEND is cleared to 0 [4] One bit time quantum elapsed? Yes Clear TE in SSER to 0 End transmission No No Note: Hatching boxes represent SSU internal operations. Figure 14.14 Flowchart Example of Transmission Operation (Clock Synchronous Communication Mode) Rev. 2.00 Mar. 15, 2006 Page 515 of 754 REJ09B0199-0200 Section 14 Synchronous Serial Communication Unit (SSU) (3) Data Reception Figure 14.15 shows an example of reception operation, and figure 14.16 shows a flowchart example of data reception. When receiving data, the SSU operates as shown below. After setting the RE bit in SSER to 1, the SSU starts data reception. In master mode, the SSU outputs a transfer clock and receives data. In slave mode, when a transfer clock is input to the SSCK pin, the SSU receives data in synchronization with the transfer clock. When 1-frame data has been received, the RDRF bit in SSSR is set to 1 and the receive data is stored in SSRDR. At this time, if the RIE bit is set to 1, an RXI interrupt is generated. The RDRF bit is automatically cleared to 0 by reading SSRDR. When the RDRF bit has been set to 1 at the 8th rising edge of the transfer clock, the ORER bit in SSSR is set to 1. This indicates that an overrun error (OEI) has occurred. At this time, data reception is stopped. While the ORER bit in SSSR is set to 1, reception is not performed. To resume the reception, clear the ORER bit to 0. SSCK SSO Bit 0 1 frame Bit 7 Bit 0 1 frame Bit 7 Bit 0 Bit 7 RDRF LSI operation User operation Dummy-read SSRDR RXI interrupt generated RXI interrupt generated Read data from SSRDR RXI interrupt generated Read data from SSRDR Figure 14.15 Example of Reception Operation (Clock Synchronous Communication Mode) Rev. 2.00 Mar. 15, 2006 Page 516 of 754 REJ09B0199-0200 Section 14 Synchronous Serial Communication Unit (SSU) Start [1] Initial setting [1] Initial setting: Specify the receive data format. Read SSSR No RDRF = 1? Yes ORER = 1? No Consecutive data reception? [2], [4] Receive error processing: When a receive error occurs, execute the designated error processing after reading the ORER bit in SSSR. After that, clear the ORER bit to 0. While the ORER bit is set to 1, transmission or reception is not resumed. [3] Yes [2] To complete reception: To complete reception, read receive data after clearing the RE bit to 0. When reading SSRDR without clearing the RE bit, reception is resumed. No Note: Hatching boxes represent SSU internal operations. Yes Read received data in SSRDR RDRF automatically cleared [3] RE = 0 Read receive data in SSRDR End reception [4] Overrun error processing Clear ORER in SSSR End reception Figure 14.16 Flowchart Example of Data Reception (Clock Synchronous Communication Mode) Rev. 2.00 Mar. 15, 2006 Page 517 of 754 REJ09B0199-0200 Section 14 Synchronous Serial Communication Unit (SSU) (4) Data Transmission/Reception Figure 14.17 shows a flowchart example of simultaneous transmission/reception. The data transmission/reception is performed combining the data transmission and data reception as mentioned above. The data transmission/reception is started by writing transmit data to SSTDR with TE = RE = 1. Before switching transmission mode (TE = 1) or reception mode (RE = 1) to transmission/reception mode (TE = RE = 1), clear the TE and RE bits to 0. When starting the transfer, confirm that the TEND, RDRF, and ORER bits are cleared to 0 before setting the TE or RE bits to 1. Start [1] [2] Initial setting Read TDRE in SSSR No [1] Initial setting: Specify the transmit/receive data format. [2] Check the SSU state and write transmit data: Write transmit data to SSTDR after reading and confirming that the TDRE bit in SSSR is 1. The TDRE bit is automatically cleared to 0 and transmission is started by writing data to SSTDR. [3] Check the SSU state: Read SSSR confirming that the RDRF bit is 1. A change of the RDRF bit (from 0 to 1) can be notified by RXI interrupt. [4] Receive error processing: When a receive error occurs, execute the designated error processing after reading the ORER bit in SSSR. After that, clear the ORER bit to 0. While the ORER bit is set to 1, transmission or reception is not resumed. [5] Procedure for consecutive data transmission/reception: To continue serial data transmission/reception, confirm that the TDRE bit is 1 meaning that SSTDR is ready to be written to. After that, data can be written to SSTDR. The TDRE bit is automatically cleared to 0 by writing data to SSTDR. TDRE = 1? Yes Write transmit data to SSTDR TDRE automatically cleared Data transferred from SSTDR to SSTRSR TDRE set to 1 to start transmission Read SSSR [3] No RDRF = 1? Yes ORER = 1? No Read receive data in SSRDR Yes [4] Note: Hatching boxes represent SSU internal operations. RDRF automatically cleared Consecutive data transmission/reception? No Read TEND in SSSR TEND = 1? Yes Clear TEND in SSSR to 0 No Yes [5] Error processing No Has the 1 bit transfer period elapsed? Yes Clear TE and RE in SSER to 0 End transmission/reception Figure 14.17 Flowchart Example of Simultaneous Transmission/Reception (Clock Synchronous Communication Mode) Rev. 2.00 Mar. 15, 2006 Page 518 of 754 REJ09B0199-0200 Section 14 Synchronous Serial Communication Unit (SSU) 14.5 Interrupt Requests The SSU interrupt requests are an overrun error, a conflict error, a receive data register full, transmit data register empty, and a transmit end interrupts. Of these interrupt sources, a receive data register full, a transmit data register empty, and a transmit end interrupts can activate the DMAC for data transfer. Since both an overrun error and a conflict error interrupts are allocated to the SSERI vector address, and both a transmit data register empty and a transmit end interrupts are allocated to the SSTXI vector address, the interrupt source should be decided by their flags. Table 14.7 lists the interrupt sources. When an interrupt condition shown in table 14.7 is satisfied, an interrupt is requested. Clear the interrupt source by CPU or DMAC data transfer. Table 14.7 Interrupt Sources Channel Abbreviation Interrupt Source 0 SSERI0 SSRXI0 SSTXI0 Overrun error Conflict error Receive data register full Transmit data register empty Transmit end 1 SSERI1 SSRXI1 SSTXI1 Overrun error Conflict error Receive data register full Transmit data register empty Transmit end 2 SSERI2 SSRXI2 SSTXI2 Overrun error Conflict error Receive data register full Transmit data register empty Transmit end Symbol OEI0 CEI0 RXI0 TXI0 TEI0 OEI1 CEI1 RXI1 TXI1 TEI1 OEI2 CEI2 RXI2 TXI2 TEI2 Interrupt Condition (RIE = 1) * (ORER = 1) (CEIE = 1) * (CE = 1) (RIE = 1) * (RDRF = 1) (TIE = 1) * (TDRE = 1) (TEIE = 1) * (TEND = 1) (RIE = 1) * (ORER = 1) (CEIE = 1) * (CE = 1) (RIE = 1) * (RDRF = 1) (TIE = 1) * (TDRE = 1) (TEIE = 1) * (TEND = 1) (RIE = 1) * (ORER = 1) (CEIE = 1) * (CE = 1) (RIE = 1) * (RDRF = 1) (TIE = 1) * (TDRE = 1) (TEIE = 1) * (TEND = 1) DTC Activation DMAC Activation Yes Yes Yes Yes Yes Yes Yes Yes Yes Rev. 2.00 Mar. 15, 2006 Page 519 of 754 REJ09B0199-0200 Section 14 Synchronous Serial Communication Unit (SSU) 14.6 14.6.1 Usage Note Setting of Module Stop Mode The SSU can be enabled/disabled by the module stop control register setting and is disabled by the initial value. Canceling module stop mode enables to access the SSU registers. For details, see section 19, Power-Down Modes. 14.6.2 Note on Clearing Module Stop Mode When clearing module stop mode, attention is required to the following. When using the SSU channel 1 (or 2), the SSU channel 1 (or 2) is not cleared module stop mode without clearing both 1 and 2 bits listed below. 1. Module stop bit for channel 1 (or 2): MSTPC9 (or MSTPC10) 2. Module stop bit for channel 0: MSTPC8 When the SSU channel 0 is not used for the SSU function, I/O port pins that are multiplexed with the SSU channel 0 function can be used as I/O port pins unless module stop mode is cleared and the SSU channel 0 is enabled transmission and reception. Rev. 2.00 Mar. 15, 2006 Page 520 of 754 REJ09B0199-0200 Section 15 A/D Converter Section 15 A/D Converter This LSI includes two units (unit 0 and unit 1) of successive approximation type 10-bit A/D converters that allow up to 16 analog input channels to be selected. Figures 15.1 and 15.2 are block diagrams for unit 0 and unit 1, respectively. This section describes unit 0, which has the same functions as the other unit. 15.1 * * * * Features * * * * * * 10-bit resolution 16 input channels (eight channels for unit 0 and eight channels for unit 1) Conversion time: 3.4 s per channel (at 35-MHz operation) Two kinds of operating modes Single mode: Single-channel A/D conversion Scan mode: Continuous A/D conversion on 1 to 4 channels, or 1 to 8 channels 16 data registers (eight registers for unit 0 and eight registers for unit 1) A/D conversion results are held in a 16-bit data register for each channel Sample and hold function Three types of conversion start Conversion can be started by software, a conversion start trigger by the 16-bit timer pulse unit (TPU), or an external trigger signal. Interrupt source A/D conversion end interrupt (ADI) request can be generated. Module stop mode can be set Pulling down the analog port enabled Rev. 2.00 Mar. 15, 2006 Page 521 of 754 REJ09B0199-0200 Section 15 A/D Converter Module data bus Bus interface ADDRG_0 ADDRC_0 ADDRD_0 ADDRH_0 ADDRA_0 ADDRB_0 ADDRE_0 ADCSR_0 ADDRF_0 Internal data bus AVCC0 10-bit D/A AVSS Successive approximation register AN0 AN1 Multiplexer + - Comparator Sample-andhold circuit Control circuit AN2 AN3 AN4 AN5 AN6 AN7 ADCR_0 ADTRG0 [Legend] ADCR_0: ADCSR_0: ADDRA_0: ADDRB_0: ADDRC_0: ADI0 interrupt signal Conversion start trigger from the TPU A/D control register_0 A/D control/status register_0 A/D data register A_0 A/D data register B_0 A/D data register C_0 ADDRD_0: ADDRE_0: ADDRF_0: ADDRG_0: ADDRH_0: A/D data register D_0 A/D data register E_0 A/D data register F_0 A/D data register G_0 A/D data register H_0 Figure 15.1 Block Diagram of A/D Converter (Unit 0/AD_0) Rev. 2.00 Mar. 15, 2006 Page 522 of 754 REJ09B0199-0200 Section 15 A/D Converter Module data bus Bus interface ADDRG_1 ADDRC_1 ADDRD_1 ADDRH_1 ADDRA_1 ADDRB_1 ADDRE_1 ADCSR_1 ADDRF_1 Internal data bus AVCC1 10-bit D/A AVSS Successive approximation register AN8 AN9 Multiplexer + - Comparator Sample-andhold circuit Control circuit AN10 AN11 AN12 AN13 AN14 AN15 ADCR_1 ADTRG1 [Legend] ADCR_1: ADCSR_1: ADDRA_1: ADDRB_1: ADDRC_1: ADI1 interrupt signal Conversion start trigger from the TPU A/D control register_1 A/D control/status register_1 A/D data register A_1 A/D data register B_1 A/D data register C_1 ADDRD_1: ADDRE_1: ADDRF_1: ADDRG_1: ADDRH_1: A/D data register D_1 A/D data register E_1 A/D data register F_1 A/D data register G_1 A/D data register H_1 Figure 15.2 Block Diagram of A/D Converter (Unit 1/AD_1) Rev. 2.00 Mar. 15, 2006 Page 523 of 754 REJ09B0199-0200 Section 15 A/D Converter 15.2 Input/Output Pins Table 15.1 shows the pin configuration of the A/D converter. Table 15.1 Pin Configuration Unit 0 Abbr. AD_0 Pin Name Analog input pin 0 Analog input pin 1 Analog input pin 2 Analog input pin 3 Analog input pin 4 Analog input pin 5 Analog input pin 6 Analog input pin 7 Symbol AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 I/O Input Input Input Input Input Input Input Input External trigger input for starting A/D conversion Analog block power supply Analog inputs Function Analog inputs A/D external trigger input pin 0 ADTRG0 Input Analog power supply pin 0 1 AD_1 Analog input pin 8 Analog input pin 9 Analog input pin 10 Analog input pin 11 Analog input pin 12 Analog input pin 13 Analog input pin 14 Analog input pin 15 AVCC0 AN8 AN9 AN10 AN11 AN12 AN13 AN14 AN15 Input Input Input Input Input Input Input Input Input A/D external trigger input pin 1 ADTRG1 Input Analog power supply pin 1 Common Analog ground pin AVCC1 AVSS Input Input External trigger input for starting A/D conversion Analog block power supply Analog block ground Rev. 2.00 Mar. 15, 2006 Page 524 of 754 REJ09B0199-0200 Section 15 A/D Converter 15.3 Register Descriptions The A/D converter has the following registers. The registers for unit 0 (A/D_0) and unit 1 (A/D_1) have the same functions. In this descriptions, AN8 to AN15 correspond to AN0 to AN7. * Unit 0 (A/D_0) A/D data register A_0 (ADDRA_0) A/D data register B_0 (ADDRB_0) A/D data register C_0 (ADDRC_0) A/D data register D_0 (ADDRD_0) A/D data register E_0 (ADDRE_0) A/D data register F_0 (ADDRF_0) A/D data register G_0 (ADDRG_0) A/D data register H_0 (ADDRH_0) A/D control/status register_0 (ADCSR_0) A/D control register_0 (ADCR_0) * Unit 1 (A/D_1) A/D data register A_1 (ADDRA_1) A/D data register B_1 (ADDRB_1) A/D data register C_1 (ADDRC_1) A/D data register D_1 (ADDRD_1) A/D data register E_1 (ADDRE_1) A/D data register F_1 (ADDRF_1) A/D data register G_1 (ADDRG_1) A/D data register H_1 (ADDRH_1) A/D control/status register_1 (ADCSR_1) A/D control register_1 (ADCR_1) The A/D converter has the register which controls the pull-down MOS for analog input pins. Analog port pull-down control register (APPDCR) Rev. 2.00 Mar. 15, 2006 Page 525 of 754 REJ09B0199-0200 Section 15 A/D Converter 15.3.1 A/D Data Registers A to H (ADDRA to ADDRH) There are eight 16-bit read-only ADDR registers, ADDRA to ADDRH, used to store the results of A/D conversion. The ADDR registers, which store a conversion result for each channel, are shown in table 15.2. The converted 10-bit data is stored in bits 15 to 6. The lower 6-bit data is always read as 0. The data bus between the CPU and the A/D converter has a 16-bit width. The data can be read directly from the CPU. ADDR must not be accessed in 8-bit units and must be accessed in 16-bit units. Bit Bit Name Initial Value R/W 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 15 14 13 12 11 10 9 8 7 6 5 -- 0 R 4 -- 0 R 3 -- 0 R 2 -- 0 R 1 -- 0 R 0 -- 0 R Table 15.2 Analog Input Channels and Corresponding ADDR Registers Analog Input Channel AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 A/D Data Register Which Stores Conversion Result ADDRA ADDRB ADDRC ADDRD ADDRE ADDRF ADDRG ADDRH Rev. 2.00 Mar. 15, 2006 Page 526 of 754 REJ09B0199-0200 Section 15 A/D Converter 15.3.2 A/D Control/Status Register (ADCSR) ADCSR controls A/D conversion operations. Bit Bit Name Initial Value R/W 7 ADF 0 R/(W)* 6 ADIE 0 R/W 5 ADST 0 R/W 4 -- 0 R 3 CH3 0 R/W 2 CH2 0 R/W 1 CH1 0 R/W 0 CH0 0 R/W Note: * Only 0 can be written to this bit, to clear the flag. Bit 7 Bit Name ADF Initial Value 0 R/W Description A status flag that indicates the end of A/D conversion. [Setting conditions] * * When A/D conversion ends in single mode When A/D conversion ends on all specified channels in scan mode When 0 is written after reading ADF = 1 (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) * When the DTC or DMAC is activated by an ADI interrupt and ADDR is read R/(W)* A/D End Flag [Clearing conditions] * 6 ADIE 0 R/W A/D Interrupt Enable When this bit is set to 1, ADI interrupts by ADF are enabled. 5 ADST 0 R/W A/D Start Clearing this bit to 0 stops A/D conversion, and the A/D converter enters wait state. Setting this bit to 1 starts A/D conversion. In single mode, this bit is cleared to 0 automatically when A/D conversion on the specified channel ends. In scan mode, A/D conversion continues sequentially on the specified channels until this bit is cleared to 0 by software or a reset. 4 0 R Reserved This is a read-only bit and cannot be modified. Rev. 2.00 Mar. 15, 2006 Page 527 of 754 REJ09B0199-0200 Section 15 A/D Converter Bit 3 2 1 0 Bit Name CH3 CH2 CH1 CH0 Initial Value 0 0 0 0 R/W R/W R/W R/W R/W Description Channel Select 3 to 0 Selects analog input together with bits SCANE and SCANS in ADCR. * When SCANE = 0 and SCANS = X 0000: AN0 0001: AN1 0010: AN2 0011: AN3 0100: AN4 0101: AN5 0110: AN6 0111: AN7 1XXX: Setting prohibited * When SCANE = 1 and SCANS = 0 0000: AN0 0001: AN0 and AN1 0010: AN0 to AN2 0011: AN0 to AN3 0100: AN4 0101: AN4 and AN5 0110: AN4 to AN6 0111: AN4 to AN7 1XXX: Setting prohibited * When SCANE = 1 and SCANS = 1 0000: AN0 0001: AN0 and AN1 0010: AN0 to AN2 0011: AN0 to AN3 0100: AN0 to AN4 0101: AN0 to AN5 0110: AN0 to AN6 0111: AN0 to AN7 1XXX: Setting prohibited [Legend] X: Don't care Note: * Only 0 can be written to this bit, to clear the flag. Rev. 2.00 Mar. 15, 2006 Page 528 of 754 REJ09B0199-0200 Section 15 A/D Converter 15.3.3 A/D Control Register (ADCR) ADCR enables A/D conversion to be started by an external trigger input. Bit Bit Name Initial Value R/W 7 TRGS1 0 R/W 6 TRGS0 0 R/W 5 SCANE 0 R/W 4 SCANS 0 R/W 3 CKS1 0 R/W 2 CKS0 0 R/W 1 -- 0 R 0 -- 0 R Bit 7 6 Bit Name TRGS1 TRGS0 Initial Value 0 0 R/W R/W R/W Description Timer Trigger Select 1 and 0 These bits select enabling or disabling of the start of A/D conversion by a trigger signal. 00: A/D conversion start by external trigger is disabled 01: A/D conversion start by external trigger from TPU is enabled 10: Setting prohibited 11: A/D conversion start by the ADTRG pin is enabled* 5 4 SCANE SCANS 0 0 R/W R/W Scan Mode These bits select the A/D conversion operating mode. 0X: Single mode 10: Scan mode. A/D conversion is performed continuously for channels 1 to 4. 11: Scan mode. A/D conversion is performed continuously for channels 1 to 8. 3 2 CKS1 CKS0 0 0 R/W R/W Clock Select 1 and 0 These bits set the A/D conversion time. Set bits CKS1 and CKS0 only while A/D conversion is stopped (ADST = 0). 00: A/D conversion time = 530 states (max) 01: A/D conversion time = 266 states (max) 10: A/D conversion time = 134 states (max) 11: A/D conversion time = 68 states (max) 1, 0 All 0 R Reserved These are read-only bits and cannot be modified. [Legend] X: Don't care Rev. 2.00 Mar. 15, 2006 Page 529 of 754 REJ09B0199-0200 Section 15 A/D Converter 15.3.4 Analog Port Pull-Down Control Register (APPDCR) APPDCR controls the pull-down MOS for analog input pins. Bit Bit Name Initial Value R/W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 AN15PD AN14PD AN13PD AN12PD AN11PD AN10PD AN9PD AN8PD AN7PD AN6PD AN5PD AN4PD AN3PD AN2PD AN1PD AN0PD 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Name AN15PD AN14PD AN13PD AN12PD AN11PD AN10PD AN9PD AN8PD AN7PD AN6PD AN5PD AN4PD AN3PD AN2PD AN1PD AN0PD Initial Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Description These bits control the pull-down MOS for analog input pins. 0: Pull-down MOS: Off 1: Pull-down MOS: On Rev. 2.00 Mar. 15, 2006 Page 530 of 754 REJ09B0199-0200 Section 15 A/D Converter 15.4 Operation The A/D converter operates by successive approximation with 10-bit resolution. It has two operating modes: single mode and scan mode. When changing the operating mode or analog input channel, to prevent incorrect operation, first clear the ADST bit in ADCSR to 0 to halt A/D conversion. The ADST bit can be set to 1 at the same time as the operating mode or analog input channel is changed. 15.4.1 Single Mode In single mode, A/D conversion is to be performed only once on the analog input of the specified single channel. 1. A/D conversion for the selected channel is started when the ADST bit in ADCSR is set to 1 by software or an external trigger input. 2. When A/D conversion is completed, the A/D conversion result is transferred to the corresponding A/D data register of the channel. 3. When A/D conversion is completed, the ADF bit in ADCSR is set to 1. If the ADIE bit is set to 1 at this time, an ADI interrupt request is generated. 4. The ADST bit remains set to 1 during A/D conversion, and is automatically cleared to 0 when A/D conversion ends. The A/D converter enters wait state. If the ADST bit is cleared to 0 during A/D conversion, A/D conversion stops and the A/D converter enters wait state. Rev. 2.00 Mar. 15, 2006 Page 531 of 754 REJ09B0199-0200 Section 15 A/D Converter Set* ADIE Set* ADST A/D conversion start Clear* ADF Channel 0 (AN0) operation state Channel 1 (AN1) operation state Channel 2 (AN2) operation state Channel 3 (AN3) operation state ADDRA Reading A/D conversion result Reading A/D conversion result A/D conversion result 2 Waiting for conversion Waiting for conversion A/D conversion 1 Waiting for conversion A/D conversion 2 Waiting for conversion Set* Clear* Waiting for conversion Waiting for conversion ADDRB ADDRC ADDRD Note: * indicates the timing of instruction execution by software. A/D conversion result 1 Figure 15.3 Example of A/D Converter Operation (Single Mode, Channel 1 Selected) Rev. 2.00 Mar. 15, 2006 Page 532 of 754 REJ09B0199-0200 Section 15 A/D Converter 15.4.2 Scan Mode In scan mode, A/D conversion is to be performed sequentially on the analog inputs of the specified channels up to four or eight channels. 1. When the ADST bit in ADCSR is set to 1 by software, TPU, or an external trigger input, A/D conversion starts on the first channel in the group. Consecutive A/D conversion on a maximum of four channels (SCANE and SCANS = B'10) or on a maximum of eight channels (SCANE and SCANS = B'11) can be selected. When consecutive A/D conversion is performed on four channels, A/D conversion starts on AN0 when CH3 and CH2 = B'00, on AN4 when CH3 and CH2 = B'01, on AN8 when CH3 and CH2 = B'10, and on AN12 when CH3 and CH2 = B'11. When consecutive A/D conversion is performed on eight channels, A/D conversion starts on AN0 when CH3 = B'0 and on AN8 when CH3 = B'1. 2. When A/D conversion for each channel is completed, the A/D conversion result is sequentially transferred to the corresponding ADDR of each channel. 3. When A/D conversion of all selected channels is completed, the ADF bit in ADCSR is set to 1. If the ADIE bit is set to 1 at this time, an ADI interrupt request is generated. A/D conversion of the first channel in the group starts again. 4. The ADST bit is not cleared automatically, and steps [2] to [3] are repeated as long as the ADST bit remains set to 1. When the ADST bit is cleared to 0, A/D conversion stops and the A/D converter enters wait state. If the ADST bit is later set to 1, A/D conversion starts again from the first channel in the group. Rev. 2.00 Mar. 15, 2006 Page 533 of 754 REJ09B0199-0200 Section 15 A/D Converter A/D conversion consecutive execution Set*1 ADST Clear*1 Clear*1 ADF Channel 0 (AN0) operation state Channel 1 (AN1) operation state Channel 2 (AN2) operation state Channel 3 (AN3) operation state ADDRA Waiting for conversion A/D conversion 1 A/D conversion time Waiting for conversion A/D conversion 2 A/D conversion 4 Waiting for conversion A/D conversion 5 Waiting for conversion Waiting for conversion Waiting for conversion A/D conversion 3 *2 Waiting for conversion Waiting for conversion Waiting for conversion Transfer A/D conversion result 1 A/D conversion result 4 A/D conversion result 2 A/D conversion result 3 ADDRB ADDRC ADDRD Notes: 1. indicates the timing of instruction execution by software. 2. Data being converted is ignored. Figure 15.4 Example of A/D Conversion (Scan Mode, Three Channels (AN0 to AN2) Selected) Rev. 2.00 Mar. 15, 2006 Page 534 of 754 REJ09B0199-0200 Section 15 A/D Converter 15.4.3 Input Sampling and A/D Conversion Time The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog input when the A/D conversion start delay time (tD) passes after the ADST bit in ADCSR is set to 1, then starts A/D conversion. Figure 15.5 shows the A/D conversion timing. Table 15.3 indicates the A/D conversion time. As indicated in figure 15.5, the A/D conversion time (tCONV) includes tD and the input sampling time (tSPL). The length of tD varies depending on the timing of the write access to ADCSR. The total conversion time therefore varies within the ranges indicated in table 15.3. In scan mode, the values given in table 15.3 apply to the first conversion time. The values given in table 15.4 apply to the second and subsequent conversions. In either case, bits CKS1 and CKS0 in ADCR should be set so that the conversion time is within the ranges indicated by the A/D conversion characteristics. (1) P Address (2) Write signal Input sampling timing ADF tD tSPL tCONV [Legend] (1): ADCSR write cycle (2): ADCSR address A/D conversion start delay time tD: tSPL: Input sampling time tCONV: A/D conversion time Figure 15.5 A/D Conversion Timing Rev. 2.00 Mar. 15, 2006 Page 535 of 754 REJ09B0199-0200 Section 15 A/D Converter Table 15.3 A/D Conversion Characteristics (Single Mode) CKS1 = 0 CKS0 = 0 Item A/D conversion start delay time Symbol tD Min. Typ. Max. 18 515 127 33 530 CKS0 = 1 Min. Typ. Max. 10 259 63 17 266 CKS0 = 0 Min. Typ. Max. 6 131 31 9 134 CKS1 = 1 CKS0 = 1 Min. Typ. Max. 4 67 15 5 68 Input sampling time tSPL A/D conversion time tCONV Note: Values in the table are the number of states. Table 15.4 A/D Conversion Characteristics (Scan Mode) CKS1 0 CKS0 0 1 1 0 1 Conversion Time (Number of States) 512 (Fixed) 256 (Fixed) 128 (Fixed) 64 (Fixed) Rev. 2.00 Mar. 15, 2006 Page 536 of 754 REJ09B0199-0200 Section 15 A/D Converter 15.4.4 External Trigger Input Timing A/D conversion can be externally triggered. When the TRGS1 and TRGS0 bits are set to B'11 in ADCR, an external trigger is input from the ADTRG pin. A/D conversion starts when the ADST bit in ADCSR is set to 1 on the falling edge of the ADTRG pin. Other operations, in both single and scan modes, are the same as when the ADST bit has been set to 1 by software. Figure 15.6 shows the timing. P ADTRG Internal trigger signal ADST A/D conversion Figure 15.6 External Trigger Input Timing 15.5 Interrupt Source The A/D converter generates an A/D conversion end interrupt (ADI) at the end of A/D conversion. Setting the ADIE bit to 1 when the ADF bit in ADCSR is set to 1 after A/D conversion is completed enables ADI interrupt requests. The DTC or DMA controller (DMAC) can be activated by an ADI interrupt. Having the converted data read by the DTC or DMAC in response to an ADI interrupt enables continuous conversion to be achieved without imposing a load on software. Table 15.5 A/D Converter Interrupt Source Unit 0 1 Abbr. ADI0 ADI1 Interrupt Source A/D_0 conversion end A/D_1 conversion end Interrupt Flag ADF ADF DTC Activation Possible Possible DMAC Activation Possible Possible Rev. 2.00 Mar. 15, 2006 Page 537 of 754 REJ09B0199-0200 Section 15 A/D Converter 15.6 A/D Conversion Accuracy Definitions This LSI's A/D conversion accuracy definitions are given below. * Resolution The number of A/D converter digital output codes. * Quantization error The deviation inherent in the A/D converter, given by 1/2 LSB (see figure 15.7). * Offset error The deviation of the analog input voltage value from the ideal A/D conversion characteristic when the digital output changes from the minimum voltage value B'0000000000 (H'000) to B'0000000001 (H'001) (see figure 15.8). * Full-scale error The deviation of the analog input voltage value from the ideal A/D conversion characteristic when the digital output changes from B'1111111110 (H'3FE) to B'1111111111 (H'3FF) (see figure 15.8). * Nonlinearity error The error with respect to the ideal A/D conversion characteristic between the zero voltage and the full-scale voltage. Does not include the offset error, full-scale error, or quantization error (see figure 15.8). * Absolute accuracy The deviation between the digital value and the analog input value. Includes the offset error, full-scale error, quantization error, and nonlinearity error. Rev. 2.00 Mar. 15, 2006 Page 538 of 754 REJ09B0199-0200 Section 15 A/D Converter Digital output 111 110 101 100 011 010 001 000 Ideal A/D conversion characteristic Quantization error 1 2 1024 1024 1022 1023 FS 1024 1024 Analog input voltage Figure 15.7 A/D Conversion Accuracy Definitions Full-scale error Digital output Ideal A/D conversion characteristic Nonlinearity error Actual A/D conversion characteristic FS Analog input voltage Offset error Figure 15.8 A/D Conversion Accuracy Definitions Rev. 2.00 Mar. 15, 2006 Page 539 of 754 REJ09B0199-0200 Section 15 A/D Converter 15.7 Analog Port Pull-Down Function Each analog port has a pull-down MOS. By setting the bits AN15PD to AN0PD in APPDCR to 1 (initial value is 0), the pull-down MOS corresponding to each analog channel is turned on. When the voltage is applied to an analog port from an external circuit, the connection between the analog port and external circuit can be checked by the A/D conversion. Note that APPDCR bits are cleared to 0 by a reset or in software standby mode. Outside This LSI External circuit AN 15 A/D converter AN15PD AN15PD is turned on by setting the AN15PD bit in the APPDCR register. AN14 to AN0 also have the same structure. Figure 15.9 Diagram of Analog Port Pull-Down Function Rev. 2.00 Mar. 15, 2006 Page 540 of 754 REJ09B0199-0200 Section 15 A/D Converter 15.8 15.8.1 Usage Notes Module Stop Mode Setting Operation of the A/D converter can be disabled or enabled using the module stop control register. The initial setting is for operation of the A/D converter to be halted. Register access is enabled by clearing module stop mode. For details, refer to section 19, Power-Down Modes. 15.8.2 Permissible Signal Source Impedance This LSI's analog input is designed so that the conversion accuracy is guaranteed for an input signal for which the signal source impedance is 5 k or less. This specification is provided to enable the A/D converter's sample-and-hold circuit input capacitance to be charged within the sampling time; if the sensor output impedance exceeds 5 k, charging may be insufficient and it may not be possible to guarantee the A/D conversion accuracy. However, if a large capacitance is provided externally for conversion in single mode, the input load will essentially comprise only the internal input resistance of 10 k, and the signal source impedance is ignored. However, since a low-pass filter effect is obtained in this case, it may not be possible to follow an analog signal with a large differential coefficient (e.g., 5 mV/s or greater) (see figure 15.10). When converting a high-speed analog signal or conversion in scan mode, a low-impedance buffer should be inserted. Sensor output impedance R 5 k Sensor input Low-pass filter C 0.1 F This LSI Equivalent circuit of the A/D converter 10 k Cin = 15 pF 20 pF Figure 15.10 Example of Analog Input Circuit Rev. 2.00 Mar. 15, 2006 Page 541 of 754 REJ09B0199-0200 Section 15 A/D Converter 15.8.3 Influences on Absolute Accuracy Adding capacitance results in coupling with GND, and therefore noise in GND may adversely affect absolute accuracy. Be sure to make the connection to an electrically stable GND such as AVss. Care is also required to insure that digital signals on the board do not interfere with filter circuits and filter circuits do not act as antennas. 15.8.4 Setting Range of Analog Power Supply and Other Pins If the conditions shown below are not met, the reliability of the LSI may be adversely affected. * Analog input voltage range The voltage applied to analog input pin ANn during A/D conversion should be in the range AVss VAN AVcc0 and AVss VAN AVcc1. * Relation between AVcc0, AVcc1, AVss and Vcc, Vss As the relationship between AVcc0, AVcc1, AVss and Vcc, Vss, set AVcc0 = Vcc 0.3 V, AVcc1 = Vcc 0.3 V, and AVss = Vss. If the A/D converter is not used, set AVcc0 = Vcc, AVcc1 = Vcc, and AVss = Vss. 15.8.5 Notes on Board Design In board design, digital circuitry and analog circuitry should be as mutually isolated as possible, and layout in which digital circuit signal lines and analog circuit signal lines cross or are in close proximity should be avoided as far as possible. Failure to do so may result in incorrect operation of the analog circuitry due to inductance, adversely affecting A/D conversion values. Digital circuitry must be isolated from the analog input pins (AN0 to AN15) and analog power supply (AVcc0 and AVcc1) by the analog ground (AVss). Also, the analog ground (AVss) should be connected at one point to a stable ground (Vss) on the board. 15.8.6 Notes on Noise Countermeasures A protection circuit connected to prevent damage due to an abnormal voltage such as an excessive surge at the analog input pins (AN0 to AN15) should be connected between AVcc0, AVcc1 and AVss as shown in figure 15.11. Also, the bypass capacitors connected to AVcc0 and AVcc1 and the filter capacitor connected to pins AN0 to AN15 must be connected to AVss. Rev. 2.00 Mar. 15, 2006 Page 542 of 754 REJ09B0199-0200 Section 15 A/D Converter If a filter capacitor is connected, the input currents at pins AN0 to AN15 are averaged, and so an error may arise. Also, when A/D conversion is performed frequently, as in scan mode, if the current charged and discharged by the capacitance of the sample-and-hold circuit in the A/D converter exceeds the current input via the input impedance (Rin), an error will arise in the analog input pin voltage. Careful consideration is therefore required when deciding the circuit constants. AVCC0 and AVCC1 Rin* 2 *1 100 AN0 to AN15 0.1 F AVSS Notes: Values are reference values. 1. 10 F 0.01 F 2. Rin: Input impedance Figure 15.11 Example of Analog Input Protection Circuit Table 15.6 Analog Pin Specifications Item Analog input capacitance Permissible signal source impedance Min Max 20 5 Unit pF k 5 k AN0 to AN15 To A/D converter 20 pF Note: Values are reference values. Figure 15.12 Analog Input Pin Equivalent Circuit Rev. 2.00 Mar. 15, 2006 Page 543 of 754 REJ09B0199-0200 Section 15 A/D Converter 15.8.7 A/D Input Hold Function in Software Standby Mode When this LSI enters software standby mode with A/D conversion enabled, the A/D conversion are retained, and the analog current is equal to as during A/D conversion. If the analog power supply current needs to be reduced in software standby mode, clear the ADST, TRGS1, and TRGS0 bits all to 0 to disable A/D conversion. Rev. 2.00 Mar. 15, 2006 Page 544 of 754 REJ09B0199-0200 Section 16 RAM Section 16 RAM This LSI has a 12-kbyte on-chip high-speed static RAM. The RAM is connected to the CPU by a 32-bit data bus, enabling 1-state read and 2-state write accesses by the CPU to all byte data, word data, and longword data. The on-chip RAM can be enabled or disabled by means of the RAME bit in the system control register (SYSCR). For details on SYSCR, refer to section 3.2.2, System Control Register (SYSCR). Product Classification Flash memory version H8SX/1582 RAM Size 12 kbytes RAM Addresses H'FF9000 to H'FFBFFF Rev. 2.00 Mar. 15, 2006 Page 545 of 754 REJ09B0199-0200 Section 16 RAM Rev. 2.00 Mar. 15, 2006 Page 546 of 754 REJ09B0199-0200 Section 17 Flash Memory (0.18-m F-ZTAT Version) Section 17 Flash Memory (0.18-m F-ZTAT Version) The flash memory has the following features. Figure 17.1 is a block diagram of the flash memory. 17.1 * Size Features ROM Size 256 kbytes ROM Address H'000000 to H'03FFFF (modes 1 to 3) Product Classification H8SX/1582 R5F61582 * Two memory MATs The start addresses of two memory spaces (memory MATs) are allocated to the same address. The mode setting in the initiation determines which memory MAT is initiated first. The memory MATs can be switched by using the bank-switching method after initiation. User MAT initiated at a power-on reset in user mode: 256 kbytes User boot MAT is initiated at a power-on reset in user boot mode: 10 kbytes * Programming/erasing interface by the download of on-chip program This LSI has a programming/erasing program. After downloading this program to the on-chip RAM, programming/erasing can be performed by setting the parameters. * Programming/erasing time Programming time: 3 ms (typ) for 128-byte simultaneous programming, 23.4 s per byte Erasing time: 1000 ms (typ) per 1 block (64 kbytes) * Number of programming The number of programming can be up to 100 times at the minimum. (1 to 100 times are guaranteed.) * Three on-board programming modes Boot mode: Using the on-chip SCI_4, the user MAT and user boot MAT can be programmed/erased. In boot mode, the bit rate between the host and this LSI can be adjusted automatically. User program mode: Using a desired interface, the user MAT can be programmed/erased. User boot mode: Using a desired interface, the user boot program can be made and the user MAT can be programmed/erased. * Off-board programming mode Programmer mode: Using a PROM programmer, the user MAT and user boot MAT can be programmed/erased. Rev. 2.00 Mar. 15, 2006 Page 547 of 754 REJ09B0199-0200 Section 17 Flash Memory (0.18-m F-ZTAT Version) * Programming/erasing protection Protection against programming/erasing of the flash memory can be set by hardware protection, software protection, or error protection. * Flash memory emulation function using the on-chip RAM Realtime emulation of the flash memory programming can be performed by overlaying parts of the flash memory (user MAT) area and the on-chip RAM. Internal address bus Internal data bus (32 bits) FCCS FPCS Module bus FECS FKEY FMATS FTDAR RAMER Flash memory Control unit Memory MAT unit User MAT: 256 kbytes User boot MAT: 10 kbytes Mode pins Operating mode [Legend] FCCS: FPCS: FECS: FKEY: FMATS: FTDAR: RAMER: Flash code control/status register Flash program code select register Flash erase code select register Flash key code register Flash MAT select register Flash transfer destination address register RAM emulation register Note: To read from or write to the registers, the FLSHE bit in SYSCR must be set to 1. Figure 17.1 Block Diagram of Flash Memory Rev. 2.00 Mar. 15, 2006 Page 548 of 754 REJ09B0199-0200 Section 17 Flash Memory (0.18-m F-ZTAT Version) 17.2 Mode Transition Diagram When the mode pins are set in the reset state and reset start is performed, this LSI enters each operating mode as shown in figure 17.2. Although the flash memory can be read in user mode, it cannot be programmed or erased. The flash memory can be programmed or erased in boot mode, user program mode, user boot mode, and programmer mode. The differences between boot mode, user program mode, user boot mode, and programmer mode are shown in table 17.1. RES = 0 RES = 0 Programmer Reset state Programmer mode setting mode ROM disabled mode ROM disabled mode setting 0 S RE =0 RES = er Us m od es in ett g Bo RE ot S= mo 0 ot g bo tin er set Us de mo S RE =0 de se tt ing *2 User mode *1 User program mode User boot mode Boot mode RAM emulation can be available On-board programming mode Notes: In this LSI, the user program mode is defined as the period from the timing when a program concerning programming and erasure is started in user mode to the timing when the program is completed. 1. Programming and erasure is started. 2. Programing and erasure is completed. Figure 17.2 Mode Transition of Flash Memory Rev. 2.00 Mar. 15, 2006 Page 549 of 754 REJ09B0199-0200 Section 17 Flash Memory (0.18-m F-ZTAT Version) Table 17.1 Differences between Boot Mode, User Program Mode, User Boot Mode, and Programmer Mode Item Programming/ erasing environment Programming/ erasing enable MAT Programming/ erasing control All erasure Block division erasure Program data transfer RAM emulation Reset initiation MAT Transition to user mode Boot Mode On-board programming * * User MAT User boot MAT Programming/ erasing interface O O From desired device via RAM O User MAT Programming/ erasing interface O O From desired device via RAM O User boot MAT*2 User Program Mode On-board programming * User MAT User Boot Mode On-board programming * User MAT Programmer Mode Off-board programming * * User MAT User boot MAT Command O (Automatic) O* 1 Command O (Automatic) x Via programmer x From host via SCI x Embedded program storage area Changing mode and reset Completing Programming/ erasure*3 Changing mode and reset Notes: 1. All-erasure is performed. After that, the specified block can be erased. 2. First, the reset vector is fetched from the embedded program storage area. After the flash memory related registers are checked, the reset vector is fetched from the user boot MAT. 3. In this LSI, the user programming mode is defined as the period from the timing when a program concerning programming and erasure is started to the timing when the program is completed. For details on a program concerning programming and erasure, see section 17.8.2, User Program Mode. Rev. 2.00 Mar. 15, 2006 Page 550 of 754 REJ09B0199-0200 Section 17 Flash Memory (0.18-m F-ZTAT Version) 17.3 Memory MAT Configuration The memory MATs of flash memory in this LSI consists of the 256-kbyte user MAT and 10-kbyte user boot MAT. The start addresses of the user MAT and user boot MAT are allocated to the same address. Therefore, when the program execution or data access is performed between the two memory MATs, the memory MATs must be switched by the flash MAT select register (FMATS). The user MAT or user boot MAT can be read in all modes. However, the user boot MAT can be programmed or erased only in boot mode and programmer mode. The size of the user MAT is different from that of the user boot MAT. Addresses which exceed the size of the 10-kbyte user boot MAT should not be accessed. If an attempt is made, data is read as an undefined value. User MAT H'000000 H'000000 10 kbytes H'0027FF User boot MAT 256 kbytes H'03FFFF Figure 17.3 Memory MAT Configuration Rev. 2.00 Mar. 15, 2006 Page 551 of 754 REJ09B0199-0200 Section 17 Flash Memory (0.18-m F-ZTAT Version) 17.4 Block Structure Figure 17.4 shows the block structure of the 256-kbyte user MAT. The heavy-line frames indicate the erase blocks. The thin-line frames indicate the programming units and the values inside the frames stand for the addresses. The user MAT is divided into three 64-kbyte blocks, one 32-kbyte block, and eight 4-kbyte blocks. The user MAT can be erased in these divided block units. Programming is done in 128-byte units starting from where the lower address is H'00 or H'80. RAM emulation can be performed in the eight 4-kbyte blocks. EB0 Erase unit: 4 kbytes EB1 Erase unit: 4 kbytes EB2 Erase unit: 4 kbytes EB3 Erase unit: 4 kbytes EB4 Erase unit: 4 kbytes EB5 Erase unit: 4 kbytes EB6 Erase unit: 4 kbytes EB7 Erase unit: 4 kbytes EB8 Erase unit: 32 kbytes EB9 Erase unit: 64 kbytes EB10 Erase unit: 64 kbytes EB11 Erase unit: 64 kbytes Programming unit: 128 bytes -------------- Programming unit: 128 bytes -------------- Programming unit: 128 bytes -------------- Programming unit: 128 bytes -------------- Programming unit: 128 bytes -------------- Programming unit: 128 bytes -------------- Programming unit: 128 bytes -------------- Programming unit: 128 bytes -------------- Programming unit: 128 bytes H'000000 H'000F80 H'001000 H'001F80 H'002000 H'002F80 H'003000 H'003F80 H'004000 H'004F80 H'005000 H'005F80 H'006000 H'006F80 H'007000 H'007F80 H'008000 H'00FF80 H'010000 H'01FF80 H'020000 H'02FF80 H'030000 H'03FF80 H'000001 H'000F81 H'001001 H'001F81 H'002001 H'002F81 H'003001 H'003F81 H'004001 H'004F81 H'005001 H'005F81 H'006001 H'006F81 H'007001 H'007F81 H'008001 H'00FF81 H'010001 H'01FF81 H'020001 H'02FF81 H'030001 H'03FF81 H'000002 H'000F82 H'001002 H'001F82 H'002002 H'002F82 H'003002 H'003F82 H'004002 H'004F82 H'005002 H'005F82 H'006002 H'006F82 H'007002 H'007F82 H'008002 H'00007F H'000FFF H'00107F H'001FFF H'00207F H'002FFF H'00307F H'003FFF H'00407F H'004FFF H'00507F H'005FFF H'00607F H'006FFF H'00707F H'007FFF H'00807F H'00FFFF H'01007F H'01FFFF H'02007F -------------- H'00FF82 H'010002 Programming unit: 128 bytes -------------- H'01FF82 H'020002 Programming unit: 128 bytes - - - - - - - - - - - - - - H'02FFFF H'02FF82 H'03007F H'030002 Programming unit: 128 bytes H'03FF82 -------------- H'03FFFF Figure 17.4 Block Structure of User MAT Rev. 2.00 Mar. 15, 2006 Page 552 of 754 REJ09B0199-0200 Section 17 Flash Memory (0.18-m F-ZTAT Version) 17.5 Programming/Erasing Interface Programming/erasing of the flash memory is done by downloading an on-chip programming/erasing program to the on-chip RAM and specifying the start address of the programming destination, the program data, and the erase block number using the programming/erasing interface registers and programming/erasing interface parameters. The procedure program for user program mode and user boot mode is made by the user. Figure 17.5 shows the procedure for creating the procedure program. For details, see section 17.8.2, User Program Mode. Start procedure program for programming/erasing Select on-chip program to be downloaded and specify destination Download on-chip program by setting VBR, FKEY, and SCO bit in FCCS Execute initialization (downloaded program execution) Programming (in 128-byte units) or erasing (in 1-block units) (downloaded program execution) No Programming/erasing completed? Yes End procedure program Figure 17.5 Procedure for Creating Procedure Program (1) Selection of On-Chip Program to be Downloaded For programming/erasing, the FLSHE bit in the system control register (SYSCR) must be set to 1 to select user program mode. This LSI has programming/erasing programs which can be downloaded to the on-chip RAM. The on-chip program to be downloaded is selected by the programming/erasing interface registers. The start address of the on-chip RAM where an on-chip program is downloaded is specified by the flash transfer destination address register (FTDAR). Rev. 2.00 Mar. 15, 2006 Page 553 of 754 REJ09B0199-0200 Section 17 Flash Memory (0.18-m F-ZTAT Version) (2) Download of On-Chip Program The on-chip program is automatically downloaded by setting the flash key code register (FKEY) and the SCO bit in the flash code control/status register (FCCS) after initializing the vector base register (VBR). The memory MAT is replaced with the embedded program storage area during download. Since the memory MAT cannot be read during programming/erasing, the procedure program must be executed in a space other than the flash memory (for example, on-chip RAM). Since the download result is returned to the programming/erasing interface parameter, whether download is normally executed or not can be confirmed. The VBR contents can be changed after completion of download. (3) Initialization of Programming/Erasing A pulse with the specified period must be applied when programming or erasing. The specified pulse width is made by the method in which wait loop is configured by the CPU instruction. Accordingly, the operating frequency of the CPU needs to be set before programming/erasing. The operating frequency of the CPU is set by the programming/erasing interface parameter. (4) Execution of Programming/Erasing For programming/erasing, the FLSHE bit in SYSCR must be set to 1 to make a transition to user program mode. The start address of the programming destination and the program data are specified in 128-byte units when programming. The block to be erased is specified with the erase block number in erase-block units when erasing. Specifications of the start address of the programming destination, program data, and erase block number are performed by the programming/erasing interface parameters, and the on-chip program is initiated. The on-chip program is executed by using the JSR or BSR instruction and executing the subroutine call of the specified address in the on-chip RAM. The execution result is returned to the programming/erasing interface parameter. The area to be programmed must be erased in advance when programming flash memory. All interrupts are disabled during programming/erasing. (5) When Programming/Erasing is Executed Consecutively When processing does not end by 128-byte programming or 1-block erasure, consecutive programming/erasing can be realized by updating the start address of the programming destination and program data, or the erase block number. Since the downloaded on-chip program is left in the on-chip RAM even after programming/erasing completes, download and initialization are not required when the same processing is executed consecutively. Rev. 2.00 Mar. 15, 2006 Page 554 of 754 REJ09B0199-0200 Section 17 Flash Memory (0.18-m F-ZTAT Version) 17.6 Input/Output Pins The flash memory is controlled through the input/output pins shown in table 17.2. Table 17.2 Pin Configuration Pin Name RES MD1 and MD0 TxD4 RxD4 I/O Input Input Output Input Function Reset Set operating mode of this LSI Serial transmit data output (used in boot mode) Serial receive data input (used in boot mode) 17.7 Register Descriptions The flash memory has the following registers. To access these registers, the FLSHE bit in the system control register (SYSCR) must be set to 1. For details on SYSCR, see section 3.2.2, System Control Register (SYSCR). Programming/Erasing Interface Registers: * * * * * * Flash code control/status register (FCCS) Flash program code select register (FPCS) Flash erase code select register (FECS) Flash key code register (FKEY) Flash MAT select register (FMATS) Flash transfer destination address register (FTDAR) Programming/Erasing Interface Parameters: * * * * * * Download pass and fail result parameter (DPFR) Flash pass and fail result parameter (FPFR) Flash program/erase frequency parameter (FPEFEQ) Flash multipurpose address area parameter (FMPAR) Flash multipurpose data destination area parameter (FMPDR) Flash erase block select parameter (FEBS) * RAM emulation register (RAMER) Rev. 2.00 Mar. 15, 2006 Page 555 of 754 REJ09B0199-0200 Section 17 Flash Memory (0.18-m F-ZTAT Version) There are several operating modes for accessing the flash memory. Respective operating modes, registers, and parameters are assigned to the user MAT and user boot MAT. The correspondence between operating modes and registers/parameters for use is shown in table 17.3. Table 17.3 Registers/Parameters and Target Modes Register/Parameter Programming/ erasing interface registers FCCS FPCS FECS FKEY FMATS FTDAR Programming/ erasing interface parameters DPFR FPFR Download O O O O O O Initialization O O Programming Erasure O O* O O O 1 Read RAM Emulation O O* O O 1 O* 2 O FPEFEQ FMPAR FMPDR FEBS RAM emulation RAMER Notes: 1. The setting is required when programming or erasing the user MAT in user boot mode. 2. The setting may be required according to the combination of initiation mode and read target memory MAT. 17.7.1 Programming/Erasing Interface Registers The programming/erasing interface registers are 8-bit registers that can be accessed only in bytes. These registers are initialized by a power-on reset. Rev. 2.00 Mar. 15, 2006 Page 556 of 754 REJ09B0199-0200 Section 17 Flash Memory (0.18-m F-ZTAT Version) (1) Flash Code Control/Status Register (FCCS) FCCS monitors errors during programming/erasing the flash memory and requests the on-chip program to be downloaded to the on-chip RAM. Bit Bit Name Initial Value R/W 7 -- 1 R 6 -- 0 R 5 -- 0 R 4 FLER 0 R 3 -- 0 R 2 -- 0 R 1 -- 0 R 0 SCO 0 (R)/W Bit 7 6 5 4 Initial Bit Name Value FLER 1 0 0 0 R/W R R R R Description Reserved These are read-only bits and cannot be modified. Flash Memory Error Indicates that an error has occurred during programming or erasing the flash memory. When this bit is set to 1, the flash memory enters the error protection state. When this bit is set to 1, high voltage is applied to the internal flash memory. To reduce the damage to the flash memory, the reset must be released after the reset input period (period of RES = 0) of at least 100 s. 0: Flash memory operates normally (Error protection is invalid) [Clearing condition] * At a power-on reset 1: An error occurs during programming/erasing flash memory (Error protection is valid) [Setting conditions] * * When an interrupt, such as NMI, occurs during programming/erasing. When the flash memory is read during programming/erasing (including a vector read and an instruction fetch). When the SLEEP instruction is executed during programming/erasing (including software standby mode). When a bus master other than the CPU, such as the DTC and DMAC, obtains bus mastership during programming/erasing. * * Rev. 2.00 Mar. 15, 2006 Page 557 of 754 REJ09B0199-0200 Section 17 Flash Memory (0.18-m F-ZTAT Version) Bit 3 to 1 0 Initial Bit Name Value SCO All 0 0 R/W R (R)/W* Description Reserved These are read-only bits and cannot be modified. Source Program Copy Operation Requests the on-chip programming/erasing program to be downloaded to the on-chip RAM. When this bit is set to 1, the on-chip program which is selected by FPCS or FECS is automatically downloaded in the on-chip RAM area specified by FTDAR. In order to set this bit to 1, the RAM emulation mode must be canceled, H'A5 must be written to FKEY, and this operation must be executed in the on-chip RAM. Dummy read of FCCS must be executed twice immediately after setting this bit to 1. All interrupts must be disabled during download. This bit is cleared to 0 when download is completed. During program download initiated with this bit, particular processing which accompanies bankswitching of the program storage area is executed. Before a download request, initialize the VBR contents to H'00000000. After download is completed, the VBR contents can be changed. 0: Download of the programming/erasing program is not requested. [Clearing condition] * When download is completed 1: Download of the programming/erasing program is requested. [Setting conditions] (When all of the following conditions are satisfied) * * * Not in RAM emulation mode (the RAMS bit in RAMER is cleared to 0) H'A5 is written to FKEY Setting of this bit is executed in the on-chip RAM Note: * This is a write-only bit. This bit is always read as 0. Rev. 2.00 Mar. 15, 2006 Page 558 of 754 REJ09B0199-0200 Section 17 Flash Memory (0.18-m F-ZTAT Version) (2) Flash Program Code Select Register (FPCS) FPCS selects the programming program to be downloaded. Bit Bit Name Initial Value R/W 7 -- 0 R 6 -- 0 R 5 -- 0 R 4 -- 0 R 3 -- 0 R 2 -- 0 R 1 -- 0 R 0 PPVS 0 R/W Bit 7 to 1 0 Initial Bit Name Value PPVS All 0 0 R/W R R/W Description Reserved These are read-only bits and cannot be modified. Program Pulse Verify Selects the programming program to be downloaded. 0: Programming program is not selected. [Clearing condition] When transfer is completed 1: Programming program is selected. (3) Flash Erase Code Select Register (FECS) FECS selects the erasing program to be downloaded. Bit Bit Name Initial Value R/W 7 -- 0 R 6 -- 0 R 5 -- 0 R 4 -- 0 R 3 -- 0 R 2 -- 0 R 1 -- 0 R 0 EPVB 0 R/W Bit 7 to 1 0 Initial Bit Name Value EPVB All 0 0 R/W R R/W Description Reserved These are read-only bits and cannot be modified. Erase Pulse Verify Block Selects the erasing program to be downloaded. 0: Erasing program is not selected. [Clearing condition] When transfer is completed 1: Erasing program is selected. Rev. 2.00 Mar. 15, 2006 Page 559 of 754 REJ09B0199-0200 Section 17 Flash Memory (0.18-m F-ZTAT Version) (4) Flash Key Code Register (FKEY) FKEY is a register for software protection that enables to download the on-chip program and perform programming/erasing of the flash memory. Bit Bit Name Initial Value R/W 7 K7 0 R/W 6 K6 0 R/W 5 K5 0 R/W 4 K4 0 R/W 3 K3 0 R/W 2 K2 0 R/W 1 K1 0 R/W 0 K0 0 R/W Bit 7 6 5 4 3 2 1 0 Initial Bit Name Value K7 K6 K5 K4 K3 K2 K1 K0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Key Code When H'A5 is written to FKEY, writing to the SCO bit in FCCS is enabled. When a value other than H'A5 is written, the SCO bit cannot be set to 1. Therefore, the on-chip program cannot be downloaded to the on-chip RAM. Only when H'5A is written can programming/erasing of the flash memory be executed. When a value other than H'5A is written, even if the programming/erasing program is executed, programming/erasing cannot be performed. H'A5: Writing to the SCO bit is enabled. (The SCO bit cannot be set to 1 when FKEY is a value other than H'A5.) H'5A: Programming/erasing of the flash memory is enabled. (When FKEY is a value other than H'5A, the software protection state is entered.) H'00: Initial value Rev. 2.00 Mar. 15, 2006 Page 560 of 754 REJ09B0199-0200 Section 17 Flash Memory (0.18-m F-ZTAT Version) (5) Flash MAT Select Register (FMATS) FMATS selects the user MAT or user boot MAT. Writing to FMATS should be done when a program in the on-chip RAM is being executed. Bit Bit Name Initial Value R/W 7 MS7 0/1* R/W 6 MS6 0 R/W 5 MS5 0/1* R/W 4 MS4 0 R/W 3 MS3 0/1* R/W 2 MS2 0 R/W 1 MS1 0/1* R/W 0 MS0 0 R/W Note: * This bit is set to 1 in user boot mode, otherwise cleared to 0. Bit 7 6 5 4 3 2 1 0 Initial Bit Name Value MS7 MS6 MS5 MS4 MS3 MS2 MS1 MS0 0/1* 0 0/1* 0 0/1* 0 0/1* 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description MAT Select The memory MATs can be switched by writing a value to FMATS. When H'AA is written to FMATS, the user boot MAT is selected. When a value other than H'AA is written, the user MAT is selected. Switch the MATs following the memory MAT switching procedure in section 17.11, Switching between User MAT and User Boot MAT. The user boot MAT cannot be selected by FMATS in user programming mode. The user boot MAT can be selected in boot mode or programmer mode. H'AA: The user boot MAT is selected. (The user MAT is selected when FMATS is a value other than H'AA.) (Initial value when initiated in user boot mode.) H'00: The user MAT is selected. (Initial value when initiated in a mode except for user boot mode.) Note: * This bit is set to 1 in user boot mode, otherwise cleared to 0. Rev. 2.00 Mar. 15, 2006 Page 561 of 754 REJ09B0199-0200 Section 17 Flash Memory (0.18-m F-ZTAT Version) (6) Flash Transfer Destination Address Register (FTDAR) FTDAR specifies the start address of the on-chip RAM at which to download an on-chip program. FTDAR must be set before setting the SCO bit in FCCS to 1. Bit Bit Name Initial Value R/W 7 TDER 0 R/W 6 TDA6 0 R/W 5 TDA5 0 R/W 4 TDA4 0 R/W 3 TDA3 0 R/W 2 TDA2 0 R/W 1 TDA1 0 R/W 0 TDA0 0 R/W Bit 7 Initial Bit Name Value TDER 0 R/W R/W Description Transfer Destination Address Setting Error This bit is set to 1 when an error has occurred in setting the start address specified by bits TDA6 to TDA0. A start address error is determined by whether the value set in bits TDA6 to TDA0 is within the range of H'00 to H'02 when download is executed by setting the SCO bit in FCCS to 1. Make sure that this bit is cleared to 0 before setting the SCO bit to 1 and the value specified by bits TDA6 to TDA0 should be within the range of H'00 to H'02. 0: The value specified by bits TDA6 to TDA0 is within the range. 1: The value specified by bits TDA6 to TDA0 is between H'03 and H'FF and download has stopped. 6 5 4 3 2 1 0 TDA6 TDA5 TDA4 TDA3 TDA2 TDA1 TDA0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W Transfer Destination Address Specifies the on-chip RAM start address of the download destination. A value between H'00 and H'02, and up to 4 kbytes can be specified as the start address of the on-chip RAM. H'00: H'01: H'02: H'FF9000 is specified as the start address. H'FFA000 is specified as the start address. H'FFB000 is specified as the start address. H'03 to H'7F: Setting prohibited. (Specifying a value from H'03 to H'7F sets the TDER bit to 1 and stops download of the on-chip program.) Rev. 2.00 Mar. 15, 2006 Page 562 of 754 REJ09B0199-0200 Section 17 Flash Memory (0.18-m F-ZTAT Version) 17.7.2 Programming/Erasing Interface Parameters The programming/erasing interface parameters specify the operating frequency, storage place for program data, start address of programming destination, and erase block number, and exchanges the execution result. These parameters use the general registers of the CPU (ER0 and ER1) or the on-chip RAM area. The initial values of programming/erasing interface parameters are undefined at a power-on reset or a transition to software standby mode. Since registers of the CPU except for R0 are saved in the stack area during download of an onchip program, initialization, programming, or erasing, allocate the stack area before performing these operations (the maximum stack size is 128 bytes). The return value of the processing result is written in R0. The programming/erasing interface parameters are used in download control, initialization before programming or erasing, programming, and erasing. Table 17.4 shows the usable parameters and target modes. The meaning of the bits in the flash pass and fail result parameter (FPFR) varies in initialization, programming, and erasure. Table 17.4 Parameters and Target Modes Parameter DPFR FPFR FPEFEQ FMPAR FMPDR FEBS Download Initialization Programming Erasure R/W R/W R/W R/W R/W R/W R/W Initial Value Undefined Undefined Undefined Undefined Undefined Undefined Allocation On-chip RAM* R0L of CPU ER0 of CPU ER1 of CPU ER0 of CPU ER0 of CPU O * O O O O O O O Note: A single byte of the start address of the on-chip RAM specified by FTDAR Download Control: The on-chip program is automatically downloaded by setting the SCO bit in FCCS to 1. The on-chip RAM area to download the on-chip program is the 4-kbyte area starting from the start address specified by FTDAR. Download is set by the programming/erasing interface registers, and the download pass and fail result parameter (DPFR) indicates the return value. Rev. 2.00 Mar. 15, 2006 Page 563 of 754 REJ09B0199-0200 Section 17 Flash Memory (0.18-m F-ZTAT Version) Initialization before Programming/Erasing: The on-chip program includes the initialization program. A pulse with the specified period must be applied when programming or erasing. The specified pulse width is made by the method in which wait loop is configured by the CPU instruction. Accordingly, the operating frequency of the CPU must be set. The initial program is set as a parameter of the programming/erasing program which has been downloaded to perform these settings. Programming: When the flash memory is programmed, the start address of the programming destination on the user MAT and the program data must be passed to the programming program. The start address of the programming destination on the user MAT must be stored in general register ER1. This parameter is called the flash multipurpose address area parameter (FMPAR). The program data is always in 128-byte units. When the program data does not satisfy 128 bytes, 128-byte program data is prepared by filling the dummy code (H'FF). The boundary of the start address of the programming destination on the user MAT is aligned at an address where the lower eight bits (A7 to A0) are H'00 or H'80. The program data for the user MAT must be prepared in consecutive areas. The program data must be in a consecutive space which can be accessed using the MOV.B instruction of the CPU and is not in the flash memory space. The start address of the area that stores the data to be written in the user MAT must be set in general register ER0. This parameter is called the flash multipurpose data destination area parameter (FMPDR). For details on the programming procedure, see section 17.8.2, User Program Mode. Erasure: When the flash memory is erased, the erase block number on the user MAT must be passed to the erasing program which is downloaded. The erase block number on the user MAT must be set in general register ER0. This parameter is called the flash erase block select parameter (FEBS). One block is selected from the block numbers of 0 to 11 as the erase block number. For details on the erasing procedure, see section 17.8.2, User Program Mode. Rev. 2.00 Mar. 15, 2006 Page 564 of 754 REJ09B0199-0200 Section 17 Flash Memory (0.18-m F-ZTAT Version) (1) Download Pass and Fail Result Parameter (DPFR: Single Byte of Start Address in OnChip RAM Specified by FTDAR) DPFR indicates the return value of the download result. The DPFR value is used to determine the download result. Bit Bit Name 7 -- 6 -- 5 -- 4 -- 3 -- 2 SS 1 FK 0 SF Bit 7 to 3 2 Initial Bit Name Value SS R/W R/W Description Unused These bits return 0. Source Select Error Detect Only one type can be specified for the on-chip program which can be downloaded. When the program to be downloaded is not selected, more than two types of programs are selected, or a program which is not mapped is selected, an error occurs. 0: Download program selection is normal 1: Download program selection is abnormal 1 FK R/W Flash Key Register Error Detect Checks the FKEY value (H'A5) and returns the result. 0: FKEY setting is normal (H'A5) 1: FKEY setting is abnormal (value other than H'A5) 0 SF R/W Success/Fail Returns the download result. Reads back the program downloaded to the on-chip RAM and determines whether it has been transferred to the on-chip RAM. 0: Download of the program has ended normally (no error) 1: Download of the program has ended abnormally (error occurs) Rev. 2.00 Mar. 15, 2006 Page 565 of 754 REJ09B0199-0200 Section 17 Flash Memory (0.18-m F-ZTAT Version) (2) Flash Pass and Fail Parameter (FPFR: General Register R0L of CPU) FPFR indicates the return values of the initialization, programming, and erasure results. The meaning of the bits in FPFR varies depending on the processing. (a) Initialization before programming/erasing FPFR indicates the return value of the initialization result. Bit Bit Name 7 -- 6 -- 5 -- 4 -- 3 -- 2 -- 1 FQ 0 SF Bit 7 to 2 1 Initial Bit Name Value FQ R/W R/W Description Unused These bits return 0. Frequency Error Detect Compares the specified CPU operating frequency with the operating frequencies supported by this LSI, and returns the result. 0: Setting of operating frequency is normal 1: Setting of operating frequency is abnormal 0 SF R/W Success/Fail Returns the initialization result. 0: Initialization has ended normally (no error) 1: Initialization has ended abnormally (error occurs) Rev. 2.00 Mar. 15, 2006 Page 566 of 754 REJ09B0199-0200 Section 17 Flash Memory (0.18-m F-ZTAT Version) (b) Programming FPFR indicates the return value of the programming result. Bit Bit Name 7 -- 6 MD 5 EE 4 FK 3 -- 2 WD 1 WA 0 SF Bit 7 6 Initial Bit Name Value MD R/W R/W Description Unused Returns 0. Programming Mode Related Setting Error Detect Detects the error protection state and returns the result. When the error protection state is entered, this bit is set to 1. Whether the error protection state is entered or not can be confirmed with the FLER bit in FCCS. For conditions to enter the error protection state, see section 17.9.3, Error Protection. 0: Normal operation (FLER = 0) 1: Error protection state, and programming cannot be performed (FLER = 1) 5 EE R/W Programming Execution Error Detect Writes 1 to this bit when the specified data could not be written because the user MAT was not erased. If this bit is set to 1, there is a high possibility that the user MAT has been written to partially. In this case, after removing the error factor, erase the user MAT. If FMATS is set to H'AA and the user boot MAT is selected, an error occurs when programming is performed. In this case, both the user MAT and user boot MAT have not been written to. Programming the user boot MAT should be performed in boot mode or programmer mode. 0: Programming has ended normally 1: Programming has ended abnormally (programming result is not guaranteed) Rev. 2.00 Mar. 15, 2006 Page 567 of 754 REJ09B0199-0200 Section 17 Flash Memory (0.18-m F-ZTAT Version) Bit 4 Initial Bit Name Value FK R/W R/W Description Flash Key Register Error Detect Checks the FKEY value (H'5A) before programming starts, and returns the result. 0: FKEY setting is normal (H'5A) 1: FKEY setting is abnormal (value other than H'5A) 3 2 WD R/W Unused Returns 0. Write Data Address Detect When an address not in the flash memory area is specified as the start address of the storage destination for the program data, an error occurs. 0: Setting of the start address of the storage destination for the program data is normal 1: Setting of the start address of the storage destination for the program data is abnormal 1 WA R/W Write Address Error Detect When the following items are specified as the start address of the programming destination, an error occurs. * * An area other than flash memory The specified address is not aligned with the 128byte boundary (lower eight bits of the address are other than H'00 and H'80) 0: Setting of the start address of the programming destination is normal 1: Setting of the start address of the programming destination is abnormal 0 SF R/W Success/Fail Returns the programming result. 0: Programming has ended normally (no error) 1: Programming has ended abnormally (error occurs) Rev. 2.00 Mar. 15, 2006 Page 568 of 754 REJ09B0199-0200 Section 17 Flash Memory (0.18-m F-ZTAT Version) (c) Erasure FPFR indicates the return value of the erasure result. Bit Bit Name 7 -- 6 MD 5 EE 4 FK 3 EB 2 -- 1 -- 0 SF Bit 7 6 Initial Bit Name Value MD R/W R/W Description Unused Returns 0. Erasure Mode Related Setting Error Detect Detects the error protection state and returns the result. When the error protection state is entered, this bit is set to 1. Whether the error protection state is entered or not can be confirmed with the FLER bit in FCCS. For conditions to enter the error protection state, see section 17.9.3, Error Protection. 0: Normal operation (FLER = 0) 1: Error protection state, and programming cannot be performed (FLER = 1) 5 EE R/W Erasure Execution Error Detect Returns 1 when the user MAT could not be erased or when the flash memory related register settings are partially changed. If this bit is set to 1, there is a high possibility that the user MAT has been erased partially. In this case, after removing the error factor, erase the user MAT. If FMATS is set to H'AA and the user boot MAT is selected, an error occurs when erasure is performed. In this case, both the user MAT and user boot MAT have not been erased. Erasing of the user boot MAT should be performed in boot mode or programmer mode. 0: Erasure has ended normally 1: Erasure has ended abnormally Rev. 2.00 Mar. 15, 2006 Page 569 of 754 REJ09B0199-0200 Section 17 Flash Memory (0.18-m F-ZTAT Version) Bit 4 Initial Bit Name Value FK R/W R/W Description Flash Key Register Error Detect Checks the FKEY value (H'5A) before erasure starts, and returns the result. 0: FKEY setting is normal (H'5A) 1: FKEY setting is abnormal (value other than H'5A) 3 EB R/W Erase Block Select Error Detect Checks whether the specified erase block number is in the block range of the user MAT, and returns the result. 0: Setting of erase block number is normal 1: Setting of erase block number is abnormal 2, 1 0 SF R/W Unused These bits return 0. Success/Fail Indicates the erasure result. 0: Erasure has ended normally (no error) 1: Erasure has ended abnormally (error occurs) (3) Flash Program/Erase Frequency Parameter (FPEFEQ: General Register ER0 of CPU) FPEFEQ sets the operating frequency of the CPU. The CPU operating frequency available in this LSI ranges from 8 MHz to 48 MHz. Bit Bit Name 31 -- 30 -- 29 -- 28 -- 27 -- 26 -- 25 -- 24 -- Bit Bit Name 23 -- 22 -- 21 -- 20 -- 19 -- 18 -- 17 -- 16 -- Bit Bit Name 15 F15 14 F14 13 F13 12 F12 11 F11 10 F10 9 F9 8 F8 Bit Bit Name 7 F7 6 F6 5 F5 4 F4 3 F3 2 F2 1 F1 0 F0 Rev. 2.00 Mar. 15, 2006 Page 570 of 754 REJ09B0199-0200 Section 17 Flash Memory (0.18-m F-ZTAT Version) Bit Initial Bit Name Value R/W R/W Description Unused These bits should be cleared to 0. Frequency Set These bits set the operating frequency of the CPU. When the PLL multiplication function is used, set the multiplied frequency. The setting value must be calculated as follows: 1. The operating frequency shown in MHz units must be rounded in a number of three decimal places and be shown in a number of two decimal places. 2. The value multiplied by 100 is converted to the binary digit and is written to FPEFEQ (general register ER0). For example, when the operating frequency of the CPU is 33.000 MHz, the value is as follows: 1. The number of three decimal places of 33.000 is rounded. 2. The formula of 33.00 x 100 = 3300 is converted to the binary digit and B'0000 1100 1110 0100 (H'0CE4) is set to ER0. 31 to 16 15 to 0 F15 to F0 Rev. 2.00 Mar. 15, 2006 Page 571 of 754 REJ09B0199-0200 Section 17 Flash Memory (0.18-m F-ZTAT Version) (4) Flash Multipurpose Address Area Parameter (FMPAR: General Register ER1 of CPU) FMPAR stores the start address of the programming destination on the user MAT. When an address in an area other than the flash memory is set, or the start address of the programming destination is not aligned with the 128-byte boundary, an error occurs. The error occurrence is indicated by the WA bit in FPFR. Bit Bit Name 31 MOA31 30 MOA30 29 MOA29 28 MOA28 27 MOA27 26 MOA26 25 MOA25 24 MOA24 Bit Bit Name 23 MOA23 22 MOA22 21 MOA21 20 MOA20 19 MOA19 18 MOA18 17 MOA17 16 MOA16 Bit Bit Name 15 MOA15 14 MOA14 13 MOA13 12 MOA12 11 MOA11 10 MOA10 9 MOA9 8 MOA8 Bit Bit Name 7 MOA7 6 MOA6 5 MOA5 4 MOA4 3 MOA3 2 MOA2 1 MOA1 0 MOA0 Bit 31 to 0 Initial Bit Name Value MOA31 to MOA0 R/W R/W Description These bits store the start address of the programming destination on the user MAT. Consecutive 128-byte programming is executed starting from the specified start address of the user MAT. Therefore, the specified start address of the programming destination becomes a 128-byte boundary, and MOA6 to MOA0 are always cleared to 0. Rev. 2.00 Mar. 15, 2006 Page 572 of 754 REJ09B0199-0200 Section 17 Flash Memory (0.18-m F-ZTAT Version) (5) Flash Multipurpose Data Destination Parameter (FMPDR: General Register ER0 of CPU) FMPDR stores the start address in the area which stores the data to be programmed in the user MAT. When the storage destination for the program data is in flash memory, an error occurs. The error occurrence is indicated by the WD bit in FPFR. Bit Bit Name 31 MOD31 30 MOD30 29 MOD29 28 MOD28 27 MOD27 26 MOD26 25 MOD25 24 MOD24 Bit Bit Name 23 MOD23 22 MOD22 21 MOD21 20 MOD20 19 MOD19 18 MOD18 17 MOD17 16 MOD16 Bit Bit Name 15 MOD15 14 MOD14 13 MOD13 12 MOD12 11 MOD11 10 MOD10 9 MOD9 8 MOD8 Bit Bit Name 7 MOD7 6 MOD6 5 MOD5 4 MOD4 3 MOD3 2 MOD2 1 MOD1 0 MOD0 Bit 31 to 0 Initial Bit Name Value MOD31 to MOD0 R/W R/W Description These bits store the start address of the area which stores the program data for the user MAT. Consecutive 128-byte data is programmed to the user MAT starting from the specified start address. Rev. 2.00 Mar. 15, 2006 Page 573 of 754 REJ09B0199-0200 Section 17 Flash Memory (0.18-m F-ZTAT Version) (6) Flash Erase Block Select Parameter (FEBS: General Register ER0 of CPU) FEBS specifies the erase block number. Settable values for the erase block numbers range from 0 to 11 (H'00000000 to H'0000000B). A value of 0 corresponds to block EB0 and a value of 11 corresponds to block EB11. An error occurs when a value outside the range from 0 to 11 is set. Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W 7 -- R/W 6 -- R/W 5 -- R/W 4 -- R/W 3 -- R/W 2 -- R/W 1 -- R/W 0 -- R/W 15 -- R/W 14 -- R/W 13 -- R/W 12 -- R/W 11 -- R/W 10 -- R/W 9 -- R/W 8 -- R/W 23 -- R/W 22 -- R/W 21 -- R/W 20 -- R/W 19 -- R/W 18 -- R/W 17 -- R/W 16 31 30 29 28 27 26 25 24 Rev. 2.00 Mar. 15, 2006 Page 574 of 754 REJ09B0199-0200 Section 17 Flash Memory (0.18-m F-ZTAT Version) 17.7.3 RAM Emulation Register (RAMER) RAMER specifies the user MAT area overlaid with part of the on-chip RAM (H'FFA000 to H'FFAFFF) when performing emulation of programming the user MAT. RAMER should be set in user mode or user program mode. To ensure dependable emulation, the memory MAT to be emulated must not be accessed immediately after changing the RAMER contents. When accessed at such a timing, correct operation is not guaranteed. Bit Bit Name Initial Value R/W 7 -- 0 R 6 -- 0 R 5 -- 0 R 4 -- 0 R 3 RAMS 0 R/W 2 RAM2 0 R/W 1 RAM1 0 R/W 0 RAM0 0 R/W Bit 7 to 4 3 Initial Bit Name Value RAMS 0 0 R/W R R/W Description Reserved These are read-only bits and cannot be modified. RAM Select Selects the function which emulates the flash memory using the on-chip RAM. 0: Disables RAM emulation function 1: Enables RAM emulation function (all blocks of the user MAT are protected against programming and erasing) 2 1 0 RAM2 RAM1 RAM0 0 0 0 R/W R/W R/W Flash Memory Area Select These bits select the user MAT area overlaid with the on-chip RAM when RAMS = 1. The following areas correspond to the 4-kbyte erase blocks. 000: H'000000 to H'000FFF (EB0) 001: H'001000 to H'001FFF (EB1) 010: H'002000 to H'002FFF (EB2) 011: H'003000 to H'003FFF (EB3) 100: H'004000 to H'004FFF (EB4) 101: H'005000 to H'005FFF (EB5) 110: H'006000 to H'006FFF (EB6) 111: H'007000 to H'007FFF (EB7) Rev. 2.00 Mar. 15, 2006 Page 575 of 754 REJ09B0199-0200 Section 17 Flash Memory (0.18-m F-ZTAT Version) 17.8 On-Board Programming Mode When the mode pins (MD0, MD1, and MD2) are set to on-board programming mode and the reset start is executed, a transition is made to on-board programming mode in which the on-chip flash memory can be programmed/erased. On-board programming mode has three operating modes: boot mode, user boot mode, and user program mode. Table 17.5 shows the pin setting for each operating mode. For details on the state transition of each operating mode for flash memory, see figure 17.2. Table 17.5 On-Board Programming Mode Setting Mode Setting User boot mode Boot mode User program mode MD1 0 1 1 MD0 1 0 1 17.8.1 Boot Mode Boot mode executes programming/erasing of the user MAT or user boot MAT by means of the control command and program data transmitted from the externally connected host via the on-chip SCI_4. In boot mode, the tool for transmitting the control command and program data, and the program data must be prepared in the host. The serial communication mode is set to asynchronous mode. The system configuration in boot mode is shown in figure 17.6. Interrupts are ignored in boot mode. Configure the user system so that interrupts do not occur. This LSI Software for analyzing control commands (on-chip) Control command, program data RxD4 SCI_4 TxD4 On-chip RAM Flash memory Host Programming tool and program data Response Figure 17.6 System Configuration in Boot Mode Rev. 2.00 Mar. 15, 2006 Page 576 of 754 REJ09B0199-0200 Section 17 Flash Memory (0.18-m F-ZTAT Version) (1) Serial Interface Setting by Host The SCI_4 is set to asynchronous mode, and the serial transmit/receive format is set to 8-bit data, one stop bit, and no parity. When a transition to boot mode is made, the boot program embedded in this LSI is initiated. When the boot program is initiated, this LSI measures the low period of asynchronous serial communication data (H'00) transmitted consecutively by the host, calculates the bit rate, and adjusts the bit rate of the SCI_4 to match that of the host. When bit rate adjustment is completed, this LSI transmits 1 byte of H'00 to the host as the bit adjustment end sign. When the host receives this bit adjustment end sign normally, it transmits 1 byte of H'55 to this LSI. When reception is not executed normally, initiate boot mode again. The bit rate may not be adjusted within the allowable range depending on the combination of the bit rate of the host and the system clock frequency of this LSI. Therefore, the transfer bit rate of the host and the system clock frequency of this LSI must be as shown in table 17.6. Start bit D0 D1 D2 D3 D4 D5 D6 D7 Stop bit Measure low period (9 bits) (data is H'00) High period of at least 1 bit Figure 17.7 Automatic-Bit-Rate Adjustment Operation Table 17.6 System Clock Frequency for Automatic-Bit-Rate Adjustment Bit Rate of Host 9,600 bps 19,200 bps System Clock Frequency of This LSI External Clock Frequency 8 to 18 MHz 16 to 18 MHz 4 to 9 MHz 8 to 9 MHz Rev. 2.00 Mar. 15, 2006 Page 577 of 754 REJ09B0199-0200 Section 17 Flash Memory (0.18-m F-ZTAT Version) (2) State Transition Diagram The state transition after boot mode is initiated is shown in figure 17.8. (Bit rate adjustment) H'00, ..., H'00 reception H'00 transmission (adjustment completed) Bit rate adjustment rece ption Boot mode initiation (reset by boot mode) 1. H'55 Inquiry command reception 2. Wait for inquiry setting command Inquiry command response Processing of inquiry setting command 3. All user MAT and user boot MAT erasure 4. Wait for programming/erasing command Read/check command reception Command response Processing of read/check command (Programming completion) (Erasure completion) (Erasure selection command reception) (Erase-block specification) (Erasure selection command reception) (Program data transmission) Wait for erase-block data Wait for program data Figure 17.8 Boot Mode State Transition Diagram Rev. 2.00 Mar. 15, 2006 Page 578 of 754 REJ09B0199-0200 Section 17 Flash Memory (0.18-m F-ZTAT Version) 1. After boot mode is initiated, the bit rate of the SCI_4 is adjusted with that of the host. 2. Inquiry information about the size, configuration, start address, and support status of the user MAT is transmitted to the host. 3. After inquiries have finished, all user MAT and user boot MAT are automatically erased. 4. When the program preparation notice is received, the state of waiting for program data is entered. The start address of the programming destination and program data must be transmitted after the programming command is transmitted. When programming is finished, the start address of the programming destination must be set to H'FFFFFFFF and transmitted. Then the state of waiting for program data is returned to the state of waiting for programming/erasing command. When the erasure preparation notice is received, the state of waiting for erase block data is entered. The erase block number must be transmitted after the erasing command is transmitted. When the erasure is finished, the erase block number must be set to H'FF and transmitted. Then the state of waiting for erase block data is returned to the state of waiting for programming/erasing command. Erasure must be executed when the specified block is programmed without a reset start after programming is executed in boot mode. When programming can be executed by only one operation, all blocks are erased before entering the state of waiting for programming/erasing command or another command. Thus, in this case, the erasing operation is not required. The commands other than the programming/erasing command perform sum check, blank check (erasure check), and memory read of the user MAT/user boot MAT and acquisition of current status information. Memory read of the user MAT/user boot MAT can only read the data programmed after all user MAT/user boot MAT has automatically been erased. No other data can be read. Rev. 2.00 Mar. 15, 2006 Page 579 of 754 REJ09B0199-0200 Section 17 Flash Memory (0.18-m F-ZTAT Version) 17.8.2 User Program Mode Programming/erasing of the user MAT is executed by downloading an on-chip program. The user boot MAT cannot be programmed/erased in user program mode. The programming/erasing flow is shown in figure 17.9. Since high voltage is applied to the internal flash memory during programming/erasing, a transition to the reset state or hardware standby mode must not be made during programming/erasing. A transition to the reset state or hardware standby mode during programming/erasing may damage the flash memory. If a reset is input, the reset must be released after the reset input period (period of RES = 0) of at least 100 s. Programming/erasing start 1. Exit RAM emulation mode beforehand. Download is not allowed in emulation mode. 2. When the program data is adjusted in emulation mode, select the download destination specified by FTDAR carefully. Make sure that the download area does not overlap the emulation area. 3. Programming/erasing is executed only in the on-chip RAM. 4. After programming/erasing is finished, protect the flash memory by the hardware protection. When programming, program data is prepared Programming/erasing procedure program is transferred to the on-chip RAM and executed Programming/erasing end Figure 17.9 Programming/Erasing Flow Rev. 2.00 Mar. 15, 2006 Page 580 of 754 REJ09B0199-0200 Section 17 Flash Memory (0.18-m F-ZTAT Version) (1) On-Chip RAM Address Map when Programming/Erasing is Executed Parts of the procedure program that is made by the user, like download request, programming/erasing procedure, and decision of the result, must be executed in the on-chip RAM. Since the on-chip program to be downloaded is embedded in the on-chip RAM, make sure the onchip program and procedure program do not overlap. Figure 17.10 shows the area of the on-chip program to be downloaded. DPFR (Return value: 1 byte) System use area (15 bytes) Area to be downloaded (size: 4 kbytes) Unusable area during programming/erasing Programming/erasing program entry Initialization program entry Initialization + programming program or Initialization + erasing program RAM emulation area or area that can be used by user Area that can be used by user FTDAR setting + 4 kbytes FTDAR setting + 16 bytes FTDAR setting FTDAR setting + 32 bytes H'FFBFFF Figure 17.10 RAM Map when Programming/Erasing is Executed Rev. 2.00 Mar. 15, 2006 Page 581 of 754 REJ09B0199-0200 Section 17 Flash Memory (0.18-m F-ZTAT Version) (2) Programming Procedure in User Program Mode The procedures for download of the on-chip program, initialization, and programming are shown in figure 17.11. Start programming procedure program Select on-chip program to be downloaded and specify download destination by FTDAR Set FKEY to H'A5 1 1. Disable interrupts and bus master operation other than CPU Set FKEY to H'5A 9. 2. 10. Set SCO to 1 after initializing VBR and execute download Download 3. Set parameters to ER1 and ER0 (FMPAR and FMPDR) Programming 11. Clear FKEY to 0 4. Programming JSR FTDAR setting + 16 FPFR = 0? Yes 12. 13. No Clear FKEY and programming error processing 14. DPFR = 0? Yes Set the FPEFEQ parameter Initialization 5. No Download error processing 6. 7. No Initialization JSR FTDAR setting + 32 Required data programming is completed? Yes FPFR = 0? Yes 8. No Initialization error processing Clear FKEY to 0 15. End programming procedure program 1 Figure 17.11 Programming Procedure in User Program Mode Rev. 2.00 Mar. 15, 2006 Page 582 of 754 REJ09B0199-0200 Section 17 Flash Memory (0.18-m F-ZTAT Version) The procedure program must be executed in an area other than the flash memory to be programmed. Setting the SCO bit in FCCS to 1 to request download must be executed in the onchip RAM. The area that can be executed in the steps of the procedure program (on-chip RAM and user MAT) is shown in section 17.8.4, On-Chip Program and Storable Area for Program Data. The following description assumes that the area to be programmed on the user MAT is erased and that program data is prepared in the consecutive area. The program data for one programming operation is always 128 bytes. When the program data exceeds 128 bytes, the start address of the programming destination and program data parameters are updated in 128-byte units and programming is repeated. When the program data is less than 128 bytes, invalid data is filled to prepare 128-byte program data. If the invalid data to be added is H'FF, the program processing time can be shortened. 1. Select the on-chip program to be downloaded and the download destination. When the PPVS bit in FPCS is set to 1, the programming program is selected. Several programming/erasing programs cannot be selected at one time. If several programs are selected, a download error is returned to the SS bit in the DPFR parameter. The on-chip RAM start address of the download destination is specified by FTDAR. 2. Write H'A5 in FKEY. If H'A5 is not written to FKEY, the SCO bit in FCCS cannot be set to 1 to request download of the on-chip program. 3. After initializing VBR to H'00000000, set the SCO bit to 1 to execute download. To set the SCO bit to 1, all of the following conditions must be satisfied. RAM emulation mode has been canceled. H'A5 is written to FKEY. Setting the SCO bit is executed in the on-chip RAM. When the SCO bit is set to 1, download is started automatically. Since the SCO bit is cleared to 0 when the procedure program is resumed, the SCO bit cannot be confirmed to be 1 in the procedure program. The download result can be confirmed by the return value of the DPFR parameter. To prevent incorrect decision, before setting the SCO bit to 1, set one byte of the on-chip RAM start address specified by FTDAR, which becomes the DPFR parameter, to a value other than the return value (e.g. H'FF). Since particular processing that is accompanied by bank switching as described below is performed when download is executed, initialize the VBR contents to H'00000000. Dummy read of FCCS must be performed twice immediately after the SCO bit is set to 1. The user-MAT space is switched to the on-chip program storage area. After the program to be downloaded and the on-chip RAM start address specified by FTDAR are checked, they are transferred to the on-chip RAM. FPCS, FECS, and the SCO bit in FCCS are cleared to 0. The return value is set in the DPFR parameter. Rev. 2.00 Mar. 15, 2006 Page 583 of 754 REJ09B0199-0200 Section 17 Flash Memory (0.18-m F-ZTAT Version) 4. 5. 6. 7. After the on-chip program storage area is returned to the user-MAT space, the procedure program is resumed. After that, VBR can be set again. The values of general registers of the CPU are held. During download, no interrupts can be accepted. However, since the interrupt requests are held, when the procedure program is resumed, the interrupts are requested. To hold a level-detection interrupt request, the interrupt must continue to be input until the download is completed. Allocate a stack area of 128 bytes at the maximum in the on-chip RAM before setting the SCO bit to 1. If access to the flash memory is requested by the DTC or DMAC during download, the operation cannot be guaranteed. Make sure that an access request by the DTC or DMAC is not generated. FKEY is cleared to H'00 for protection. The download result must be confirmed by the value of the DPFR parameter. Check the value of the DPFR parameter (one byte of start address of the download destination specified by FTDAR). If the value of the DPFR parameter is H'00, download has been performed normally. If the value is not H'00, the source that caused download to fail can be investigated by the description below. If the value of the DPFR parameter is the same as that before downloading, the setting of the start address of the download destination in FTDAR may be abnormal. In this case, confirm the setting of the TDER bit in FTDAR. If the value of the DPFR parameter is different from that before downloading, check the SS bit or FK bit in the DPFR parameter to confirm the download program selection and FKEY setting, respectively. The operating frequency of the CPU is set in the FPEFEQ parameter for initialization. The settable operating frequency of the FPEFEQ parameter ranges from 8 to 48 MHz. When the frequency is set otherwise, an error is returned to the FPFR parameter of the initialization program and initialization is not performed. For details on setting the frequency, see section 17.7.2 (3), Flash Program/Erase Frequency Parameter (FPEFEQ). Initialization is executed. The initialization program is downloaded together with the programming program to the on-chip RAM. The entry point of the initialization program is at the address which is 32 bytes after #DLTOP (start address of the download destination specified by FTDAR). Call the subroutine to execute initialization by using the following steps. Rev. 2.00 Mar. 15, 2006 Page 584 of 754 REJ09B0199-0200 Section 17 Flash Memory (0.18-m F-ZTAT Version) MOV.L #DLTOP+32,ER2 JSR NOP @ER2 ; Set entry address to ER2 ; Call initialization routine The general registers other than ER0 and ER1 are held in the initialization program. R0L is a return value of the FPFR parameter. Since the stack area is used in the initialization program, a stack area of 128 bytes at the maximum must be allocated in RAM. Interrupts can be accepted during execution of the initialization program. Make sure the program storage area and stack area in the on-chip RAM and register values are not overwritten. 8. The return value in the initialization program, the FPFR parameter is determined. 9 All interrupts and the use of a bus master other than the CPU are disabled during programming/erasing. The specified voltage is applied for the specified time when programming or erasing. If interrupts occur or the bus mastership is moved to other than the CPU during programming/erasing, causing a voltage exceeding the specifications to be applied, the flash memory may be damaged. Therefore, interrupts are disabled by setting bit 7 (I bit) in the condition code register (CCR) to B'1 in interrupt control mode 0 and by setting bits 2 to 0 (I2 to I0 bits) in the extend register (EXR) to B'111 in interrupt control mode 2. Accordingly, interrupts other than NMI are held and not executed. Configure the user system so that NMI interrupts do not occur. The interrupts that are held must be executed after all programming completes. When the bus mastership is moved to other than the CPU, such as to the DTC or DMAC, the error protection state is entered. Therefore, make sure the DTC and DMAC do not acquire the bus. 10. FKEY must be set to H'5A and the user MAT must be prepared for programming. 11. The parameters required for programming are set. The start address of the programming destination on the user MAT (FMPAR parameter) is set in general register ER1. The start address of the program data storage area (FMPDR parameter) is set in general register ER0. Example of FMPAR parameter setting: When an address other than one in the user MAT area is specified for the start address of the programming destination, even if the programming program is executed, programming is not executed and an error is returned to the FPFR parameter. Since the program data for one programming operation is 128 bytes, the lower eight bits of the address must be H'00 or H'80 to be aligned with the 128-byte boundary. Example of FMPDR parameter setting: When the storage destination for the program data is flash memory, even if the programming routine is executed, programming is not executed and an error is returned to the FPFR parameter. In this case, the program data must be transferred to the on-chip RAM and then programming must be executed. Rev. 2.00 Mar. 15, 2006 Page 585 of 754 REJ09B0199-0200 Section 17 Flash Memory (0.18-m F-ZTAT Version) 12. Programming is executed. The entry point of the programming program is at the address which is 16 bytes after #DLTOP (when start address of the download destination specified by FTDAR is #DLTOP). Call the subroutine to execute programming by using the following steps. MOV.L JSR NOP #DLTOP+16,ER2 @ER2 ; Set entry address to ER2 ; Call programming routine The general registers other than ER0 and ER1 are held in the programming program. R0L is a return value of the FPFR parameter. Since the stack area is used in the programming program, a stack area of 128 bytes at the maximum must be allocated in RAM. 13. The return value in the programming program, the FPFR parameter is determined. 14. Determine whether programming of the necessary data has finished. If more than 128 bytes of data are to be programmed, update the FMPAR and FMPDR parameters in 128-byte units, and repeat steps 11 to 14. Increment the programming destination address by 128 bytes and update the programming data pointer correctly. If an address which has already been programmed is written to again, not only will a programming error occur, but also flash memory will be damaged. 15. After programming finishes, clear FKEY and specify software protection. If this LSI is restarted by a reset immediately after programming has finished, secure the reset input period (period of RES = 0) of at least 100 s. Rev. 2.00 Mar. 15, 2006 Page 586 of 754 REJ09B0199-0200 Section 17 Flash Memory (0.18-m F-ZTAT Version) (3) Erasing Procedure in User Program Mode The procedures for download of the on-chip program, initialization, and erasing are shown in figure 17.12. Start erasing procedure program Select on-chip program to be downloaded and specify download destination by FTDAR 1 1. Disable interrupts and bus master operation other than CPU Set FKEY to H'5A Set FKEY to H'A5 Download Set SCO to 1 after initializing VBR and execute download Set FEBS parameter Erasing JSR FTDAR setting + 16 FPFR = 0? Yes 2. Clear FKEY to 0 Erasing 3. 4. No DPFR = 0? Yes Set the FPEFEQ parameter Initialization JSR FTDAR setting + 32 FPFR = 0 ? Yes 1 No Download error processing No Clear FKEY and erasing error processing Required block erasing is completed? Yes Clear FKEY to 0 5. Initialization 6. No Initialization error processing End erasing procedure program Figure 17.12 Erasing Procedure in User Program Mode Rev. 2.00 Mar. 15, 2006 Page 587 of 754 REJ09B0199-0200 Section 17 Flash Memory (0.18-m F-ZTAT Version) The procedure program must be executed in an area other than the user MAT to be erased. Setting the SCO bit in FCCS to 1 to request download must be executed in the on-chip RAM. The area that can be executed in the steps of the procedure program (on-chip RAM and user MAT) is shown in section 17.8.4, On-Chip Program and Storable Area for Program Data. For the downloaded on-chip program area, see figure 17.10. One erasure processing erases one block. For details on block divisions, refer to figure 17.4. To erase two or more blocks, update the erase block number and repeat the erasing processing for each block. 1. Select the on-chip program to be downloaded and the download destination. When the PPVS bit in FPCS is set to 1, the programming program is selected. Several programming/erasing programs cannot be selected at one time. If several programs are selected, a download error is returned to the SS bit in the DPFR parameter. The on-chip RAM start address of the download destination is specified by FTDAR. For the procedures to be carried out after setting FKEY, see section 17.8.2 (2), Programming Procedure in User Program Mode. 2. Set the FEBS parameter necessary for erasure. Set the erase block number (FEBS parameter) of the user MAT in general register ER0. If a value other than an erase block number of the user MAT is set, no block is erased even though the erasing program is executed, and an error is returned to the FPFR parameter. 3. Erasure is executed. Similar to as in programming, the entry point of the erasing program is at the address which is 16 bytes after #DLTOP (when the start address of the download destination specified by FTDAR is #DLTOP). Call the subroutine to execute erasure by using the following steps. MOV.L #DLTOP+16, ER2 JSR NOP @ER2 ; Set entry address to ER2 ; Call erasing routine The general registers other than ER0 and ER1 are held in the erasing program. R0L is a return value of the FPFR parameter. Since the stack area is used in the erasing program, a stack area of 128 bytes at the maximum must be allocated in RAM. 4. The return value in the erasing program, the FPFR parameter is determined. 5. Determine whether erasure of the necessary blocks has finished. If more than one block is to be erased, update the FEBS parameter and repeat steps 2 to 5. 6. After erasure completes, clear FKEY and specify software protection. If this LSI is restarted by a power-on reset immediately after erasure has finished, secure the reset input period (period of RES = 0) of at least 100 s. Rev. 2.00 Mar. 15, 2006 Page 588 of 754 REJ09B0199-0200 * * * Section 17 Flash Memory (0.18-m F-ZTAT Version) (4) Procedure of Erasing, Programming, and RAM Emulation in User Program Mode By changing the on-chip RAM start address of the download destination in FTDAR, the erasing program and programming program can be downloaded to separate on-chip RAM areas. Figure 17.13 shows a repeating procedure of erasing, programming, and RAM emulation. 1 Start procedure program Make a transition to RAM emulation mode and tuning parameters in on-chip RAM Erasing program Set FTDAR to H'00 (specify download destination to H'FF9000) Download erasing program Emulation/Erasing/Programming download Exit emulation mode Initialize erasing program Erase relevant block (execute erasing program) Programming program download Set FTDAR to H'02 (specify download destination H'FFB000) Set FMPDR to H'FFA000 and program relevant block (execute programming program) Download programming program Confirm operation Initialize programming program End ? Yes No 1 End procedure program Figure 17.13 Repeating Procedure of Erasing, Programming, and RAM Emulation in User Program Mode Rev. 2.00 Mar. 15, 2006 Page 589 of 754 REJ09B0199-0200 Section 17 Flash Memory (0.18-m F-ZTAT Version) In figure 17.13, since RAM emulation is performed, the erasing/programming program is downloaded to avoid the 4-kbyte on-chip RAM area (H'FFA000 to H'FFAFFF). Download and initialization are performed only once at the beginning. Note the following when executing the procedure program. * Be careful not to overwrite data in the on-chip RAM with overlay settings. In addition to the programming program area, erasing program area, and RAM emulation area, areas for the procedure programs, work area, and stack area are reserved in the on-chip RAM. Do not make settings that will overwrite data in these areas. * Be sure to initialize both the programming program and erasing program. When the FPEFEQ parameter is initialized, also initialize both the erasing program and programming program. Initialization must be executed for both entry addresses: 32 bytes after #DLTOP (start address of download destination for erasing program is), and 32 bytes after #DLTOP (start address of download destination for programming program). 17.8.3 User Boot Mode Branching to a programming/erasing program prepared by the user enables user boot mode which is a user-arbitrary boot mode to be used. Only the user MAT can be programmed/erased in user boot mode. Programming/erasing of the user boot MAT is only enabled in boot mode or programmer mode. (1) Initiation in User Boot Mode When the reset start is executed with the mode pins set to user boot mode, the built-in check routine runs and checks the user MAT and user boot MAT states. While the check routine is running, NMI and all other interrupts cannot be accepted. Next, processing starts from the execution start address of the reset vector in the user boot MAT. At this point, the user boot MAT is selected (FMATS = H'AA) as the execution memory MAT. Rev. 2.00 Mar. 15, 2006 Page 590 of 754 REJ09B0199-0200 Section 17 Flash Memory (0.18-m F-ZTAT Version) (2) User MAT Programming in User Boot Mode Figure 17.14 shows the procedure for programming the user MAT in user boot mode. The difference between the programming procedures in user program mode and user boot mode is the memory MAT switching as shown in figure 17.14. For programming the user MAT in user boot mode, additional processing made by setting FMATS is required: switching from the user boot MAT to the user MAT, and switching back to the user boot MAT after programming completes. Start programming procedure program Select on-chip program to be downloaded and specify download destination by FTDAR Set FKEY to H'A5 Set SCO to 1 after initializing VBR and execute download Download 1 Set FMATS to value other than H'AA to select user MAT MAT switchover Set FKEY to H'5A Clear FKEY to 0 Set parameter to ER0 and ER1 (FMPAR and FMPDR) Programming JSR FTDAR setting + 16 User-MAT selection state User-boot-MAT selection state No Download error processing Yes Set the FPEFEQ parameter Initialization JSR FTDAR setting + 32 FPFR = 0 ? Yes Programming DPFR = 0 ? FPFR = 0 ? Yes No Required data programming is completed? Yes No Clear FKEY and programming error processing Initialization No Initialization error processing Clear FKEY to 0 Disable interrupts and bus master operation other than CPU Set FMATS to H'AA to select user boot MAT MAT switchover End programming procedure program User-boot-MAT selection state Note: The MAT must be switched by FMATS to perform the programming error processing in the user boot MAT. 1 Figure 17.14 Procedure for Programming User MAT in User Boot Mode Rev. 2.00 Mar. 15, 2006 Page 591 of 754 REJ09B0199-0200 Section 17 Flash Memory (0.18-m F-ZTAT Version) In user boot mode, though the user boot MAT can be seen in the flash memory space, the user MAT is hidden in the background. Therefore, the user MAT and user boot MAT are switched while the user MAT is being programmed. Because the user boot MAT is hidden while the user MAT is being programmed, the procedure program must be executed in an area other than flash memory. After programming completes, switch the memory MATs again to return to the first state. Memory MAT switching is enabled by setting FMATS. However note that access to a memory MAT is not allowed until memory MAT switching is completed. During memory MAT switching, the LSI is in an unstable state, e.g. if an interrupt occurs, from which memory MAT the interrupt vector is read is undetermined. Perform memory MAT switching in accordance with the description in section 17.11, Switching between User MAT and User Boot MAT. Except for memory MAT switching, the programming procedure is the same as that in user program mode. The area that can be executed in the steps of the procedure program (on-chip RAM, user MAT, and external space) is shown in section 17.8.4, On-Chip Program and Storable Area for Program Data. (3) User MAT Erasing in User Boot Mode Figure 17.15 shows the procedure for erasing the user MAT in user boot mode. The difference between the erasing procedures in user program mode and user boot mode is the memory MAT switching as shown in figure 17.15. For erasing the user MAT in user boot mode, additional processing made by setting FMATS is required: switching from the user boot MAT to the user MAT, and switching back to the user boot MAT after erasing completes. Rev. 2.00 Mar. 15, 2006 Page 592 of 754 REJ09B0199-0200 Section 17 Flash Memory (0.18-m F-ZTAT Version) Start erasing procedure program Select on-chip program to be downloaded and specify download destination by FTDAR Set FKEY to H'A5 Set FKEY to H'5A 1 Set FMATS to value other than H'AA to select user MAT MAT switchover Set SCO to 1 after initializing VBR and execute download Download Clear FKEY to 0 Set FEBS parameter Programming JSR FTDAR setting + 16 User-boot-MAT selection state Yes Set the FPEFEQ parameter Erasing No Download error processing User-MAT selection state DPFR = 0 ? FPFR = 0 ? Yes No Required block erasing is completed? Yes No Clear FKEY and erasing error processing Initialization Initialization JSR FTDAR setting + 32 FPFR = 0 ? No Yes Initialization error processing Clear FKEY to 0 Disable interrupts and bus master operation other than CPU User-boot-MAT Set FMATS to H'AA to select user boot MAT MAT switchover End erasing procedure program selection state Note: The MAT must be switched by FMATS to perform the erasing error processing in the user boot MAT. 1 Figure 17.15 Procedure for Erasing User MAT in User Boot Mode Memory MAT switching is enabled by setting FMATS. However note that access to a memory MAT is not allowed until memory MAT switching is completed. During memory MAT switching, the LSI is in an unstable state, e.g. if an interrupt occurs, from which memory MAT the interrupt vector is read is undetermined. Perform memory MAT switching in accordance with the description in section 17.11, Switching between User MAT and User Boot MAT. Except for memory MAT switching, the erasing procedure is the same as that in user program mode. The area that can be executed in the steps of the procedure program (on-chip RAM, user MAT, and external space) is shown in section 17.8.4, On-Chip Program and Storable Area for Program Data. Rev. 2.00 Mar. 15, 2006 Page 593 of 754 REJ09B0199-0200 Section 17 Flash Memory (0.18-m F-ZTAT Version) 17.8.4 On-Chip Program and Storable Area for Program Data In the descriptions in this manual, the on-chip programs and program data storage areas are assumed to be in the on-chip RAM. However, they can be executed from part of the flash memory which is not to be programmed or erased as long as the following conditions are satisfied. * The on-chip program is downloaded to and executed in the on-chip RAM specified by FTDAR. Therefore, this on-chip RAM area is not available for use. * Since the on-chip program uses a stack area, allocate 128 bytes at the maximum as a stack area. * Download requested by setting the SCO bit in FCCS to 1 should be executed from the on-chip RAM because it will require switching of the memory MATs. * In an operating mode in which the external address space is not accessible, such as single-chip mode, the required procedure programs, NMI handling vector table, and NMI handling routine should be transferred to the on-chip RAM before programming/erasing starts (download result is determined). * The flash memory is not accessible during programming/erasing. Programming/erasing is executed by the program downloaded to the on-chip RAM. Therefore, the procedure program that initiates operation, the NMI handling vector table, and the NMI handling routine should be stored in the on-chip RAM other than the flash memory. * After programming/erasing starts, access to the flash memory should be inhibited until FKEY is cleared. The reset input state (period of RES = 0) must be set to at least 100 s when the operating mode is changed and the reset start executed on completion of programming/erasing. Transitions to the reset state are inhibited during programming/erasing. When the reset signal is input, a reset input state (period of RES = 0) of at least 100 s is needed before the reset signal is released. * Switching of the memory MATs by FMATS should be needed when programming/erasing of the user MAT is operated in user boot mode. The program which switches the memory MATs should be executed from the on-chip RAM. For details, see section 17.11, Switching between User MAT and User Boot MAT. Make sure you know which memory MAT is currently selected when switching them. * When the program data storage area is within the flash memory area, an error will occur even when the data stored is normal program data. Therefore, the data should be transferred to the on-chip RAM to place the address that the FMPDR parameter indicates in an area other than the flash memory. Rev. 2.00 Mar. 15, 2006 Page 594 of 754 REJ09B0199-0200 Section 17 Flash Memory (0.18-m F-ZTAT Version) In consideration of these conditions, the areas in which the program data can be stored and executed are determined by the combination of the processing contents, operating mode, and bank structure of the memory MATs, as shown in tables 17.7 to 17.11. Table 17.7 Executable Memory MAT Operating Mode Processing Contents Programming Erasing Note: * User Program Mode See table 17.8 See table 17.9 Programming/Erasing is possible to the user MAT. User Boot Mode* See table 17.10 See table 17.11 Rev. 2.00 Mar. 15, 2006 Page 595 of 754 REJ09B0199-0200 Section 17 Flash Memory (0.18-m F-ZTAT Version) Table 17.8 Usable Area for Programming in User Program Mode Storable/Executable Area Selected MAT Embedded Program User MAT Storage MAT O O O O O O O O O O O O O O O O O O Item Storage area for program data Operation for selecting on-chip program to be downloaded Operation for writing H'A5 to FKEY Execution of writing 1 to SCO bit in FCCS (download) Operation for clearing FKEY Decision of download result Operation for download error Operation for setting initialization parameter Execution of initialization Decision of initialization result Operation for initialization error NMI handling routine Operation for disabling interrupts Operation for writing H'5A to FKEY Operation for setting programming parameter Execution of programming Decision of programming result Operation for programming error Operation for clearing FKEY Note: * On-Chip RAM O O O O O O O O O O O O O O O O O O O User MAT x* O O x O O O O x O O x O O x x x x x Transferring the program data to the on-chip RAM beforehand enables this area to be used. Rev. 2.00 Mar. 15, 2006 Page 596 of 754 REJ09B0199-0200 Section 17 Flash Memory (0.18-m F-ZTAT Version) Table 17.9 Usable Area for Erasure in User Program Mode Storable/Executable Area Selected MAT Embedded Program User MAT Storage MAT O O O O O O O O O O O O O O O O O O Item Operation for selecting on-chip program to be downloaded Operation for writing H'A5 to FKEY Execution of writing 1 to SCO bit in FCCS (download) Operation for clearing FKEY Decision of download result Operation for download error Operation for setting initialization parameter Execution of initialization Decision of initialization result Operation for initialization error NMI handling routine Operation for disabling interrupts Operation for writing H'5A to FKEY Operation for setting erasure parameter Execution of erasure Decision of erasure result Operation for erasure error Operation for clearing FKEY On-Chip RAM O O O O O O O O O O O O O O O O O O User MAT O O x O O O O x O O x O O x x x x x Rev. 2.00 Mar. 15, 2006 Page 597 of 754 REJ09B0199-0200 Section 17 Flash Memory (0.18-m F-ZTAT Version) Table 17.10 Usable Area for Programming in User Boot Mode Storable/Executable Area On-Chip RAM O O O O O O O O O O O O O O O O O O O O O User Boot User MAT MAT x*1 O O x O O O O x O O x O x x x x x x* x x 2 Selected MAT User Boot MAT O O O O O O O O O O O O O O O O O O O O Embedded Program Storage MAT Item Storage area for program data Operation for selecting on-chip program to be downloaded Operation for writing H'A5 to FKEY Execution of writing 1 to SCO bit in FCCS (download) Operation for clearing FKEY Decision of download result Operation for download error Operation for setting initialization parameter Execution of initialization Decision of initialization result Operation for initialization error NMI handling routine Operation for disabling interrupts Switching memory MATs by FMATS Operation for writing H'5A to FKEY Operation for setting programming parameter Execution of programming Decision of programming result Operation for programming error Operation for clearing FKEY Switching memory MATs by FMATS Notes: 1. Transferring the program data to the on-chip RAM beforehand enables this area to be used. 2. Switching memory MATs by FMATS by a program in the on-chip RAM enables this area to be used. Rev. 2.00 Mar. 15, 2006 Page 598 of 754 REJ09B0199-0200 Section 17 Flash Memory (0.18-m F-ZTAT Version) Table 17.11 Usable Area for Erasure in User Boot Mode Storable/Executable Area On-Chip RAM O O O O O O O O O O O O O O O O O O O O User Boot User MAT MAT O O x O O O O x O O x O x x x x x x* x x O O O O O O O O O O O O O O O O O Selected MAT User Boot MAT O O O Embedded Program Storage MAT Item Operation for selecting on-chip program to be downloaded Operation for writing H'A5 to FKEY Execution of writing 1 to SCO bit in FCCS (download) Operation for clearing FKEY Decision of download result Operation for download error Operation for setting initialization parameter Execution of initialization Decision of initialization result Operation for initialization error NMI handling routine Operation for disabling interrupts Switching memory MATs by FMATS Operation for writing H'5A to FKEY Operation for setting erasure parameter Execution of erasure Decision of erasure result Operation for erasure error Operation for clearing FKEY Switching memory MATs by FMATS Note: Switching memory MATs by FMATS by a program in the on-chip RAM enables this area to be used. Rev. 2.00 Mar. 15, 2006 Page 599 of 754 REJ09B0199-0200 Section 17 Flash Memory (0.18-m F-ZTAT Version) 17.9 Protection There are three types of protection against the flash memory programming/erasing: hardware protection, software protection, and error protection. 17.9.1 Hardware Protection Programming and erasure of the flash memory is forcibly disabled or suspended by hardware protection. In this state, download of an on-chip program and initialization are possible. However, programming or erasure of the user MAT cannot be performed even if the programming/erasing program is initiated, and the error in programming/erasing is indicated by the FPFR parameter. Table 17.12 Hardware Protection Function to be Protected Item Reset protection Description * The programming/erasing interface registers are initialized in the reset state (including a reset by the WDT) and the programming/erasing protection state is entered. The reset state will not be entered by a reset using the RES pin unless the RES pin is held low until oscillation has settled after a power is initially supplied. In the case of a reset during operation, hold the RES pin low for the RES pulse width given in the AC characteristics. If a reset is input during programming or erasure, data in the flash memory is not guaranteed. In this case, execute erasure and then execute programming again. Download O Programming/ Erasing O * Rev. 2.00 Mar. 15, 2006 Page 600 of 754 REJ09B0199-0200 Section 17 Flash Memory (0.18-m F-ZTAT Version) 17.9.2 Software Protection The software protection protects the flash memory against programming/erasing by disabling download of the programming/erasing program, using the key code, and by the RAMER setting. Table 17.13 Software Protection Function to be Protected Item Description Download Programming/ Erasing O Protection The programming/erasing protection state is O by SCO bit entered when the SCO bit in FCCS is cleared to 0 to disable download of the programming/erasing programs. Protection by FKEY The programming/erasing protection state is entered because download and programming/erasing are disabled unless the required key code is written in FKEY. O O Emulation protection The programming/erasing protection state is O entered when the RAMS bit in the RAM emulation register (RAMER) is set to 1. O 17.9.3 Error Protection Error protection is a mechanism for aborting programming or erasure when a CPU runaway occurs or operations not according to the programming/erasing procedures are detected during programming/erasing of the flash memory. Aborting programming or erasure in such cases prevents damage to the flash memory due to excessive programming or erasing. If an error occurs during programming/erasing of the flash memory, the FLER bit in FCCS is set to 1 and the error protection state is entered. * When an interrupt request, such as NMI, occurs during programming/erasing. * When the flash memory is read from during programming/erasing (including a vector read or an instruction fetch). * When a SLEEP instruction is executed (including software-standby mode) during programming/erasing. * When a bus master other than the CPU, such as the DTC or DMAC, obtains bus mastership during programming/erasing. Rev. 2.00 Mar. 15, 2006 Page 601 of 754 REJ09B0199-0200 Section 17 Flash Memory (0.18-m F-ZTAT Version) Error protection is canceled by a reset. Note that the reset should be released after the reset input period of at least 100 s has passed. Since high voltages are applied during programming/erasing of the flash memory, some voltage may remain after the error protection state has been entered. For this reason, it is necessary to reduce the risk of damaging the flash memory by extending the reset input period so that the charge is released. The state-transition diagram in figure 17.16 shows transitions to and from the error protection state. Programming/erasing mode Read disabled Programming/erasing enabled FLER = 0 RES = 0 Reset (hardware protection) Read disabled Programming/erasing disabled FLER = 0 Programming/erasing interface register is in its initial state. Er (S ror oc oft cu wa rre d by S RE =0 re Error occurrence sta nd RES = 0 ) Error-protection mode Read enabled Programming/erasing disabled FLER = 1 Software standby mode Error-protection mode (software standby) Read disabled Programming/erasing disabled FLER = 1 Programming/erasing interface register is in its initial state. Cancel software standby mode Figure 17.16 Transitions to Error Protection State Rev. 2.00 Mar. 15, 2006 Page 602 of 754 REJ09B0199-0200 Section 17 Flash Memory (0.18-m F-ZTAT Version) 17.10 Flash Memory Emulation Using RAM For realtime emulation of the data written to the flash memory using the on-chip RAM, the onchip RAM area can be overlaid with several flash memory blocks (user MAT) using the RAM emulation register (RAMER). The overlaid area can be accessed from both the user MAT area specified by RAMER and the overlaid RAM area. The emulation can be performed in user mode and user program mode. Figure 17.17 shows an example of emulating realtime programming of the user MAT. Emulation program start Set RAMER Write tuning data to overlaid RAM area Execute application program No Tuning OK? Yes Cancel setting in RAMER Program emulation block in user MAT Emulation program end Figure 17.17 RAM Emulation Flow Rev. 2.00 Mar. 15, 2006 Page 603 of 754 REJ09B0199-0200 Section 17 Flash Memory (0.18-m F-ZTAT Version) Figure 17.18 shows an example of overlaying flash memory block area EB0. This area can be accessed via both the on-chip RAM and flash memory area. H'00000 H'01000 H'02000 H'03000 H'04000 H'05000 H'06000 H'07000 H'08000 Flash memory user MAT EB8 to EB11 H'3FFFF H'FFBFFF EB0 EB1 EB2 EB3 EB4 EB5 EB6 EB7 H'FF9000 H'FFA000 H'FFAFFF On-chip RAM Figure 17.18 Address Map of Overlaid RAM Area The flash memory area that can be emulated is the one area selected by bits RAM2 to RAM0 in RAMER from among the eight blocks, EB0 to EB7, of the user MAT. To overlay a part of the on-chip RAM with block EB0 for realtime emulation, set the RAMS bit in RAMER to 1 and bits RAM2 to RAM0 to B'000. For programming/erasing the user MAT, the procedure programs including a download program of the on-chip program must be executed. At this time, the download area should be specified so that the overlaid RAM area is not overwritten by downloading the on-chip program. Since the area in which the tuned data is stored is overlaid with the download area when FTDAR = H'01, the tuned data must be saved in an unused area beforehand. Figure 17.19 shows an example of the procedure to program the tuned data in block EB0 of the user MAT. Rev. 2.00 Mar. 15, 2006 Page 604 of 754 REJ09B0199-0200 Section 17 Flash Memory (0.18-m F-ZTAT Version) (1) Exit RAM emulation mode. (2) Transfer user-created programming/erasing procedure program. H'00000 H'01000 H'02000 H'03000 H'04000 H'05000 H'06000 H'07000 H'08000 Flash memory user MAT EB8 to EB11 H'3FFFF Download area Tuned data area Area for programming/ erasing program etc. EB0 EB1 EB2 EB3 EB4 EB5 EB6 EB7 (3) Download the on-chip programming/erasing program to the area specified by FTDAR. FTDAR setting should avoid the tuned data area. (4) Program after erasing, if necessary. Specified by FTDAR H'FFA000 H'FFAFFF H'FFB000 H'FFBFFF Figure 17.19 Programming Tuned Data 1. After tuning program data is completed, clear the RAMS bit in RAMER to 0 to cancel the overlaid RAM. 2. Transfer the user-created procedure program to the on-chip RAM. 3. Start the procedure program and download the on-chip program to the on-chip RAM. The start address of the download destination should be specified by FTDAR so that the tuned data area does not overlay the download area. 4. When block EB0 of the user MAT has not been erased, the programming program must be downloaded after block EB0 is erased. Specify the tuned data saved in the FMPAR and FMPDR parameters and then execute programming. Note: Setting the RAMS bit to 1 makes all the blocks of the user MAT enter the programming/erasing protection state (emulation protection state) regardless of the setting of the RAM2 to RAM0 bits. Under this condition, the on-chip program cannot be downloaded. When data is to be actually programmed and erased, clear the RAMS bit to 0. Rev. 2.00 Mar. 15, 2006 Page 605 of 754 REJ09B0199-0200 Section 17 Flash Memory (0.18-m F-ZTAT Version) 17.11 Switching between User MAT and User Boot MAT It is possible to switch between the user MAT and user boot MAT. However, the following procedure is required because the start addresses of these MATs are allocated to the same address. Switching to the user boot MAT disables programming and erasing. Programming of the user boot MAT should take place in boot mode or programmer mode. 1. Memory MAT switching by FMATS should always be executed from the on-chip RAM. 2. When accessing the memory MAT immediately after switching the memory MATs by FMATS from the on-chip RAM, similarly execute the NOP instruction in the on-chip RAM for eight times (this prevents access to the flash memory during memory MAT switching). 3. If an interrupt request has occurred during memory MAT switching, there is no guarantee of which memory MAT is accessed. Always mask the maskable interrupts before switching memory MATs. In addition, configure the system so that NMI interrupts do not occur during memory MAT switching. 4. After the memory MATs have been switched, take care because the interrupt vector table will also have been switched. If interrupt processing is to be the same before and after memory MAT switching, transfer the interrupt processing routines to the on-chip RAM and specify VBR to place the interrupt vector table in the on-chip RAM. 5. Memory sizes of the user MAT and user boot MAT are different. When accessing the user boot MAT, do not access addresses which exceed the 10-kbyte memory space. If an access is equal to or greater than 10 kbytes, the read values are undefined. Figure 17.20 Switching between User MAT and User Boot MAT Rev. 2.00 Mar. 15, 2006 Page 606 of 754 REJ09B0199-0200 Section 17 Flash Memory (0.18-m F-ZTAT Version) 17.12 Programmer Mode Along with its on-board programming mode, this LSI also has a programmer mode as a further mode for the writing and erasing of programs and data. In programmer mode, a general-purpose PROM programmer that supports the device types shown in table 17.14 can be used to write programs to the on-chip ROM without any limitation. Table 17.14 Device Types Supported in Programmer Mode Target Memory MAT User MAT User boot MAT Size 256 kbytes 10 kbytes Device Type FZTAT256V5A FZTATUSBTV5A 17.13 Standard Serial Communication Interface Specifications for Boot Mode The boot program initiated in boot mode performs serial communication using the host and onchip SCI_4. The serial communication interface specifications are shown below. The boot program has three states. 1. Bit-rate-adjustment state In this state, the boot program adjusts the bit rate to achieve serial communication with the host. Initiating boot mode enables starting of the boot program and entry to the bit-rateadjustment state. The program receives the command from the host to adjust the bit rate. After adjusting the bit rate, the program enters the inquiry/selection state. 2. Inquiry/selection state In this state, the boot program responds to inquiry commands from the host. The device name, clock mode, and bit rate are selected. After selection of these settings, the program is made to enter the programming/erasing state by the command for a transition to the programming/erasing state. The program transfers the libraries required for erasure to the onchip RAM and erases the user MATs and user boot MATs before the transition. 3. Programming/erasing state Programming and erasure by the boot program take place in this state. The boot program is made to transfer the programming/erasing programs to the on-chip RAM by commands from the host. Sum checks and blank checks are executed by sending these commands from the host. Rev. 2.00 Mar. 15, 2006 Page 607 of 754 REJ09B0199-0200 Section 17 Flash Memory (0.18-m F-ZTAT Version) These boot program states are shown in figure 17.21. Reset Bit-rate-adjustment state Inquiry/response wait Response Inquiry Operations for inquiry and selection Operations for response Transition to programming/erasing Operations for erasing user MATs and user boot MATs Programming/erasing wait Programming Operations for programming Erasing Operations for erasing Operations for checking Checking Figure 17.21 Boot Program States Rev. 2.00 Mar. 15, 2006 Page 608 of 754 REJ09B0199-0200 Section 17 Flash Memory (0.18-m F-ZTAT Version) (1) Bit-Rate-Adjustment State The bit rate is calculated by measuring the period of transfer of a low-level byte (H'00) from the host. The bit rate can be changed by the command for a new bit rate selection. After the bit rate has been adjusted, the boot program enters the inquiry and selection state. The bit-rate-adjustment sequence is shown in figure 17.22. Host Boot program H'00 (30 times maximum) Measuring the 1-bit length H'00 (completion of adjustment) H'55 H'E6 (boot response) (H'FF (error)) Figure 17.22 Bit-Rate-Adjustment Sequence (2) Communications Protocol After adjustment of the bit rate, the protocol for serial communications between the host and the boot program is as shown below. 1. One-byte commands and one-byte responses These one-byte commands and one-byte responses consist of the inquiries and the ACK for successful completion. 2. n-byte commands or n-byte responses These commands and responses are comprised of n bytes of data. These are selections and responses to inquiries. The program data size is not included under this heading because it is determined in another command. 3. Error response The error response is a response to inquiries. It consists of an error response and an error code and comes two bytes. 4. Programming of 128 bytes The size is not specified in commands. The size of n is indicated in response to the programming unit inquiry. Rev. 2.00 Mar. 15, 2006 Page 609 of 754 REJ09B0199-0200 Section 17 Flash Memory (0.18-m F-ZTAT Version) 5. Memory read response This response consists of four bytes of data. One-byte command or one-byte response n-byte Command or n-byte response Command or response Data Size Command or response Checksum Error response Error code Error response 128-byte programming Address Command Data (n bytes) Checksum Memory read response Size Response Data Checksum Figure 17.23 Communication Protocol Format * Command (one byte): Commands including inquiries, selection, programming, erasing, and checking * Response (one byte): Response to an inquiry * Size (one byte): The amount of data for transmission excluding the command, amount of data, and checksum * Checksum (one byte): The checksum is calculated so that the total of all values from the command byte to the SUM byte becomes H'00. * Data (n bytes): Detailed data of a command or response * Error response (one byte): Error response to a command * Error code (one byte): Type of the error * Address (four bytes): Address for programming * Data (n bytes): Data to be programmed (the size is indicated in the response to the programming unit inquiry.) * Size (four bytes): Four-byte response to a memory read Rev. 2.00 Mar. 15, 2006 Page 610 of 754 REJ09B0199-0200 Section 17 Flash Memory (0.18-m F-ZTAT Version) (3) Inquiry and Selection States The boot program returns information from the flash memory in response to the host's inquiry commands and sets the device code, clock mode, and bit rate in response to the host's selection command. Table 17.15 lists the inquiry and selection commands. Table 17.15 Inquiry and Selection Commands Command H'20 H'10 H'21 H'11 H'22 Command Name Supported device inquiry Device selection Clock mode inquiry Clock mode selection Multiplication ratio inquiry Description Inquiry regarding device codes Selection of device code Inquiry regarding numbers of clock modes and values of each mode Indication of the selected clock mode Inquiry regarding the number of frequencymultiplied clock types, the number of multiplication ratios, and the values of each multiple Inquiry regarding the maximum and minimum values of the main clock and peripheral clocks Inquiry regarding the number of user boot MATs and the start and last addresses of each MAT Inquiry regarding the a number of user MATs and the start and last addresses of each MAT H'23 H'24 Operating clock frequency inquiry User boot MAT information inquiry H'25 H'26 H'27 H'3F H'40 H'4F User MAT information inquiry Block for erasing information Inquiry Inquiry regarding the number of blocks and the start and last addresses of each block Programming unit inquiry New bit rate selection Transition to programming/erasing state Boot program status inquiry Inquiry regarding the unit of program data Selection of new bit rate Erasing of user MAT and user boot MAT, and entry to programming/erasing state Inquiry into the operated status of the boot program Rev. 2.00 Mar. 15, 2006 Page 611 of 754 REJ09B0199-0200 Section 17 Flash Memory (0.18-m F-ZTAT Version) The selection commands, which are device selection (H'10), clock mode selection (H'11), and new bit rate selection (H'3F), should be sent from the host in that order. When two or more selection commands are sent at once, the last command will be valid. All of these commands, except for the boot program status inquiry command (H'4F), will be valid until the boot program receives the programming/erasing transition (H'40). The host can choose the needed commands and make inquiries while the above commands are being transmitted. H'4F is valid even after the boot program has received H'40. (a) Supported Device Inquiry The boot program will return the device codes of supported devices and the product code in response to the supported device inquiry. Command H'20 * Command, H'20, (one byte): Inquiry regarding supported devices Response H'30 Number of characters *** SUM Size Number of devices Product name Device code * Response, H'30, (one byte): Response to the supported device inquiry * Size (one byte): Number of bytes to be transmitted, excluding the command, size, and checksum, that is, the amount of data contributes by the number of devices, characters, device codes and product names * Number of devices (one byte): The number of device types supported by the boot program * Number of characters (one byte): The number of characters in the device codes and boot program's name * Device code (four bytes): ASCII code of the supporting product * Product name (n bytes): Type name of the boot program in ASCII-coded characters * SUM (one byte): Checksum The checksum is calculated so that the total number of all values from the command byte to the SUM byte becomes H'00. Rev. 2.00 Mar. 15, 2006 Page 612 of 754 REJ09B0199-0200 Section 17 Flash Memory (0.18-m F-ZTAT Version) (b) Device Selection The boot program will set the supported device to the specified device code. The program will return the selected device code in response to the inquiry after this setting has been made. Command H'10 Size Device code SUM * Command, H'10, (one byte): Device selection * Size (one byte): Amount of device-code data This is fixed at 4 * Device code (four bytes): Device code (ASCII code) returned in response to the supported device inquiry * SUM (one byte): Checksum Response H'06 * Response, H'06, (one byte): Response to the device selection command ACK will be returned when the device code matches. Error response H'90 ERROR * Error response, H'90, (one byte): Error response to the device selection command * ERROR : (one byte): Error code H'11: Sum check error H'21: Device code error, that is, the device code does not match (c) Clock Mode Inquiry The boot program will return the supported clock modes in response to the clock mode inquiry. Command H'21 * Command, H'21, (one byte): Inquiry regarding clock mode Response H'31 Size Number of modes Mode *** SUM * Response, H'31, (one byte): Response to the clock-mode inquiry * Size (one byte): Amount of data that represents the number of modes and modes * Number of clock modes (one byte): The number of supported clock modes H'00 indicates no clock mode or the device allows to read the clock mode. * Mode (one byte): Values of the supported clock modes (i.e. H'01 means clock mode 1.) * SUM (one byte): Checksum Rev. 2.00 Mar. 15, 2006 Page 613 of 754 REJ09B0199-0200 Section 17 Flash Memory (0.18-m F-ZTAT Version) (d) Clock Mode Selection The boot program will set the specified clock mode. The program will return the selected clockmode information after this setting has been made. The clock-mode selection command should be sent after the device-selection commands. Command H'11 Size Mode SUM * * * * Command, H'11, (one byte): Selection of clock mode Size (one byte): Amount of data that represents the modes Mode (one byte): A clock mode returned in reply to the supported clock mode inquiry. SUM (one byte): Checksum H'06 Response * Response, H'06, (one byte): Response to the clock mode selection command ACK will be returned when the clock mode matches. Error Response H'91 ERROR * Error response, H'91, (one byte) : Error response to the clock mode selection command * ERROR : (one byte): Error code H'11: Checksum error H'22: Clock mode error, that is, the clock mode does not match. Even if the clock mode numbers are H'00 and H'01 by a clock mode inquiry, the clock mode must be selected using these respective values. Rev. 2.00 Mar. 15, 2006 Page 614 of 754 REJ09B0199-0200 Section 17 Flash Memory (0.18-m F-ZTAT Version) (e) Multiplication Ratio Inquiry The boot program will return the supported multiplication and division ratios. Command H'22 * Command, H'22, (one byte): Inquiry regarding multiplication ratio Response H'32 Number of multiplication ratios *** SUM Size Multiplication ratio Number of types *** * Response, H'32, (one byte): Response to the multiplication ratio inquiry * Size (one byte): The amount of data that represents the number of clock sources and multiplication ratios and the multiplication ratios * Number of types (one byte): The number of supported multiplied clock types (e.g. when there are two multiplied clock types, which are the main and peripheral clocks, the number of types will be H'02.) * Number of multiplication ratios (one byte): The number of multiplication ratios for each type (e.g. the number of multiplication ratios to which the main clock can be set and the peripheral clock can be set.) * Multiplication ratio (one byte) Multiplication ratio: The value of the multiplication ratio (e.g. when the clock-frequency multiplier is four, the value of multiplication ratio will be H'04.) Division ratio: The inverse of the division ratio, i.e. a negative number (e.g. when the clock is divided by two, the value of division ratio will be H'FE. H'FE = D'-2) The number of multiplication ratios returned is the same as the number of multiplication ratios and as many groups of data are returned as there are types. * SUM (one byte): Checksum Rev. 2.00 Mar. 15, 2006 Page 615 of 754 REJ09B0199-0200 Section 17 Flash Memory (0.18-m F-ZTAT Version) (f) Operating Clock Frequency Inquiry The boot program will return the number of operating clock frequencies, and the maximum and minimum values. Command H'23 * Command, H'23, (one byte): Inquiry regarding operating clock frequencies Response H'33 Size Number of operating clock frequencies Maximum value of operating clock frequency Minimum value of operating clock frequency *** SUM * Response, H'33, (one byte): Response to operating clock frequency inquiry * Size (one byte): The number of bytes that represents the minimum values, maximum values, and the number of frequencies. * Number of operating clock frequencies (one byte): The number of supported operating clock frequency types (e.g. when there are two operating clock frequency types, which are the main and peripheral clocks, the number of types will be H'02.) * Minimum value of operating clock frequency (two bytes): The minimum value of the multiplied or divided clock frequency. The minimum and maximum values of the operating clock frequency represent the values in MHz, valid to the hundredths place of MHz, and multiplied by 100. (e.g. when the value is 17.00 MHz, it will be 2000, which is H'07D0.) * Maximum value (two bytes): Maximum value among the multiplied or divided clock frequencies. There are as many pairs of minimum and maximum values as there are operating clock frequencies. * SUM (one byte): Checksum Rev. 2.00 Mar. 15, 2006 Page 616 of 754 REJ09B0199-0200 Section 17 Flash Memory (0.18-m F-ZTAT Version) (g) User Boot MAT Information Inquiry The boot program will return the number of user boot MATs and their addresses. Command H'24 * Command, H'24, (one byte): Inquiry regarding user boot MAT information Response H'34 *** SUM Size Number of areas Area-last address Area-start address * Response, H'34, (one byte): Response to user boot MAT information inquiry * Size (one byte): The number of bytes that represents the number of areas, area-start addresses, and area-last address * Number of Areas (one byte): The number of consecutive user boot MAT areas When user boot MAT areas are consecutive, the number of areas returned is H'01. * Area-start address (four byte): Start address of the area * Area-last address (four byte): Last address of the area There are as many groups of data representing the start and last addresses as there are areas. * SUM (one byte): Checksum (h) User MAT Information Inquiry The boot program will return the number of user MATs and their addresses. Command H'25 * Command, H'25, (one byte): Inquiry regarding user MAT information Response H'35 *** SUM Size Number of areas Last address area Start address area * Response, H'35, (one byte): Response to the user MAT information inquiry * Size (one byte): The number of bytes that represents the number of areas, area-start address and area-last address * Number of areas (one byte): The number of consecutive user MAT areas When the user MAT areas are consecutive, the number of areas is H'01. * Area-start address (four bytes): Start address of the area Rev. 2.00 Mar. 15, 2006 Page 617 of 754 REJ09B0199-0200 Section 17 Flash Memory (0.18-m F-ZTAT Version) * Area-last address (four bytes): Last address of the area There are as many groups of data representing the start and last addresses as there are areas. * SUM (one byte): Checksum (i) Erased Block Information Inquiry The boot program will return the number of erased blocks and their addresses. Command H'26 * Command, H'26, (two bytes): Inquiry regarding erased block information Response H'36 *** SUM Size Number of blocks Block last address Block start address * Response, H'36, (one byte): Response to the number of erased blocks and addresses * Size (three bytes): The number of bytes that represents the number of blocks, block-start addresses, and block-last addresses. * Number of blocks (one byte): The number of erased blocks * Block start address (four bytes): Start address of a block * Block last Address (four bytes): Last address of a block There are as many groups of data representing the start and last addresses as there are areas. * SUM (one byte): Checksum (j) Programming Unit Inquiry The boot program will return the programming unit used to program data. Command H'27 * Command, H'27, (one byte): Inquiry regarding programming unit Response H'37 Size Programming unit SUM * Response, H'37, (one byte): Response to programming unit inquiry * Size (one byte): The number of bytes that indicate the programming unit, which is fixed to 2 * Programming unit (two bytes): A unit for programming This is the unit for reception of programming. * SUM (one byte): Checksum Rev. 2.00 Mar. 15, 2006 Page 618 of 754 REJ09B0199-0200 Section 17 Flash Memory (0.18-m F-ZTAT Version) (k) New Bit-Rate Selection The boot program will set a new bit rate and return the new bit rate. This selection should be sent after sending the clock mode selection command. Command H'3F Number of multiplication ratios SUM Size Multiplication ratio 1 Bit rate Multiplication ratio 2 Input frequency * Command, H'3F, (one byte): Selection of new bit rate * Size (one byte): The number of bytes that represents the bit rate, input frequency, number of multiplication ratios, and multiplication ratio * Bit rate (two bytes): New bit rate One hundredth of the value (e.g. when the value is 19200 bps, it will be 192, which is H'00C0.) * Input frequency (two bytes): Frequency of the clock input to the boot program This is valid to the hundredths place and represents the value in MHz multiplied by 100. (E.g. when the value is 20.00 MHz, it will be 2000, which is H'07D0.) * Number of multiplication ratios (one byte): The number of multiplication ratios to which the device can be set. * Multiplication ratio 1 (one byte) : The value of multiplication or division ratios for the main operating frequency Multiplication ratio (one byte): The value of the multiplication ratio (e.g. when the clock frequency is multiplied by four, the multiplication ratio will be H'04.) Division ratio: The inverse of the division ratio, as a negative number (e.g. when the clock frequency is divided by two, the value of division ratio will be H'FE. H'FE = D'-2) * Multiplication ratio 2 (one byte): The value of multiplication or division ratios for the peripheral frequency Multiplication ratio (one byte): The value of the multiplication ratio (e.g. when the clock frequency is multiplied by four, the multiplication ratio will be H'04.) (Division ratio: The inverse of the division ratio, as a negative number (E.g. when the clock is divided by two, the value of division ratio will be H'FE. H'FE = D'-2) * SUM (one byte): Checksum Response H'06 * Response, H'06, (one byte): Response to selection of a new bit rate When it is possible to set the bit rate, the response will be ACK. Rev. 2.00 Mar. 15, 2006 Page 619 of 754 REJ09B0199-0200 Section 17 Flash Memory (0.18-m F-ZTAT Version) Error Response H'BF ERROR * Error response, H'BF, (one byte): Error response to selection of new bit rate * ERROR: (one byte): Error code H'11: Sum checking error H'24: Bit-rate selection error The rate is not available. H'25: Error in input frequency This input frequency is not within the specified range. H'26: Multiplication-ratio error The ratio does not match an available ratio. H'27: Operating frequency error The frequency is not within the specified range. (4) Receive Data Check The methods for checking of receive data are listed below. 1. Input frequency The received value of the input frequency is checked to ensure that it is within the range of minimum to maximum frequencies which matches the clock modes of the specified device. When the value is out of this range, an input-frequency error is generated. 2. Multiplication ratio The received value of the multiplication ratio or division ratio is checked to ensure that it matches the clock modes of the specified device. When the value is out of this range, an inputfrequency error is generated. 3. Operating frequency Operating frequency is calculated from the received value of the input frequency and the multiplication or division ratio. The input frequency is input to the LSI and the LSI is operated at the operating frequency. The expression is given below. Operating frequency = Input frequency x Multiplication ratio, or Operating frequency = Input frequency / Division ratio The calculated operating frequency should be checked to ensure that it is within the range of minimum to maximum frequencies which are available with the clock modes of the specified device. When it is out of this range, an operating frequency error is generated. Rev. 2.00 Mar. 15, 2006 Page 620 of 754 REJ09B0199-0200 Section 17 Flash Memory (0.18-m F-ZTAT Version) 4. Bit rate To facilitate error checking, the value (n) of clock select (CKS) in the serial mode register (SMR), and the value (N) in the bit rate register (BRR), which are found from the peripheral operating clock frequency () and bit rate (B), are used to calculate the error rate to ensure that it is less than 4%. If the error is more than 4%, a bit rate error is generated. The error is calculated using the following expression: Error (%) = {[ x 106 (N + 1) x B x 64 x 2(2xn - 1) ] - 1} x 100 When the new bit rate is selectable, the rate will be set in the register after sending ACK in response. The host will send an ACK with the new bit rate for confirmation and the boot program will response with that rate. Confirmation H'06 * Confirmation, H'06, (one byte): Confirmation of a new bit rate Response H'06 * Response, H'06, (one byte): Response to confirmation of a new bit rate The sequence of new bit-rate selection is shown in figure 17.24. Host Setting a new bit rate H'06 (ACK) Waiting for one-bit period at the specified bit rate Boot program Setting a new bit rate Setting a new bit rate H'06 (ACK) with the new bit rate H'06 (ACK) with the new bit rate Figure 17.24 New Bit-Rate Selection Sequence Rev. 2.00 Mar. 15, 2006 Page 621 of 754 REJ09B0199-0200 Section 17 Flash Memory (0.18-m F-ZTAT Version) (5) Transition to Programming/Erasing State The boot program will transfer the erasing program, and erase the user MATs and user boot MATs in that order. On completion of this erasure, ACK will be returned and will enter the programming/erasing state. The host should select the device code, clock mode, and new bit rate with device selection, clockmode selection, and new bit-rate selection commands, and then send the command for the transition to programming/erasing state. These procedures should be carried out before sending of the programming selection command or program data. Command H'40 * Command, H'40, (one byte): Transition to programming/erasing state Response H'06 * Response, H'06, (one byte): Response to transition to programming/erasing state The boot program will send ACK when the user MAT and user boot MAT have been erased by the transferred erasing program. Error Response H'C0 H'51 * Error response, H'C0, (one byte): Error response for user boot MAT blank check * Error code, H'51, (one byte): Erasing error An error occurred and erasure was not completed. (6) Command Error A command error will occur when a command is undefined, the order of commands is incorrect, or a command is unacceptable. Issuing a clock-mode selection command before a device selection or an inquiry command after the transition to programming/erasing state command, are examples. Error Response H'80 H'xx * Error response, H'80, (one byte): Command error * Command, H'xx, (one byte): Received command Rev. 2.00 Mar. 15, 2006 Page 622 of 754 REJ09B0199-0200 Section 17 Flash Memory (0.18-m F-ZTAT Version) (7) Command Order The order for commands in the inquiry selection state is shown below. 1. A supported device inquiry (H'20) should be made to inquire about the supported devices. 2. The device should be selected from among those described by the returned information and set with a device-selection (H'10) command. 3. A clock-mode inquiry (H'21) should be made to inquire about the supported clock modes. 4. The clock mode should be selected from among those described by the returned information and set. 5. After selection of the device and clock mode, inquiries for other required information should be made, such as the multiplication-ratio inquiry (H'22) or operating frequency inquiry (H'23), which are needed for a new bit-rate selection. 6. A new bit rate should be selected with the new bit-rate selection (H'3F) command, according to the returned information on multiplication ratios and operating frequencies. 7. After selection of the device and clock mode, the information of the user boot MAT and user MAT should be made to inquire about the user boot MATs information inquiry (H'24), user MATs information inquiry (H'25), erased block information inquiry (H'26), and programming unit inquiry (H'27). 8. After making inquiries and selecting a new bit rate, issue the transition to programming/erasing state command (H'40). The boot program will then enter the programming/erasing state. Rev. 2.00 Mar. 15, 2006 Page 623 of 754 REJ09B0199-0200 Section 17 Flash Memory (0.18-m F-ZTAT Version) (8) Programming/Erasing State A programming selection command makes the boot program select the programming method, a 128-byte programming command makes it program the memory with data, and an erasing selection command and block erasing command make it erase the block. Table 17.16 lists the programming/erasing commands. Table 17.16 Programming/Erasing Commands Command H'42 H'43 H'50 H'48 H'58 H'52 H'4A H'4B H'4C H'4D H'4F Command Name Description User boot MAT programming selection Transfers the user boot MAT programming program User MAT programming selection 128-byte programming Erasing selection Block erasing Memory read User boot MAT sum check User MAT sum check User boot MAT blank check User MAT blank check Boot program status inquiry Transfers the user MAT programming program Programs 128 bytes of data Transfers the erasing program Erases a block of data Reads the contents of memory Checks the checksum of the user boot MAT Checks the checksum of the user MAT Checks the blank data of the user boot MAT Checks the blank data of the user MAT Inquires into the boot program's status Rev. 2.00 Mar. 15, 2006 Page 624 of 754 REJ09B0199-0200 Section 17 Flash Memory (0.18-m F-ZTAT Version) * Programming Programming is executed by the programming selection and 128-byte programming commands. Firstly, the host should send the programming selection command and select the programming method and programming MATs. There are two programming selection commands, and selection is according to the area and method for programming. 1. User boot MAT programming selection 2. User MAT programming selection After issuing the programming selection command, the host should send the 128-byte programming command. The 128-byte programming command that follows the selection command represents the data programmed according to the method specified by the selection command. When more than 128-byte data is programmed, 128-byte commands should repeatedly be executed. Sending a 128-byte programming command with H'FFFFFFFF as the address will stop the programming. On completion of programming, the boot program will wait for selection of programming or erasing. Where the sequence of programming operations that is executed includes programming with another method or of another MAT, the procedure must be repeated from the programming selection command. The sequence for the programming selection and 128-byte programming commands is shown in figure 17.25. Host Programming selection (H'42, H'43) Boot program Transfer of the programming program ACK 128-byte programming (address, data) Repeat ACK 128-byte programming (H'FFFFFFFF) ACK Programming Figure 17.25 Programming Sequence Rev. 2.00 Mar. 15, 2006 Page 625 of 754 REJ09B0199-0200 Section 17 Flash Memory (0.18-m F-ZTAT Version) * Erasure Erasure is executed by the erasure selection and block erasure commands. Firstly, erasure is selected by the erasure selection command and the boot program then erases the specified block. The command should be repeatedly executed if two or more blocks are to be erased. Sending a block erasure command from the host with the block number H'FF will stop the erasure operating. On completion of erasing, the boot program will wait for selection of programming or erasing. The sequence for the erasure selection and block erasure commands is shown in figure 17.26. Host Boot program Preparation for erasure (H'48) Transfer of erasure program ACK Erasure (Erasure block number) Repeat ACK Erasure Erasure (H'FF) ACK Figure 17.26 Erasure Sequence Rev. 2.00 Mar. 15, 2006 Page 626 of 754 REJ09B0199-0200 Section 17 Flash Memory (0.18-m F-ZTAT Version) (a) User Boot MAT Programming Selection The boot program will transfer a programming program. The data is programmed to the user boot MATs by the transferred programming program. Command H'42 * Command, H'42, (one byte): User boot-program programming selection Response H'06 * Response, H'06, (one byte): Response to user boot-program programming selection When the programming program has been transferred, the boot program will return ACK. Error Response H'C2 ERROR * Error response : H'C2 (1 byte): Error response to user boot MAT programming selection * ERROR : (1 byte): Error code H'54: Selection processing error (transfer error occurs and processing is not completed) (b) (b) User MAT Programming Selection The boot program will transfer a program for user MAT programming selection. The data is programmed to the user MATs by the transferred program for programming. Command H'43 * Command, H'43, (one byte): User-program programming selection Response H'06 * Response, H'06, (one byte): Response to user-program programming selection When the programming program has been transferred, the boot program will return ACK. Error Response H'C3 ERROR * Error response : H'C3 (1 byte): Error response to user boot MAT programming selection * ERROR : (1 byte): Error code H'54: Selection processing error (transfer error occurs and processing is not completed) (c) 128-Byte Programming The boot program will use the programming program transferred by the programming selection to program the user boot MATs or user MATs in response to 128-byte programming. Rev. 2.00 Mar. 15, 2006 Page 627 of 754 REJ09B0199-0200 Section 17 Flash Memory (0.18-m F-ZTAT Version) Command H'50 Data *** SUM Address *** * Command, H'50, (one byte): 128-byte programming * Programming Address (four bytes): Start address for programming Multiple of the size specified in response to the programming unit inquiry (i.e. H'00, H'01, H'00, H'00 : H'00010000) * Program data (128 bytes): Data to be programmed The size is specified in the response to the programming unit inquiry. * SUM (one byte): Checksum Response H'06 * Response, H'06, (one byte): Response to 128-byte programming On completion of programming, the boot program will return ACK. Error Response H'D0 ERROR * Error response, H'D0, (one byte): Error response for 128-byte programming * ERROR: (one byte): Error code H'11: Checksum Error H'2A: Address error The read address is not in the MAT. H'53: Programming error A programming error has occurred and programming cannot be continued. The specified address should match the unit for programming of data. For example, when the programming is in 128-byte units, the lower eight bits of the address should be H'00 or H'80. When there are less than 128 bytes of data to be programmed, the host should fill the rest with H'FF. Sending the 128-byte programming command with the address of H'FFFFFFFF will stop the programming operation. The boot program will interpret this as the end of the programming and wait for selection of programming or erasing. Command H'50 Address SUM * Command, H'50, (one byte): 128-byte programming * Programming Address (four bytes): End code is H'FF, H'FF, H'FF, H'FF. * SUM (one byte): Checksum Rev. 2.00 Mar. 15, 2006 Page 628 of 754 REJ09B0199-0200 Section 17 Flash Memory (0.18-m F-ZTAT Version) Response H'06 * Response, H'06, (one byte): Response to 128-byte programming On completion of programming, the boot program will return ACK. Error Response H'D0 ERROR * Error Response, H'D0, (one byte): Error response for 128-byte programming * ERROR: (one byte): Error code H'11: Checksum error H'53: Programming error An error has occurred in programming and programming cannot be continued. (d) Erasure Selection The boot program will transfer the erasure program. User MAT data is erased by the transferred erasure program. Command H'48 * Command, H'48, (one byte): Erasure selection Response H'06 * Response, H'06, (one byte): Response for erasure selection After the erasure program has been transferred, the boot program will return ACK. Error Response H'C8 ERROR * Error Response, H'C8, (one byte): Error response to erasure selection * ERROR: (one byte): Error code H'54: Selection processing error (transfer error occurs and processing is not completed) (e) Block Erasure The boot program will erase the contents of the specified block. Command H'58 Size Block number SUM * Command, H'58, (one byte): Erasure * Size (one byte): The number of bytes that represents the erase block number This is fixed to 1. * Block number (one byte): Number of the block to be erased * SUM (one byte): Checksum Rev. 2.00 Mar. 15, 2006 Page 629 of 754 REJ09B0199-0200 Section 17 Flash Memory (0.18-m F-ZTAT Version) Response H'06 * Response, H'06, (one byte): Response to Erasure After erasure has been completed, the boot program will return ACK. Error Response H'D8 ERROR * Error Response, H'D8, (one byte): Response to Erasure * ERROR (one byte): Error code H'11: Sum check error H'29: Block number error Block number is incorrect. H'51: Erasure error An error has occurred during erasure. On receiving block number H'FF, the boot program will stop erasure and wait for a selection command. Command H'58 Size Block number SUM * Command, H'58, (one byte): Erasure * Size, (one byte): The number of bytes that represents the block number This is fixed to 1. * Block number (one byte): H'FF Stop code for erasure * SUM (one byte): Checksum Response H'06 * Response, H'06, (one byte): Response to end of erasure (ACK) When erasure is to be performed after the block number H'FF has been sent, the procedure should be executed from the erasure selection command. Rev. 2.00 Mar. 15, 2006 Page 630 of 754 REJ09B0199-0200 Section 17 Flash Memory (0.18-m F-ZTAT Version) (f) Memory Read The boot program will return the data in the specified address. Command H'52 Size Area Read address SUM Read size * Command: H'52 (1 byte): Memory read * Size (1 byte): Amount of data that represents the area, read address, and read size (fixed at 9) * Area (1 byte) H'00: User boot MAT H'01: User MAT An address error occurs when the area setting is incorrect. * Read address (4 bytes): Start address to be read from * Read size (4 bytes): Size of data to be read * SUM (1 byte): Checksum Response H'52 Data SUM Read size *** * * * * Response: H'52 (1 byte): Response to memory read Read size (4 bytes): Size of data to be read Data (n bytes): Data for the read size from the read address SUM (1 byte): Checksum H'D2 ERROR Error Response * Error response: H'D2 (1 byte): Error response to memory read * ERROR: (1 byte): Error code H'11: Sum check error H'2A: Address error The read address is not in the MAT. H'2B: Size error The read size exceeds the MAT. Rev. 2.00 Mar. 15, 2006 Page 631 of 754 REJ09B0199-0200 Section 17 Flash Memory (0.18-m F-ZTAT Version) (g) User-Boot Program Sum Check The boot program will return the byte-by-byte total of the contents of the bytes of the user-boot program, as a four-byte value. Command H'4A * Command, H'4A, (one byte): Sum check for user-boot program Response H'5A Size Checksum of user boot program SUM * Response, H'5A, (one byte): Response to the sum check of user-boot program * Size (one byte): The number of bytes that represents the checksum This is fixed to 4. * Checksum of user boot program (four bytes): Checksum of user boot MATs The total of the data is obtained in byte units. * SUM (one byte): Sum check for data being transmitted (h) User-Program Sum Check The boot program will return the byte-by-byte total of the contents of the bytes of the user program. Command H'4B * Command, H'4B, (one byte): Sum check for user program Response H'5B Size Checksum of user program SUM * Response, H'5B, (one byte): Response to the sum check of the user program * Size (one byte): The number of bytes that represents the checksum This is fixed to 4. * Checksum of user boot program (four bytes): Checksum of user MATs The total of the data is obtained in byte units. * SUM (one byte): Sum check for data being transmitted Rev. 2.00 Mar. 15, 2006 Page 632 of 754 REJ09B0199-0200 Section 17 Flash Memory (0.18-m F-ZTAT Version) (i) User Boot MAT Blank Check The boot program will check whether or not all user boot MATs are blank and return the result. Command H'4C * Command, H'4C, (one byte): Blank check for user boot MAT Response H'06 * Response, H'06, (one byte): Response to the blank check of user boot MAT If all user MATs are blank (H'FF), the boot program will return ACK. Error Response H'CC H'52 * Error Response, H'CC, (one byte): Response to blank check for user boot MAT * Error Code, H'52, (one byte): Erasure has not been completed. (j) User MAT Blank Check The boot program will check whether or not all user MATs are blank and return the result. Command H'4D * Command, H'4D, (one byte): Blank check for user MATs Response H'06 * Response, H'06, (one byte): Response to the blank check for user MATs If the contents of all user MATs are blank (H'FF), the boot program will return ACK. Error Response H'CD H'52 * Error Response, H'CD, (one byte): Error response to the blank check of user MATs. * Error code, H'52, (one byte): Erasure has not been completed. Rev. 2.00 Mar. 15, 2006 Page 633 of 754 REJ09B0199-0200 Section 17 Flash Memory (0.18-m F-ZTAT Version) (k) Boot Program State Inquiry The boot program will return indications of its present state and error condition. This inquiry can be made in the inquiry/selection state or the programming/erasing state. Command H'4F * Command, H'4F, (one byte): Response H'5F Size Inquiry regarding boot program's state ERROR SUM Status * * * * Response, H'5F, (one byte): Response to boot program state inquiry Size (one byte): The number of bytes. This is fixed to 2. Status (one byte): State of the boot program ERROR (one byte): Error status ERROR = 0 indicates normal operation. ERROR = 1 indicates error has occurred. * SUM (one byte): Sum check Table 17.17 Status Code Code H'11 H'12 H'13 H'1F H'31 H'3F H'4F H'5F Description Device selection wait Clock mode selection wait Bit rate selection wait Programming/erasing state transition wait (bit rate selection is completed) Programming state for erasure Programming/erasing selection wait (erasure is completed) Program data receive wait Erase block specification wait (erasure is completed) Rev. 2.00 Mar. 15, 2006 Page 634 of 754 REJ09B0199-0200 Section 17 Flash Memory (0.18-m F-ZTAT Version) Table 17.18 Error Code Code H'00 H'11 H'12 H'21 H'22 H'24 H'25 H'26 H'27 H'29 H'2A H'2B H'51 H'52 H'53 H'54 H'80 H'FF Description No error Sum check error Program size error Device code mismatch error Clock mode mismatch error Bit rate selection error Input frequency error Multiplication ratio error Operating frequency error Block number error Address error Data length error Erasure error Erasure incomplete error Programming error Selection processing error Command error Bit-rate-adjustment confirmation error Rev. 2.00 Mar. 15, 2006 Page 635 of 754 REJ09B0199-0200 Section 17 Flash Memory (0.18-m F-ZTAT Version) 17.14 Usage Notes 1. The initial state of the product at its shipment is in the erased state. For the product whose revision of erasing is undefined, we recommend to execute automatic erasure for checking the initial state (erased state) and compensating. 2. For the PROM programmer suitable for programmer mode in this LSI and its program version, refer to the instruction manual of the socket adapter. 3. If the socket, socket adapter, or product index does not match the specifications, too much current flows and the product may be damaged. 4. Use a PROM programmer that supports the device with 256-kbyte on-chip flash memory and 5.0-V programming voltage. Do not select HN28F101 and 3.3-V programming voltage with the programmer parameters. Use only the specified socket adapter. 5. Do not remove the chip from the PROM programmer nor input a reset signal during programming/erasing in which a high voltage is applied to the flash memory. Doing so may damage the flash memory permanently. If a reset is input accidentally, the reset must be released after the reset input period of at least 100 s. 6. The flash memory is not accessible until FKEY is cleared after programming/erasing starts. If the operating mode is changed and this LSI is restarted by a reset immediately after programming/erasing has finished, secure the reset input period (period of RES = 0) of at least 100 s. Transition to the reset state during programming/erasing is inhibited. If a reset is input accidentally, the reset must be released after the reset input period of at least 100 s. 7. At powering on or off the Vcc power supply, fix the RES pin to low and set the flash memory to hardware protection state. This power on/off timing must also be satisfied at a power-off and power-on caused by a power failure and other factors. 8. In on-board programming mode or programmer mode, programming of the 128-byte programming-unit block must be performed only once. Perform programming in the state where the programming-unit block is fully erased. 9. When the chip is to be reprogrammed with the programmer after execution of programming or erasure in on-board programming mode, it is recommended that automatic programming is performed after execution of automatic erasure. 10. To program the flash memory, the program data and program must be placed at higher addresses than those of the external interrupt vector table, and H'FF must be written to all the system reserved areas in the exception handling vector table. 11. The programming program that includes the initialization routine and the erasing program that includes the initialization routine are each 4 kbytes or less. Accordingly, when the CPU clock frequency is 48 MHz, the download for each program takes approximately 35 s at the maximum. Rev. 2.00 Mar. 15, 2006 Page 636 of 754 REJ09B0199-0200 Section 17 Flash Memory (0.18-m F-ZTAT Version) 12. A programming/erasing program for the flash memory used in a conventional F-ZTAT H8, H8S microcomputer which does not support download of the on-chip program by setting the SCO bit in FCCS to 1 cannot run in this LSI. Be sure to download the on-chip program to execute programming/erasing of the flash memory in this F-ZTAT H8SX microcomputer. 13. Unlike a conventional F-ZTAT H8 or H8S microcomputers, measures against a program crash are not taken by WDT during programming/erasing. When needed, measures should be taken by user. A periodic interrupt generated by the WDT can be used as the measures, as an example. The interrupt generation cycle should take into consideration time to download a programming/erasing program and time to program/erase the flash memory. 14. When downloading the programming/erasing program, do not clear the SCO bit in FCCS to 0 after immediately setting it to 1. Otherwise, download cannot be performed normally. Immediately after executing the instruction to set the SCO bit to 1, dummy read of the FCCS must be executed twice. 15. The contents of some general registers are not saved in a programming/erasing program. When needed, save general registers in the procedure program. Rev. 2.00 Mar. 15, 2006 Page 637 of 754 REJ09B0199-0200 Section 17 Flash Memory (0.18-m F-ZTAT Version) Rev. 2.00 Mar. 15, 2006 Page 638 of 754 REJ09B0199-0200 Section 18 Clock Pulse Generator Section 18 Clock Pulse Generator This LSI has an on-chip clock pulse generator (CPG) that generates the system clock (I), peripheral module clock (P), and external clock (B). The clock pulse generator consists of an oscillator, PLL (Phase Locked Loop) circuit, and divider. Figure 18.1 shows a block diagram of the clock pulse generator. Clock frequencies can be changed by the PLL circuit and divider in the CPG. Changing the system clock control register (SCKCR) setting by software can change the clock frequencies. This LSI supports three types of clocks: a system clock provided to the CPU and bus masters, a peripheral module clock provided to the peripheral modules, and an external clock provided to the external bus. These clocks can be specified independently. Note, however, that the frequencies of the peripheral clock and external clock are lower than that of the system clock. SCKCR ICK2 to ICK0 1/1 1/2 Selector System clock (I) 1/4 (to the CPU and 1/8 bus masters) SCKCR Divider (1/1, 1/2, 1/4, and 1/8) PCK2 to PCK0 1/1 1/2 Peripheral module 1/4 Selector clock (P) 1/8 (to peripheral modules) SCKCR BCK2 to BCK0 1/1 1/2 Selector External bus clock (B) 1/4 (to the B pin) 1/8 EXTAL Oscillator XTAL PLL circuit EXTAL x 8 Figure 18.1 Block Diagram of Clock Pulse Generator Rev. 2.00 Mar. 15, 2006 Page 639 of 754 REJ09B0199-0200 Section 18 Clock Pulse Generator 18.1 Register Description The clock pulse generator has the following register. * System clock control register (SCKCR) 18.1.1 System Clock Control Register (SCKCR) SCKCR controls B clock output and frequencies of the system, peripheral module, and external clocks, and selects the B clock to be output. Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W 15 PSTOP1 0 R/W 7 -- 0 R/W 14 -- 0 R/W 6 PCK2 0 R/W 13 POSEL1 0 R/W 5 PCK1 1 R/W 12 -- 0 R/W 4 PCK0 0 R/W 11 -- 0 R/W 3 -- 0 R/W 10 ICK2 0 R/W 2 BCK2 0 R/W 9 ICK1 1 R/W 1 BCK1 1 R/W 8 ICK0 0 R/W 0 BCK0 0 R/W Bit 15 Bit Name PSTOP1 Initial Value 0 R/W R/W Description Clock Output Enable Controls output on PA7. * Normal operation 0: B output 1: Fixed high * * Software standby mode Hardware standby mode X: Fixed high X: Hi-Z 14 0 R/W Reserved This bit is always read as 0. The write value should always be 0. Rev. 2.00 Mar. 15, 2006 Page 640 of 754 REJ09B0199-0200 Section 18 Clock Pulse Generator Bit 13 Bit Name POSEL1 Initial Value 0 R/W R/W Description B Output Select 1 Controls the B output on PA7. 0: External clock (B) 1: Setting prohibited 12, 11 All 0 R/W Reserved These bits are always read as 0. The write value should always be 0. 10 9 8 ICK2 ICK1 ICK0 0 1 0 R/W R/W R/W System Clock (I) Select These bits select the frequency of the system clock provided to the CPU, DTC, and DMAC. The ratio to the input clock is as follows: 000: x 8 001: x 4 010: x 2 011: x 1 1XX: Setting prohibited The frequency of the peripheral module clock changes to the same frequency as the system clock if the frequency of the system clock is lower than that of the peripheral module clock. 7 0 R/W Reserved This bit is always read as 0. The write value should always be 0. 6 5 4 PCK2 PCK1 PCK0 0 1 0 R/W R/W R/W Peripheral Module Clock (P) Select These bits select the frequency of the peripheral module clock. The ratio to the input clock is as follows: 000: x 8 001: x 4 010: x 2 011: x 1 1XX: Setting prohibited The frequency of the peripheral module clock should be lower than that of the system clock. Though these bits can be set so as to make the frequency of the peripheral module clock higher than that of the system clock, the clocks will have the same frequency in reality. Rev. 2.00 Mar. 15, 2006 Page 641 of 754 REJ09B0199-0200 Section 18 Clock Pulse Generator Bit 3 Bit Name Initial Value 0 R/W R/W Description Reserved This bit is always read as 0. The write value should always be 0. 2 1 0 BCK2 BCK1 BCK0 0 1 0 R/W R/W R/W External clock (B) Select These bits select the frequency of the external clock. The ratio to the input clock is as follows: 000: x 8 001: x 4 010: x 2 011: x 1 1XX: Setting prohibited The frequency of the external clock should be lower than that of the system clock. Though these bits can be set so as to make the frequency of the external clock higher than that of the system clock, the clocks will have the same frequency in reality. Note: X: Don't care Rev. 2.00 Mar. 15, 2006 Page 642 of 754 REJ09B0199-0200 Section 18 Clock Pulse Generator 18.2 Oscillator Clock pulses can be supplied by connecting a crystal resonator, or by input of an external clock. 18.2.1 Connecting Crystal Resonator A crystal resonator can be connected as shown in the example in figure 18.2. Select the damping resistance Rd according to table 18.1. An AT-cut parallel-resonance type should be used. When the clock is provided by connecting a crystal resonator, a crystal resonator having a frequency of 4 to 9 MHz should be connected. CL1 EXTAL XTAL Rd CL2 10 pF CL1 = CL2 22 pF Figure 18.2 Connection of Crystal Resonator (Example) Table 18.1 Damping Resistance Value Frequency (MHz) Rd () 4 500 6 300 8 200 9 100 Figure 18.3 shows an equivalent circuit of the crystal resonator. Use a crystal resonator that has the characteristics shown in table 18.2. CL L XTAL Rs EXTAL AT-cut parallel-resonance type C0 Figure 18.3 Crystal Resonator Equivalent Circuit Rev. 2.00 Mar. 15, 2006 Page 643 of 754 REJ09B0199-0200 Section 18 Clock Pulse Generator Table 18.2 Crystal Resonator Characteristics Frequency (MHz) RS Max. () C0 Max. (pF) 4 120 7 6 100 7 8 80 7 9 80 7 18.2.2 External Clock Input An external clock signal can be input as shown in the examples in figure 18.4. If the XTAL pin is left open, make sure that parasitic capacitance is no more than 10 pF. When the counter clock is input to the XTAL pin, make sure that the external clock is held high in standby mode. EXTAL XTAL Open External clock input (a) XTAL pin left open EXTAL XTAL External clock input (b) Counter clock input on XTAL pin Figure 18.4 External Clock Input (Examples) For the input conditions of the external clock, refer to table 21.4, Clock Timing, in section 21.3.1, Clock Timing. The input external clock should be from 4 to 9 MHz. Rev. 2.00 Mar. 15, 2006 Page 644 of 754 REJ09B0199-0200 Section 18 Clock Pulse Generator 18.3 PLL Circuit The PLL circuit has the function of multiplying the frequency of the clock from the oscillator by a factor of 8. The frequency multiplication factor is fixed. 18.4 Frequency Divider The frequency divider divides the PLL clock to generate a 1/2, 1/4, or 1/8 clock. After bits ICK2 to ICK0 and PCK 2 to PCK0 are modified, this LSI operates at the modified frequency. 18.5 18.5.1 Usage Notes Notes on Clock Pulse Generator 1. The following points should be noted since the frequency of (I: system clock and P: peripheral module clock) supplied to each module changes according to the setting of SCKCR. Select a clock division ratio that is within the operation guaranteed range of clock cycle time tcyc shown in the AC timing of electrical characteristics. When the SSU is in use, 8 MHz I 48 MHz, and 8 MHz P 24 MHz, the following settings are not permitted: I < 8MHz, I > 48 MHz, P < 8 MHz, and P > 24 MHz. When the SSU is not in use, 8 MHz I 48 MHz, and 8 MHz P 35 MHz, the following settings are not permitted: I < 8MHz, I > 48 MHz, P < 8MHz, and P > 35 MHz. 2. All the on-chip peripheral modules (except for the DTC and DMAC) operate on the P. Therefore, note that the time processing of modules such as a timer and SCI differs before and after changing the clock division ratio. In addition, wait time for clearing software standby mode differs by changing the clock division ratio. For details, see section 19.7.3, Setting Oscillation Settling Time after Clearing Software Standby Mode. 3. The relationship between the system clock and peripheral module clock is I P. In addition, the system clock setting has priority. Accordingly, P may have the frequency set by bits ICK2 to ICK0 regardless of the settings of bits PCK2 to PCK0. 4. Figure 18.5 shows the clock modification timing. After a value is written to SCKCR, this LSI waits for the current bus cycle to complete. After the current bus cycle completes, each clock frequency will be modified within one cycle (worst case) of the external clock. Rev. 2.00 Mar. 15, 2006 Page 645 of 754 REJ09B0199-0200 Section 18 Clock Pulse Generator One cycle (worst case) after the bus cycle completion External clock I Bus master CPU CPU CPU Operating clock specified in SCKCR Operating clock changed Figure 18.5 Clock Modification Timing 18.5.2 Notes on Resonator Since various characteristics related to the resonator are closely linked to the user's board design, thorough evaluation is necessary on the user's part, using the resonator connection examples shown in this section as a reference. As the parameters for the resonator will depend on the floating capacitance of the resonator and the mounting circuit, the parameters should be determined in consultation with the resonator manufacturer. The design must ensure that a voltage exceeding the maximum rating is not applied to the resonator pin. 18.5.3 Notes on Board Design When using the crystal resonator, place the crystal resonator and its load capacitors as close as possible to the XTAL and EXTAL pins. Other signal lines should be routed away from the oscillation circuit as shown in figure 18.6 to prevent induction from interfering with correct oscillation. Rev. 2.00 Mar. 15, 2006 Page 646 of 754 REJ09B0199-0200 Section 18 Clock Pulse Generator Inhibited Signal A Signal B This LSI CL2 XTAL EXTAL CL1 Figure 18.6 Note on Board Design for Oscillation Circuit Figure 18.7 shows a connection example of bypass capacitor. Please be sure to insert bypass capacitor (CB) close to the Vcc and Vss pins and its capacitance meets the characteristics of the user system board. This LSI Vcc (4) CB*2 C1*1 Vcc (46) VcL (50) Vss (48) CB*2 Vcc (26) Vss (24) Vss (6) Vcc (82) Vss (85) Vcc (64) Vss (62) CB*2 CB*2 CB*2 Notes: Numbers in parenthesis are pin numbers. 1. A 0.1-F capacitor should be used here. 2. CB is a laminated ceramic capacitor. Figure 18.7 Connection Example of Bypass Capacitor 18.5.4 Notes on Input Clock Frequency The frequency of the input clock is multiplied in the PLL circuit by a factor of 8. To reduce noises, a lower frequency ranging of 4 to 9 MHz is recommended. Rev. 2.00 Mar. 15, 2006 Page 647 of 754 REJ09B0199-0200 Section 18 Clock Pulse Generator Rev. 2.00 Mar. 15, 2006 Page 648 of 754 REJ09B0199-0200 Section 19 Power-Down Modes Section 19 Power-Down Modes This LSI has power consumption reduction functions, such as multi-clock function, module stop function, and transition function to power-down mode. 19.1 Features * Multi-clock function The frequency division ratio is settable independently for the system clock, peripheral module clock, and external bus clock. * Module stop function The functions for each peripheral modules can be stopped to make a transition to a powerdown mode. * Transition function to power-down mode Transition to a power-down mode is possible to stop the CPU, all the on-chip peripheral modules, and oscillator. * Three power-down modes Sleep mode All-module-clock-stop mode Software standby mode Table 19.1 shows conditions for making a transition to a power-down mode, states of the CPU and peripheral modules, and clearing method for each mode. After the reset state, since this LSI operates in normal program execution state, the modules, other than the DTC and DMAC are stopped. Rev. 2.00 Mar. 15, 2006 Page 649 of 754 REJ09B0199-0200 Section 19 Power-Down Modes Table 19.1 Operating States Operating State Sleep Mode Transition condition Cancellation method Oscillator CPU All-Module-Clock-Stop Mode Software Standby Mode Control register + instruction External interrupt Halted Halted (retained) Halted (retained) Halted*1 Retained Control register + Control register + instruction instruction Interrupt Functions Halted (retained) Interrupt*2 Functions Halted (retained) Functions Halted* 3 Watchdog timer Functions Other peripheral Functions modules I/O port Functions Retained Notes: "Halted (retained)" in the table means that the internal register values are retained and internal operations are suspended. 1. SCI and SSU enter the reset state, and other peripheral modules retain their states. 2. External interrupt and some internal interrupts (watchdog timer) 3. SSU enters the reset state, and other peripheral modules retain their states. SSBY = 0 Reset state SLEEP instruction RES pin = high All interrupts SLEEP instruction Program execution state Interrupt*1 SLEEP instruction SSBY = 1 External interrupt*2 Software standby mode Program halted state Transition after exception handling Notes: 1. NMI, IRQ0 to IRQ15, and watchdog timer interrupts. 2. NMI and IRQ0 to IRQ15. Note that IRQ is valid only when the corresponding bit in SSIER is set to 1. SSBY = 0, ACSE = 1 MSTPCR = H'F[0-F]FFFFFF All-module-clockstop mode Sleep mode Figure 19.1 Mode Transitions Rev. 2.00 Mar. 15, 2006 Page 650 of 754 REJ09B0199-0200 Section 19 Power-Down Modes 19.2 Register Descriptions The registers related to the power-down modes are shown below. For details on the system clock control register (SCKCR), refer to section 18.1.1, System Clock Control Register (SCKCR). * * * * Standby control register (SBYCR) Module stop control register A (MSTPCRA) Module stop control register B (MSTPCRB) Module stop control register C (MSTPCRC) Standby Control Register (SBYCR) 19.2.1 SBYCR controls software standby mode. Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W 15 SSBY 0 R/W 7 0 R/W 14 1 R/W 6 0 R/W 13 0 R/W 5 0 R/W 12 STS4 0 R/W 4 0 R/W 11 STS3 1 R/W 3 0 R/W 10 STS2 1 R/W 2 0 R/W 9 STS1 1 R/W 1 0 R/W 8 STS0 1 R/W 0 0 R/W Bit 15 Bit Name 0 Initial Value 0 R/W R/W Description Software Standby Specifies the transition mode after executing the SLEEP instruction 0: Shifts to sleep mode after the SLEEP instruction is executed 1: Shifts to software standby mode after the SLEEP instruction is executed Rev. 2.00 Mar. 15, 2006 Page 651 of 754 REJ09B0199-0200 Section 19 Power-Down Modes Bit 14 Bit Name Initial Value 1 R/W R/W Description Reserved This bit is always read as 1. The write value should always be 1. Reserved This bit is always read as 0. The write value should always be 0. Standby Timer Select 4 to 0 These bits select the time the MCU waits for the clock to settle when software standby mode is cleared by an external interrupt. With a crystal resonator, refer to table 19.2 and make a selection according to the operating frequency so that the standby time is at least equal to the oscillation settling time. With an external clock, a PLL circuit settling time is necessary. Refer to table 19.2 to set the standby time. While oscillation is being settled, the timer is counted on the P clock frequency. Careful consideration is required in multi-clock mode. 00000: Reserved 00001: Reserved 00010: Reserved 00011: Reserved 00100: Reserved 00101: Standby time = 64 states 00110: Standby time = 512 states 00111: Standby time = 1024 states 01000: Standby time = 2048 states 01001: Standby time = 4096 states 01010: Standby time = 16384 states 01011: Standby time = 32768 states 01100: Standby time = 65536 states 01101: Standby time = 131072 states 01110: Standby time = 262144 states 01111: Standby time = 524288 states 10000: Reserved 10001: Reserved 1001X: Reserved 101XX: Reserved 11XXX: Reserved 13 0 R/W 12 11 10 9 8 STS4 STS3 STS2 STS1 STS0 0 1 1 1 1 R/W R/W R/W R/W R/W Rev. 2.00 Mar. 15, 2006 Page 652 of 754 REJ09B0199-0200 Section 19 Power-Down Modes Bit 7 to 0 Bit Name Initial Value All 0 R/W R/W Description Reserved These bits are always read as 0. The write value should always be 0. Note: The flash memory settling time must be reserved. 19.2.2 Module Stop Control Registers A and B (MSTPCRA and MSTPCRB) MSTPCRA and MSTPCRB control module stop mode. Setting a bit to 1 makes the corresponding module enter module stop mode, while clearing the bit to 0 clears module stop mode. * MSTPCRA Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W 15 ACSE 0 R/W 7 MSTPA7 1 R/W 14 MSTPA14 0 R/W 6 MSTPA6 1 R/W 13 MSTPA13 0 R/W 5 MSTPA5 1 R/W 12 MSTPA12 0 R/W 4 MSTPA4 1 R/W 11 MSTPA11 1 R/W 3 MSTPA3 1 R/W 10 MSTPA10 1 R/W 2 MSTPA2 1 R/W 9 MSTPA9 1 R/W 1 MSTPA1 1 R/W 8 MSTPA8 1 R/W 0 MSTPA0 1 R/W * MSTPCRB Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W 15 MSTPB15 1 R/W 7 MSTPB7 1 R/W 14 MSTPB14 1 R/W 6 MSTPB6 1 R/W 13 MSTPB13 1 R/W 5 MSTPB5 1 R/W 12 MSTPB12 1 R/W 4 MSTPB4 1 R/W 11 MSTPB11 1 R/W 3 MSTPB3 1 R/W 10 MSTPB10 1 R/W 2 MSTPB2 1 R/W 9 MSTPB9 1 R/W 1 MSTPB1 1 R/W 8 MSTPB8 1 R/W 0 MSTPB0 1 R/W Rev. 2.00 Mar. 15, 2006 Page 653 of 754 REJ09B0199-0200 Section 19 Power-Down Modes * MSTPCRA Bit 15 Bit Name ACSE Initial Value 0 R/W R/W Module All-Module-Clock-Stop Mode Enable Enables/disables all-module-clock-stop mode for reducing current consumption by stopping the bus controller and I/O ports operations when the CPU executes the SLEEP instruction after module stop mode has been set for all the on-chip peripheral modules controlled by MSTPCR. 0: All-module-clock-stop mode disabled 1: All-module-clock-stop mode enabled 14 MSTPA14 0 R/W Reserved These bits are always read as 0. The write value should always be 0. 13 12 11 10 9 8 7 6 5 4 3 2 MSTPA13 MSTPA12 MSTPA11 MSTPA10 MSTPA9 MSTPA8 MSTPA7 MSTPA6 MSTPA5 MSTPA4 MSTPA3 MSTPA2 0 0 1 1 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W A/D converter (unit 1) A/D converter (unit 0) Reserved These bits are always read as 1. The write value should always be 1. 1 0 MSTPA1 MSTPA0 1 1 R/W R/W 16-bit timer pulse unit (TPU channels 11 to 6) 16-bit timer pulse unit (TPU channels 5 to 0) DMA controller (DMAC) Data transfer controller (DTC) Reserved These bits are always read as 1. The write value should always be 1. Rev. 2.00 Mar. 15, 2006 Page 654 of 754 REJ09B0199-0200 Section 19 Power-Down Modes * MSTPCRB Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Name MSTPB15 MSTPB14 MSTPB13 MSTPB12 MSTPB11 MSTPB10 MSTPB9 MSTPB MSTPB7 MSTPB6 MSTPB5 MSTPB4 MSTPB3 MSTPB2 MSTPB1 MSTPB0 Initial Value 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Module Programmable pulse generator (PPG) Reserved These bits are always read as 1. The write value should always be 1. Serial communication interface_4 (SCI_4) Serial communication interface_3 (SCI_3) Reserved These bits are always read as 1. The write value should always be 1. Rev. 2.00 Mar. 15, 2006 Page 655 of 754 REJ09B0199-0200 Section 19 Power-Down Modes 19.2.3 Module Stop Control Register C (MSTPCRC) When bits MSTPC1 and MSTPC0 are set to 1, the corresponding on-chip RAM stops. Do not set the corresponding MSTPC1 and MSTPC0 bits to 1 while accessing the on-chip RAM. Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W 15 MSTPC15 1 R/W 7 MSTPC7 0 R/W 14 MSTPC14 1 R/W 6 MSTPC6 0 R/W 13 MSTPC13 1 R/W 5 MSTPC5 0 R/W 12 MSTPC12 1 R/W 4 MSTPC4 0 R/W 11 MSTPC11 1 R/W 3 MSTPC3 0 R/W 10 MSTPC10 1 R/W 2 MSTPC2 0 R/W 9 MSTPC9 1 R/W 1 MSTPC1 0 R/W 8 MSTPC8 1 R/W 0 MSTPC0 0 R/W Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Name MSTPC15 MSTPC14 MSTPC13 MSTPC12 MSTPC11 MSTPC10 MSTPC9 MSTPC8 MSTPC7 MSTPC6 MSTPC5 MSTPC4 MSTPC3 MSTPC2 MSTPC1 MSTPC0 Initial Value 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Module Reserved These bits are always read as 1. The write value should always be 1. Synchronous serial communication unit 2 (SSU_2) Synchronous serial communication unit 1 (SSU_1) Synchronous serial communication unit 0 (SSU_0) Reserved These bits are always read as 0. The write value should always be 0. On-chip RAM (H'FFF9000 to H'FFFBFFF) The write value to MSTPC1 and MSTPC0 should always be the same. Rev. 2.00 Mar. 15, 2006 Page 656 of 754 REJ09B0199-0200 Section 19 Power-Down Modes 19.3 Multi-Clock Function When bits ICK2 to ICK0, PCK2 to PCK0, and BCK2 to BCK0 in SCKCR are set, a transition is made to multi-clock mode at the end of the bus cycle. In multi-clock mode, the CPU and bus masters operate on the operating clock specified by bits ICK2 to ICK0. The peripheral modules operate on the operating clock specified by bits PCK2 to PCK0. The external bus operates on the operating clock specified by bits BCK2 to BCK0. Even if the frequencies specified by bits PCK2 to PCK0 and BCK2 to BCK0 are higher than the frequency specified by bits ICK2 to ICK0, the specified values are not reflected in the peripheral module and external bus clocks. The peripheral module and external bus clocks are restricted to the operating clock specified by bits ICK2 to ICK0. Multi-clock mode is cleared by clearing all of bits ICK2 to ICK0, PCK2 to PCK0, and BCK2 to BCK0 to 0. A transition is made to normal mode at the end of the bus cycle, and multi-clock mode is cleared. If a SLEEP instruction is executed while the SSBY bit in SBYCR is cleared to 0, this LSI enters sleep mode. When sleep mode is cleared by an interrupt, multi-clock mode is restored. If a SLEEP instruction is executed while the SSBY bit in SBYCR is set to 1, this LSI enters software standby mode. When software standby mode is cleared by an external interrupt, multiclock mode is restored. When the RES pin is driven low, the reset state is entered and multi-clock mode is cleared. The same applies to a reset caused by watchdog timer overflow. 19.4 Module Stop Mode Module stop mode can be set for individual on-chip peripheral modules. When the corresponding MSTP bit in MSTPCRA, MSTPCRB, or MSTPCRC is set to 1, module operation stops at the end of the bus cycle and a transition is made to module stop mode. The CPU continues operating independently. When the corresponding MSTP bit is cleared to 0, module stop mode is cleared and the module starts operating at the end of the bus cycle. In module stop mode, the internal states of modules other than the SCI and SSU are retained. After the reset state is cleared, all modules other than the DMAC, DTC, and on-chip RAM are in module stop mode. Rev. 2.00 Mar. 15, 2006 Page 657 of 754 REJ09B0199-0200 Section 19 Power-Down Modes The registers of the module for which module stop mode is selected cannot be read from or written to. 19.5 19.5.1 Sleep Mode Transition to Sleep Mode When the SLEEP instruction is executed when the SSBY bit in SBYCR is 0, the CPU enters sleep mode. In sleep mode, CPU operation stops but the contents of the CPU's internal registers are retained. Other peripheral functions do not stop. 19.5.2 Clearing Sleep Mode Sleep mode is exited by any interrupt, signals on the RES pin, and a reset caused by a watchdog timer overflow. 1. Clearing by interrupt When an interrupt occurs, sleep mode is exited and interrupt exception processing starts. Sleep mode is not exited if the interrupt is disabled, or interrupts other than NMI are masked by the CPU. 2. Clearing by RES pin Setting the RES pin level low selects the reset state. After the stipulated reset input duration, driving the RES pin high makes the CPU start the reset exception processing. 3. Clearing by reset caused by watchdog timer overflow Sleep mode is exited by an internal reset caused by a watchdog timer overflow. 19.6 All-Module-Clock-Stop Mode When the ACSE bit in MSTPCRA is set to 1 and all modules controlled by MSTPCR are stopped (MSTPCRA, MSTPCRB = H'FFFFFFFF, MSTPCRC = H'FF00), executing a SLEEP instruction with the SSBY bit in SBYCR cleared to 0 will cause all modules (except for the watchdog timer), the bus controller, and the I/O ports to stop operating, and to make a transition to all-moduleclock-stop mode at the end of the bus cycle. All-module-clock-stop mode is cleared by an external interrupt (NMI or IRQ0 to IRQ15 pins), RES pin input, or an internal interrupt (watchdog timer), and the CPU returns to the normal program execution state via the exception handling state. All-module-clock-stop mode is not cleared if interrupts are disabled or interrupts other than NMI are masked on the CPU side. Rev. 2.00 Mar. 15, 2006 Page 658 of 754 REJ09B0199-0200 Section 19 Power-Down Modes 19.7 19.7.1 Software Standby Mode Transition to Software Standby Mode If a SLEEP instruction is executed when the SSBY bit in SBYCR is set to 1, software standby mode is entered. In this mode, the CPU, on-chip peripheral functions, and oscillator all stop. However, the contents of the CPU's internal registers, on-chip RAM data, and the states of on-chip peripheral functions other than the SCI and SSU, and the states of the I/O ports, are retained. In this mode the oscillator stops, allowing power consumption to be significantly reduced. If the WDT is used as a watchdog timer, it is impossible to make a transition to software standby mode. The WDT should be stopped before the SLEEP instruction execution. 19.7.2 Clearing Software Standby Mode Software standby mode is cleared by an external interrupt (NMI pin, or pins IRQ0 to IRQ15*), or by means of the RES pin. 1. Clearing by interrupt When an NMI or IRQ0 to IRQ15* interrupt request signal is input, clock oscillation starts, and after the elapse of the time set in bits STS4 to STS0 in SBYCR, stable clocks are supplied to the entire LSI, software standby mode is cleared, and interrupt exception handling is started. When clearing software standby mode with an IRQ0 to IRQ15* interrupt, set the corresponding enable bit to 1 and ensure that no interrupt with a higher priority than interrupts IRQ0 to IRQ15* is generated. Software standby mode cannot be cleared if the interrupt has been masked on the CPU side or has been designated as a DTC or DMAC activation source. Note: * By setting the SSIn bit in SSIER to 1, IRQ0 to IRQ15 can be used as a software standby mode clearing source. 2. Clearing by RES pin When the RES pin is driven low, clock oscillation is started. At the same time as clock oscillation starts, clocks are supplied to the entire LSI. Note that the RES pin must be held low until clock oscillation settles. When the RES pin goes high, the CPU begins reset exception handling. Rev. 2.00 Mar. 15, 2006 Page 659 of 754 REJ09B0199-0200 Section 19 Power-Down Modes 19.7.3 Setting Oscillation Settling Time after Clearing Software Standby Mode Bits STS4 to STS0 in SBYCR should be set as described below. 1. Using a crystal resonator Set bits STS4 to STS0 so that the standby time is at least equal to the oscillation settling time. Table 19.2 shows the standby times for operating frequencies and settings of bits STS4 to STS0. 2. Using an external clock A PLL circuit settling time is necessary. Refer to table 19.2 to set the standby time. Table 19.2 Oscillation Settling Time Settings Standby STS4 STS3 STS2 STS1 STS0 Time 0 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 0 Reserved Reserved Reserved Reserved Reserved 64 512 1024 2048 4096 16384 32765 65536 131072 262144 524288 Reserved P* [MHz] 35 1.8 14.6 29.3 58.5 0.12 0.47 0.94 1.87 3.74 7.49 14.98 25 2.6 20.5 41.0 81.9 0.16 0.66 1.31 2.62 5.24 10.49 20.97 20 3.2 25.6 51.2 102.4 0.20 0.82 1.64 3.28 6.55 13.11 26.21 13 4.9 39.4 78.8 157.5 0.32 1.26 2.52 5.04 10.08 20.16 40.33 10 6.4 51.2 102.4 204.8 0.41 1.64 3.28 6.55 13.11 26.21 52.43 8 8.0 64.0 128.0 256.0 0.51 2.05 4.10 8.19 16.38 32.77 65.54 ms Unit s : Recommended time setting when using an external clock. : Recommended time setting when using a crystal resonator. Note: * is the output from the peripheral module frequency divider. Rev. 2.00 Mar. 15, 2006 Page 660 of 754 REJ09B0199-0200 Section 19 Power-Down Modes 19.7.4 Software Standby Mode Application Example Figure 19.2 shows an example in which a transition is made to software standby mode at the falling edge on the NMI pin, and software standby mode is cleared at the rising edge on the NMI pin. In this example, an NMI interrupt is accepted with the NMIEG bit in INTCR cleared to 0 (falling edge specification), then the NMIEG bit is set to 1 (rising edge specification), the SSBY bit is set to 1, and a SLEEP instruction is executed, causing a transition to software standby mode. Software standby mode is then cleared at the rising edge on the NMI pin. Oscillator NMI NMIEG SSBY NMI exception handling NMIEG = 1 SSBY = 1 Software standby mode (power-down mode) Oscillation settling time tOSC2 NMI exception handling SLEEP instruction Figure 19.2 Software Standby Mode Application Example Rev. 2.00 Mar. 15, 2006 Page 661 of 754 REJ09B0199-0200 Section 19 Power-Down Modes 19.8 B Clock Output Control Output of the B clock can be controlled by bits PSTOP1 and POSEL1 in SCKCR, and DDR for the corresponding PA7 pin. Clearing both bits PSTOP1 and POSEL1 to 0 enables the B clock output on the PA7 pin. When bit PSTOP1 is set to 1, the B clock output stops at the end of the bus cycle, and the B clock output goes high. When DDR for the PA7 pin is cleared to 0, the B clock output is disabled and the pin becomes an input port. Disabling B output can reduce electromagnetic interference (EMI). Take it into consideration for design of the user system board. Tables 19.3 shows the states of the B pin in each processing state. Table 19.3 B Pin (PA7) State in Each Processing State Register Setting Value DDR 0 1 1 1 PSTOP1 POSEL1 Normal Operating State Hi-Z B output Setting prohibited High All-Module- Software Standby Mode Clock-Stop Sleep Mode Mode OPE = 0 OPE = 1 Hi-Z B output Setting prohibited High Hi-Z B output Setting prohibited High Hi-Z High Setting prohibited High Hi-Z High Setting prohibited High X 0 0 1 X 0 1 X Rev. 2.00 Mar. 15, 2006 Page 662 of 754 REJ09B0199-0200 Section 19 Power-Down Modes 19.9 19.9.1 Usage Notes I/O Port Status In software standby mode, the I/O port states are retained. Therefore, there is no reduction in current consumption for the output current when a high-level signal is output. 19.9.2 Current Consumption during Oscillation Settling Standby Period Current consumption increases during the oscillation settling standby period. 19.9.3 DTC and DMAC Module Stop Depending on the operating state of the DMAC and DTC, bit MSTPA13 or MSTPA12 may not be set to 1. Setting of the DMAC or DTC module stop mode should be carried out only when the DMAC or DTC is not activated. For details, refer to section 7, DMA Controller (DMAC), and section 8, Data Transfer Controller (DTC). 19.9.4 On-Chip Peripheral Module Interrupts Relevant interrupt operations cannot be performed in module stop mode. Consequently, if module stop mode is entered when an interrupt has been requested, it will not be possible to clear the CPU interrupt source or the DMAC or DTC activation source. Interrupts should therefore be disabled before entering module stop mode. 19.9.5 Writing to MSTPCRA, MSTPCRB, and MSTPCRC MSTPCRA, MSTPCRB, and MSTPCRC should only be written to by the CPU. Rev. 2.00 Mar. 15, 2006 Page 663 of 754 REJ09B0199-0200 Section 19 Power-Down Modes Rev. 2.00 Mar. 15, 2006 Page 664 of 754 REJ09B0199-0200 Section 20 List of Registers Section 20 List of Registers The register list gives information on the on-chip I/O register addresses, how the register bits are configured, and the register states in each operating mode. The information is given as shown below. 1. * * * Register addresses (address order) Registers are listed from the lower allocation addresses. Registers are classified according to functional modules. Undefined and reserved addresses cannot be accessed. Do not access these addresses; otherwise, the operation when accessing these bits and subsequent operations cannot be guaranteed. Register bits Bit configurations of the registers are listed in the same order as the register addresses. Reserved bits are indicated by in the bit name column. Space in the bit name field indicates that the entire register is allocated to either the counter or data. For the registers of 16 or 32 bits, the MSB is listed first. Byte configuration description order is subject to big endian. Register states in each operating mode Register states are listed in the same order as the register addresses. For the initialized state of each bit, refer to the register description in the corresponding section. The register states shown here are for the basic operating modes. If there is a specific reset for an on-chip peripheral module, refer to the section on that on-chip peripheral module. 2. * * * * 3. * * * Rev. 2.00 Mar. 15, 2006 Page 665 of 754 REJ09B0199-0200 Section 20 List of Registers 20.1 Register Addresses (Address Order) Number of Bits Address* 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 H'FF200 H'FF201 H'FF202 H'FF203 H'FF204 H'FF205 H'FF206 H'FF207 H'FF208 H'FF209 H'FF20A H'FF20B H'FF20C H'FF20D H'FF210 H'FF211 H'FF212 H'FF213 H'FF214 H'FF215 H'FF216 H'FF217 H'FF218 H'FF219 H'FF21A H'FF21B H'FF21C H'FF21D H'FF220 H'FF221 Data Width 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 Access Cycles (Read/Write) 3P/3P 3P/3P 3P/3P 3P/3P 3P/3P 3P/3P 3P/3P 3P/3P 3P/3P 3P/3P 3P/3P 3P/3P 3P/3P 3P/3P 3P/3P 3P/3P 3P/3P 3P/3P 3P/3P 3P/3P 3P/3P 3P/3P 3P/3P 3P/3P 3P/3P 3P/3P 3P/3P 3P/3P 3P/3P 3P/3P Register Name SS control register H_0 SS control register L_0 SS mode register_0 SS enable register_0 SS status register_0 SS control register 2_0 SS transmit data register 0_0 SS transmit data register 1_0 SS transmit data register 2_0 SS transmit data register 3_0 SS receive data register 0_0 SS receive data register 1_0 SS receive data register 2_0 SS receive data register 3_0 SS control register H_1 SS control register L_1 SS mode register_1 SS enable register_1 SS status register_1 SS control register2_1 SS transmit data register 0_1 SS transmit data register 1_1 SS transmit data register 2_1 SS transmit data register 3_1 SS receive data register 0_1 SS receive data register 1_1 SS receive data register 2_1 SS receive data register 3_1 SS control register H_2 SS control register L_2 Abbr. SSCRH_0 SSCRL_0 SSMR_0 SSER_0 SSSR_0 SSCR2_0 SSTDR0_0 SSTDR1_0 SSTDR2_0 SSTDR3_0 SSRDR0_0 SSRDR1_0 SSRDR2_0 SSRDR3_0 SSCRH_1 SSCRL_1 SSMR_1 SSER_1 SSSR_1 SSCR2_1 SSTDR0_1 SSTDR1_1 SSTDR2_1 SSTDR3_1 SSRDR0_1 SSRDR1_1 SSRDR2_1 SSRDR3_1 SSCRH_2 SSCRL_2 Module SSU_0 SSU_0 SSU_0 SSU_0 SSU_0 SSU_0 SSU_0 SSU_0 SSU_0 SSU_0 SSU_0 SSU_0 SSU_0 SSU_0 SSU_1 SSU_1 SSU_1 SSU_1 SSU_1 SSU_1 SSU_1 SSU_1 SSU_1 SSU_1 SSU_1 SSU_1 SSU_1 SSU_1 SSU_2 SSU_2 Rev. 2.00 Mar. 15, 2006 Page 666 of 754 REJ09B0199-0200 Section 20 List of Registers Register Name SS mode register_2 SS enable register_2 SS status register_2 SS control register 2_2 SS transmit data register 0_2 SS transmit data register 1_2 SS transmit data register 2_2 SS transmit data register 3_2 SS receive data register 0_2 SS receive data register 1_2 SS receive data register 2_2 SS receive data register 3_2 Abbr. SSMR_2 SSER_2 SSSR_2 SSCR2_2 SSTDR0_2 SSTDR1_2 SSTDR2_2 SSTDR3_2 SSRDR0_2 SSRDR1_2 SSRDR2_2 SSRDR3_2 Number of Bits Address* 8 8 8 8 8 8 8 8 8 8 8 8 8 16 16 16 16 16 16 16 16 16 8 8 8 8 8 8 8 8 8 H'FF222 H'FF223 H'FF224 H'FF225 H'FF226 H'FF227 H'FF228 H'FF229 H'FF22A H'FF22B H'FF22C H'FF22D H'FF240 H'FF284 H'FFA90 H'FFA92 H'FFA94 H'FFA96 H'FFA98 H'FFA9A H'FFA9C H'FFA9E H'FFAA0 H'FFAA1 H'FFB00 H'FFB01 H'FFB10 H'FFB11 H'FFB12 H'FFB13 H'FFB14 Module SSU_2 SSU_2 SSU_2 SSU_2 SSU_2 SSU_2 SSU_2 SSU_2 SSU_2 SSU_2 SSU_2 SSU_2 PORT A/D A/D_1 A/D_1 A/D_1 A/D_1 A/D_1 A/D_1 A/D_1 A/D_1 A/D_1 A/D_1 TPU TPU TPU_6 TPU_6 TPU_6 TPU_6 TPU_6 Data Width 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 Access Cycles (Read/Write) 3P/3P 3P/3P 3P/3P 3P/3P 3P/3P 3P/3P 3P/3P 3P/3P 3P/3P 3P/3P 3P/3P 3P/3P 3P/3P 3P/3P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P Port H realtime input data register PHRTIDR Analog port pull-down control register A/D data register A_1 A/D data register B_1 A/D data register C_1 A/D data register D_1 A/D data register E_1 A/D data register F_1 A/D data register G_1 A/D data register H_1 A/D control/status register_1 A/D control register_1 Timer start register Timer synchronous register Timer control register_6 Timer mode register_6 Timer I/O control register H_6 Timer I/O control register L_6 Timer interrupt enable register_6 APPDCR ADDRA_1 ADDRB_1 ADDRC_1 ADDRD_1 ADDRE_1 ADDRF_1 ADDRG_1 ADDRH_1 ADCSR_1 ADCR_1 TSTRB TSYRB TCR_6 TMDR_6 TIORH_6 TIORL_6 TIER_6 Rev. 2.00 Mar. 15, 2006 Page 667 of 754 REJ09B0199-0200 Section 20 List of Registers Access Cycles (Read/Write) 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P Register Name Timer status register_6 Timer counter _6 Timer general register A_6 Timer general register B_6 Timer general register C_6 Timer general register D_6 Timer control register_7 Timer mode register_7 Timer I/O control register_7 Timer interrupt enable register_7 Timer status register_7 Timer counter_7 Timer general register A_7 Timer general register B_7 Timer control register_8 Timer mode register_8 Timer I/O control register_8 Timer interrupt enable register_8 Timer status register_8 Timer counter_8 Timer general register A_8 Timer general register B_8 Timer control register_9 Timer mode register_9 Timer I/O control register H_9 Timer I/O control register L_9 Timer interrupt enable register_9 Timer status register_9 Timer counter_9 Timer general register A_9 Timer general register B_9 Timer general register C_9 Timer general register D_9 Abbr. TSR_6 TCNT_6 TGRA_6 TGRB_6 TGRC_6 TGRD_6 TCR_7 TMDR_7 TIOR_7 TIER_7 TSR_7 TCNT_7 TGRA_7 TGRB_7 TCR_8 TMDR_8 TIOR_8 TIER_8 TSR_8 TCNT_8 TGRA_8 TGRB_8 TCR_9 TMDR_9 TIORH_9 TIORL_9 TIER_9 TSR_9 TCNT_9 TGRA_9 TGRB_9 TGRC_9 TGRD_9 Number of Bits Address* 8 16 16 16 16 16 8 8 8 8 8 16 16 16 8 8 8 8 8 16 16 16 8 8 8 8 8 8 16 16 16 16 16 H'FFB15 H'FFB16 H'FFB18 H'FFB1A H'FFB1C H'FFB1E H'FFB20 H'FFB21 H'FFB22 H'FFB24 H'FFB25 H'FFB26 H'FFB28 H'FFB2A H'FFB30 H'FFB31 H'FFB32 H'FFB34 H'FFB35 H'FFB36 H'FFB38 H'FFB3A H'FFB40 H'FFB41 H'FFB42 H'FFB43 H'FFB44 H'FFB45 H'FFB46 H'FFB48 H'FFB4A H'FFB4C H'FFB4E Module TPU_6 TPU_6 TPU_6 TPU_6 TPU_6 TPU_6 TPU_7 TPU_7 TPU_7 TPU_7 TPU_7 TPU_7 TPU_7 TPU_7 TPU_8 TPU_8 TPU_8 TPU_8 TPU_8 TPU_8 TPU_8 TPU_8 TPU_9 TPU_9 TPU_9 TPU_9 TPU_9 TPU_9 TPU_9 TPU_9 TPU_9 TPU_9 TPU_9 Data Width 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 Rev. 2.00 Mar. 15, 2006 Page 668 of 754 REJ09B0199-0200 Section 20 List of Registers Register Name Timer control register_10 Timer mode register_10 Timer I/O control register_10 Abbr. TCR_10 TMDR_10 TIOR_10 Number of Bits Address* 8 8 8 8 8 16 16 16 8 8 8 8 8 16 16 16 8 8 8 8 8 8 8 8 8 8 8 8 8 H'FFB50 H'FFB51 H'FFB52 H'FFB54 H'FFB55 H'FFB56 H'FFB58 H'FFB5A H'FFB60 H'FFB61 H'FFB62 H'FFB64 H'FFB65 H'FFB66 H'FFB68 H'FFB6A H'FFB80 H'FFB81 H'FFB82 H'FFB85 H'FFB89 H'FFB8A H'FFB8C H'FFB90 H'FFB91 H'FFB92 H'FFB93 H'FFB94 H'FFB95 Module TPU_10 TPU_10 TPU_10 TPU_10 TPU_10 TPU_10 TPU_10 TPU_10 TPU_11 TPU_11 TPU_11 TPU_11 TPU_11 TPU_11 TPU_11 TPU_11 I/O port I/O port I/O port I/O port I/O port I/O port I/O port I/O port I/O port I/O port I/O port I/O port I/O port Data Width 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 8 8 8 8 8 8 8 8 8 8 8 8 8 Access Cycles (Read/Write) 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P Timer interrupt enable register_10 TIER_10 Timer status register_10 Timer counter _10 Timer general register A_10 Timer general register B_10 Timer control register_11 Timer mode register_11 Timer I/O control register_11 TSR_10 TCNT_10 TGRA_10 TGRB_10 TCR_11 TMDR_11 TIOR_11 Timer interrupt enable register_11 TIER_11 Timer status register_11 Timer counter _11 Timer general register A_11 Timer general register B_11 Port 1 data direction register Port 2 data direction register Port 3 data direction register Port 6 data direction register Port A data direction register Port B data direction register Port D data direction register TSR_11 TCNT_11 TGRA_11 TGRB_11 P1DDR P2DDR P3DDR P6DDR PADDR PBDDR PDDDR Port 1 input buffer control register P1ICR Port 2 input buffer control register P2ICR Port 3 input buffer control register P3ICR Port 4 input buffer control register P4ICR Port 5 input buffer control register P5ICR Port 6 input buffer control register P6ICR Rev. 2.00 Mar. 15, 2006 Page 669 of 754 REJ09B0199-0200 Section 20 List of Registers Access Cycles (Read/Write) 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/3P 2P/3P 2P/3P 2P/3P Register Name Abbr. Number of Bits Address* 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 16 H'FFB99 H'FFB9A H'FFB9C H'FFBA0 H'FFBA1 H'FFBA2 H'FFBA3 H'FFBA4 H'FFBA5 H'FFBA6 H'FFBA7 H'FFBA8 H'FFBA9 H'FFBAA H'FFBAB H'FFBAC H'FFBAD H'FFBAE H'FFBAF H'FFBB4 H'FFBB8 H'FFBB9 H'FFBBA H'FFBBB H'FFBBC H'FFBC9 H'FFBCA H'FFBCB H'FFBCE Module I/O port I/O port I/O port I/O port I/O port I/O port I/O port I/O port I/O port I/O port I/O port I/O port I/O port I/O port I/O port I/O port I/O port I/O port I/O port I/O port I/O port I/O port I/O port I/O port I/O port I/O port I/O port I/O port INTC Data Width 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Port A input buffer control register PAICR Port B input buffer control register PBICR Port D input buffer control register PDICR Port H register Port I register Port J register Port K register Port H data register Port I data register Port J data register Port K data register Port H data direction register Port I data direction register Port J data direction register Port K data direction register Port I input buffer control register PORTH PORTI PORTJ PORTK PHDR PIDR PJDR PKDR PHDDR PIDDR PJDDR PKDDR PIICR Port H input buffer control register PHICR Port J input buffer control register PJICR Port K input buffer control register PKICR Port D pull-up MOS control register Port H pull-up MOS control register Port I pull-up MOS control register Port J pull-up MOS control register Port K pull-up MOS control register Port 2 open drain control register Port function control register 9 Port function control register A Port function control register B Software standby release IRQ enable register PDPCR PHPCR PIPCR PJPCR PKPCR P2ODR PFCR9 PFCRA PFCRB SSIER Rev. 2.00 Mar. 15, 2006 Page 670 of 754 REJ09B0199-0200 Section 20 List of Registers Register Name DMA source address register_0 DMA destination address register_0 DMA offset register_0 DMA transfer count register_0 DMA block size register_0 DMA mode control register_0 DMA address control register_0 DMA source address register_1 DMA destination address register_1 DMA offset register_1 DMA transfer count register_1 DMA block size register_1 DMA mode control register_1 DMA address control register_1 DMA source address register_2 DMA destination address register_2 DMA offset register_2 DMA transfer count register_2 DMA block size register_2 DMA mode control register_2 DMA address control register_2 DMA source address register_3 DMA destination address register_3 DMA offset register_3 DMA transfer count register_3 DMA block size register_3 DMA mode control register_3 DMA address control register_3 Abbr. DSAR_0 DDAR_0 DOFR_0 DTCR_0 DBSR_0 DMDR_0 DACR_0 DSAR_1 DDAR_1 DOFR_1 DTCR_1 DBSR_1 DMDR_1 DACR_1 DSAR_2 DDAR_2 DOFR_2 DTCR_2 DBSR_2 DMDR_2 DACR_2 DSAR_3 DDAR_3 DOFR_3 DTCR_3 DBSR_3 DMDR_3 DACR_3 Number of Bits Address* 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 H'FFC00 H'FFC04 H'FFC08 H'FFC0C H'FFC10 H'FFC14 H'FFC18 H'FFC20 H'FFC24 H'FFC28 H'FFC2C H'FFC30 H'FFC34 H'FFC38 H'FFC40 H'FFC44 H'FFC48 H'FFC4C H'FFC50 H'FFC54 H'FFC58 H'FFC60 H'FFC64 H'FFC68 H'FFC6C H'FFC70 H'FFC74 H'FFC78 Module DMAC_0 DMAC_0 DMAC_0 DMAC_0 DMAC_0 DMAC_0 DMAC_0 DMAC_1 DMAC_1 DMAC_1 DMAC_1 DMAC_1 DMAC_1 DMAC_1 DMAC_2 DMAC_2 DMAC_2 DMAC_2 DMAC_2 DMAC_2 DMAC_2 DMAC_3 DMAC_3 DMAC_3 DMAC_3 DMAC_3 DMAC_3 DMAC_3 Data Width 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 Access Cycles (Read/Write) 2I/2I 2I/2I 2I/2I 2I/2I 2I/2I 2I/2I 2I/2I 2I/2I 2I/2I 2I/2I 2I/2I 2I/2I 2I/2I 2I/2I 2I/2I 2I/2I 2I/2I 2I/2I 2I/2I 2I/2I 2I/2I 2I/2I 2I/2I 2I/2I 2I/2I 2I/2I 2I/2I 2I/2I Rev. 2.00 Mar. 15, 2006 Page 671 of 754 REJ09B0199-0200 Section 20 List of Registers Register Name DMA module request select register_0 DMA module request select register_1 DMA module request select register_2 DMA module request select register_3 Interrupt priority register A Interrupt priority register B Interrupt priority register C Interrupt priority register D Interrupt priority register E Interrupt priority register F Interrupt priority register G Interrupt priority register I Interrupt priority register K Interrupt priority register L Interrupt priority register M Interrupt priority register N Interrupt priority register O Interrupt priority register Q Interrupt priority register R IRQ sense control register H IRQ sense control register L DTC vector base register Bus control register 2 RAM emulation register Mode control register System control register System clock control register Standby control register Abbr. DMRSR_0 DMRSR_1 DMRSR_2 DMRSR_3 IPRA IPRB IPRC IPRD IPRE IPRF IPRG IPRI IPRK IPRL IPRM IPRN IPRO IPRQ IPRR ISCRH ISCRL DTCVBR BCR2 RAMER MDCR SYSCR SCKCR SBYCR Number of Bits Address* 8 8 8 8 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 32 8 8 16 16 16 16 H'FFD20 H'FFD21 H'FFD22 H'FFD23 H'FFD40 H'FFD42 H'FFD44 H'FFD46 H'FFD48 H'FFD4A H'FFD4C H'FFD50 H'FFD54 H'FFD56 H'FFD58 H'FFD5A H'FFD5C H'FFD60 H'FFD62 H'FFD68 H'FFD6A H'FFD80 H'FFD94 H'FFD9E H'FFDC0 H'FFDC2 H'FFDC4 H'FFDC6 Module DMAC_0 DMAC_1 DMAC_2 DMAC_3 INTC INTC INTC INTC INTC INTC INTC INTC INTC INTC INTC INTC INTC INTC INTC INTC INTC BSC BSC BSC SYSTEM SYSTEM SYSTEM SYSTEM Data Width 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 Access Cycles (Read/Write) 2I/2I 2I/2I 2I/2I 2I/2I 2I/3I 2I/3I 2I/3I 2I/3I 2I/3I 2I/3I 2I/3I 2I/3I 2I/3I 2I/3I 2I/3I 2I/3I 2I/3I 2I/3I 2I/3I 2I/3I 2I/3I 2I/3I 2I/3I 2I/3I 2I/3I 2I/3I 2I/3I 2I/3I Rev. 2.00 Mar. 15, 2006 Page 672 of 754 REJ09B0199-0200 Section 20 List of Registers Register Name Module stop control register A Module stop control register B Module stop control register C Serial mode register_3 Bit rate register_3 Serial control register_3 Transmit data register_3 Serial status register_3 Receive data register_3 Smart card mode register_3 Serial mode register_4 Bit rate register_4 Serial control register_4 Transmit data register_4 Serial status register_4 Receive data register_4 Smart card mode register_4 Flash code control/status register Abbr. MSTPCRA MSTPCRB MSTPCRC SMR_3 BRR_3 SCR_3 TDR_3 SSR_3 RDR_3 SCMR_3 SMR_4 BRR_4 SCR_4 TDR_4 SSR_4 RDR_4 SCMR_4 FCCS Number of Bits Address* 16 16 16 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 16 16 16 H'FFDC8 H'FFDCA H'FFDCC H'FFE88 H'FFE89 H'FFE8A H'FFE8B H'FFE8C H'FFE8D H'FFE8E H'FFE90 H'FFE91 H'FFE92 H'FFE93 H'FFE94 H'FFE95 H'FFE96 H'FFEA8 H'FFEA9 H'FFEAA H'FFEAC H'FFEAD H'FFEAE H'FFEE0 H'FFEE1 H'FFEE2 H'FFEE4 H'FFEE5 H'FFEE6 H'FFEE8 H'FFEEA Module SYSTEM SYSTEM SYSTEM SCI_3 SCI_3 SCI_3 SCI_3 SCI_3 SCI_3 SCI_3 SCI_4 SCI_4 SCI_4 SCI_4 SCI_4 SCI_4 SCI_4 FLASH FLASH FLASH FLASH FLASH FLASH TPU_4 TPU_4 TPU_4 TPU_4 TPU_4 TPU_4 TPU_4 TPU_4 Data Width 16 16 16 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 16 16 16 16 16 16 16 16 Access Cycles (Read/Write) 2I/3I 2I/3I 2I/3I 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P Flash program code select register FPCS Flash erase code select register Flash key code register Flash MAT select register Flash transfer destination address register Timer control register_4 Timer mode register_4 Timer I/O control register_4 Timer interrupt enable register_4 Timer status register_4 Timer counter_4 Timer general register A_4 Timer general register B_4 FECS FKEY FMATS FTDAR TCR_4 TMDR_4 TIOR_4 TIER_4 TSR_4 TCNT_4 TGRA_4 TGRB_4 Rev. 2.00 Mar. 15, 2006 Page 673 of 754 REJ09B0199-0200 Section 20 List of Registers Register Name Timer control register_5 Timer mode register_5 Timer I/O control register_5 Timer interrupt enable register_5 Timer status register_5 Timer counter_5 Timer general register A_5 Timer general register B_5 DTC enable register A DTC enable register B DTC enable register C DTC enable register D DTC enable register E DTC enable register F DTC enable register G DTC enable register H DTC control register Interrupt control register CPU priority control register IRQ enable register IRQ status register Port 1 register Port 2 register Port 3 register Port 4 register Port 5 register Port 6 register Port A register Port B register Port D register Abbr. TCR_5 TMDR_5 TIOR_5 TIER_5 TSR_5 TCNT_5 TGRA_5 TGRB_5 DTCERA DTCERB DTCERC DTCERD DTCERE DTCERF DTCERG DTCERH DTCCR INTCR CPUPCR IER ISR PORT1 PORT2 PORT3 PORT4 PORT5 PORT6 PORTA PORTB PORTD Number of Bits Address* 8 8 8 8 8 16 16 16 16 16 16 16 16 16 16 16 8 8 8 16 16 8 8 8 8 8 8 8 8 8 H'FFEF0 H'FFEF1 H'FFEF2 H'FFEF4 H'FFEF5 H'FFEF6 H'FFEF8 H'FFEFA H'FFF20 H'FFF22 H'FFF24 H'FFF26 H'FFF28 H'FFF2A H'FFF2C H'FFF2E H'FFF30 H'FFF32 H'FFF33 H'FFF34 H'FFF36 H'FFF40 H'FFF41 H'FFF42 H'FFF43 H'FFF44 H'FFF45 H'FFF49 H'FFF4A H'FFF4C Module TPU_5 TPU_5 TPU_5 TPU_5 TPU_5 TPU_5 TPU_5 TPU_5 DTC DTC DTC DTC DTC DTC DTC DTC DTC INTC INTC INTC INTC I/O port I/O port I/O port I/O port I/O port I/O port I/O port I/O port I/O port Data Width 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 8 8 8 8 8 8 8 8 8 Access Cycles (Read/Write) 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2I/3I 2I/3I 2I/3I 2I/3I 2I/3I 2I/3I 2I/3I 2I/3I 2I/3I 2I/3I 2I/3I 2I/3I 2I/3I 2P/-- 2P/-- 2P/-- 2P/-- 2P/-- 2P/-- 2P/-- 2P/-- 2P/-- Rev. 2.00 Mar. 15, 2006 Page 674 of 754 REJ09B0199-0200 Section 20 List of Registers Register Name Port 1 data register Port 2 data register Port 3 data register Port 6 data register Port A data register Port B data register Port D data register PPG output control register PPG output mode register Next data enable register H Next data enable register L Output data register H Output data register L Next data register H Next data register L Next data register H Next data register L A/D data register A_0 A/D data register B_0 A/D data register C_0 A/D data register D_0 A/D data register E_0 A/D data register F_0 A/D data register G_0 A/D data register H_0 A/D control/status register_0 A/D control register_0 Abbr. P1DR P2DR P3DR P6DR PADR PBDR PDDR PCR PMR NDERH NDERL PODRH PODRL NDRH NDRL NDRH NDRL ADDRA_0 ADDRB_0 ADDRC_0 ADDRD_0 ADDRE_0 ADDRF_0 ADDRG_0 ADDRH_0 ADCSR_0 ADCR_0 Number of Bits Address* 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 16 16 16 16 16 16 16 16 8 8 H'FFF50 H'FFF51 H'FFF52 H'FFF55 H'FFF59 H'FFF5A H'FFF5C H'FFF76 H'FFF77 H'FFF78 H'FFF79 H'FFF7A H'FFF7B H'FFF7C H'FFF7D H'FFF7E H'FFF7F H'FFF90 H'FFF92 H'FFF94 H'FFF96 H'FFF98 H'FFF9A H'FFF9C H'FFF9E H'FFFA0 H'FFFA1 Module I/O port I/O port I/O port I/O port I/O port I/O port I/O port PPG PPG PPG PPG PPG PPG PPG PPG PPG PPG A/D_0 A/D_0 A/D_0 A/D_0 A/D_0 A/D_0 A/D_0 A/D_0 A/D_0 A/D_0 Data Width 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 16 16 16 16 16 16 16 16 16 16 Access Cycles (Read/Write) 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P Rev. 2.00 Mar. 15, 2006 Page 675 of 754 REJ09B0199-0200 Section 20 List of Registers Register Name Timer control/status register Timer counter Reset control/status register Timer start register Timer synchronous register Timer control register_0 Timer mode register_0 Timer I/O control register H_0 Timer I/O control register L_0 Timer interrupt enable register_0 Timer status register_0 Timer counter_0 Timer general register A_0 Timer general register B_0 Timer general register C_0 Timer general register D_0 Timer control register_1 Timer mode register_1 Timer I/control register_1 Timer interrupt enable register_1 Timer status register_1 Timer counter_1 Timer general register A_1 Timer general register B_1 Timer control register_2 Timer mode register_2 Timer I/O control register_2 Timer interrupt enable register_2 Timer status register_2 Timer counter_2 Timer general register A_2 Timer general register B_2 Abbr. TCSR TCNT RSTCSR TSTR TSYR TCR_0 TMDR_0 TIORH_0 TIORL_0 TIER_0 TSR_0 TCNT_0 TGRA_0 TGRB_0 TGRC_0 TGRD_0 TCR_1 TMDR_1 TIOR_1 TIER_1 TSR_1 TCNT_1 TGRA_1 TGRB_1 TCR_2 TMDR_2 TIOR_2 TIER_2 TSR_2 TCNT_2 TGRA_2 TGRB_2 Number of Bits Address* 8 8 8 8 8 8 8 8 8 8 8 16 16 16 16 16 8 8 8 8 8 16 16 16 8 8 8 8 8 16 16 16 H'FFFA4 H'FFFA5 H'FFFA7 H'FFFBC H'FFFBD H'FFFC0 H'FFFC1 H'FFFC2 H'FFFC3 H'FFFC4 H'FFFC5 H'FFFC6 H'FFFC8 H'FFFCA H'FFFCC H'FFFCE H'FFFD0 H'FFFD1 H'FFFD2 H'FFFD4 H'FFFD5 H'FFFD6 H'FFFD8 H'FFFDA H'FFFE0 H'FFFE1 H'FFFE2 H'FFFE4 H'FFFE5 H'FFFE6 H'FFFE8 H'FFFEA Module WDT WDT WDT TPU TPU TPU_0 TPU_0 TPU_0 TPU_0 TPU_0 TPU_0 TPU_0 TPU_0 TPU_0 TPU_0 TPU_0 TPU_1 TPU_1 TPU_1 TPU_1 TPU_1 TPU_1 TPU_1 TPU_1 TPU_2 TPU_2 TPU_2 TPU_2 TPU_2 TPU_2 TPU_2 TPU_2 Data Width Access Cycles (Read/Write) 2P/3P 2P/3P 2P/3P 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P Rev. 2.00 Mar. 15, 2006 Page 676 of 754 REJ09B0199-0200 Section 20 List of Registers Register Name Timer control register_3 Timer mode register_3 Timer I/O control register H_3 Timer I/O control register L_3 Timer interrupt enable register_3 Timer status register_3 Timer counter_3 Timer general register A_3 Timer general register B_3 Timer general register C_3 Timer general register D_3 Abbr. TCR_3 TMDR_3 TIORH_3 TIORL_3 TIER_3 TSR_3 TCNT_3 TGRA_3 TGRB_3 TGRC_3 TGRD_3 Number of Bits Address* 8 8 8 8 8 8 16 16 16 16 16 H'FFFF0 H'FFFF1 H'FFFF2 H'FFFF3 H'FFFF4 H'FFFF5 H'FFFF6 H'FFFF8 H'FFFFA H'FFFFC H'FFFFE Module TPU_3 TPU_3 TPU_3 TPU_3 TPU_3 TPU_3 TPU_3 TPU_3 TPU_3 TPU_3 TPU_3 Data Width 16 16 16 16 16 16 16 16 16 16 16 Access Cycles (Read/Write) 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P Note: * The lower 20 bits are indicated. Rev. 2.00 Mar. 15, 2006 Page 677 of 754 REJ09B0199-0200 Section 20 List of Registers 20.2 Register Bits Register addresses and bit names of the on-chip peripheral modules are described below. Each line covers eight bits, and 16-bit and 32-bit registers are shown as 2 or 4 lines, respectively. Register Abbreviation SSCRH_0 SSCRL_0 SSMR_0 SSER_0 SSSR_0 SSCR2_0 SSTDR0_0 SSTDR1_0 SSTDR2_0 SSTDR3_0 SSRDR0_0 SSRDR1_0 SSRDR2_0 SSRDR3_0 SSCRH_1 SSCRL_1 SSMR_1 SSER_1 SSSR_1 SSCR2_1 SSTDR0_1 SSTDR1_1 SSTDR2_1 SSTDR3_1 SSRDR0_1 SSRDR1_1 SSRDR2_1 SSRDR3_1 MSS MLS TE SDOS BIDE SSUMS CPOS RE ORER SSCKOS SRES CPHS SCSOS SOL SOLP TEIE TEND SCKS CKS2 TIE TDRE SSODTS CSS1 DATS1 CKS1 RIE RDRF CSS0 DATS0 CKS0 CEIE CE SSU_1 Bit Bit Bit SRES CPHS SCSOS Bit Bit Bit Bit Bit 24/16/8/0 CSS0 DATS0 CKS0 CEIE CE Module SSU_0 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 MSS MLS TE SDOS BIDE SSUMS CPOS RE ORER SSCKOS SOL SOLP TEIE TEND SCKS CKS2 TIE TDRE SSODTS CSS1 DATS1 CKS1 RIE RDRF TENDSTS SCSATS TENDSTS SCSATS Rev. 2.00 Mar. 15, 2006 Page 678 of 754 REJ09B0199-0200 Section 20 List of Registers Register Abbreviation SSCRH_2 SSCRL_2 SSMR_2 SSER_2 SSSR_2 SSCR2_2 SSTDR0_2 SSTDR1_2 SSTDR2_2 SSTDR3_2 SSRDR0_2 SSRDR1_2 SSRDR2_2 SSRDR3_2 PHRTIDR APPDCR Bit Bit Bit Bit Bit Bit Bit Bit 24/16/8/0 CSS0 DATS0 CKS0 CEIE CE Module SSU_2 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 MSS MLS TE SDOS BIDE SSUMS CPOS RE ORER SSCKOS SRES CPHS SCSOS SOL SOLP TEIE TEND SCKS CKS2 TIE TDRE SSODTS CSS1 DATS1 CKS1 RIE RDRF TENDSTS SCSATS PHRTIDR7 PHRTIDR6 PHRTIDR5 PHRTIDR4 PHRTIDR3 PHRTIDR2 PHRTIDR1 PHRTIDR0 I/O port AN15PD AN7PD AN14PD AN6PD AN13PD AN5PD AN12PD AN4PD AN11PD AN3PD AN10PD AN2PD AN9PD AN1PD AN8PD AN0PD A/D_1 A/D ADDRA_1 ADDRB_1 ADDRC_1 ADDRD_1 ADDRE_1 ADDRF_1 ADDRG_1 ADDRH_1 ADCSR_1 ADCR_1 ADF TRGS1 ADIE TRGS0 ADST SCANE SCANS CH3 CKS1 CH2 CKS0 CH1 CH0 Rev. 2.00 Mar. 15, 2006 Page 679 of 754 REJ09B0199-0200 Section 20 List of Registers Register Abbreviation TSTRB TSYRB TCR_6 TMDR_6 TIORH_6 TIORL_6 TIER_6 TSR_6 TCNT_6 Bit Bit Bit Bit Bit Bit Bit Bit 24/16/8/0 CST0 SYNC0 TPSC0 MD0 IOA0 IOC0 TGIEA TGFA TPU_6 Module TPU 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 CCLR2 IOB3 IOD3 CCLR1 IOB2 IOD2 CST5 SYNC5 CCLR0 BFB IOB1 IOD1 TCIEU CST4 SYNC4 CKEG1 BFA IOB0 IOD0 TCIEV TCFV CST3 SYNC3 CKEG0 MD3 IOA3 IOC3 TGIED TGFD CST2 SYNC2 TPSC2 MD2 IOA2 IOC2 TGIEC TGFC CST1 SYNC1 TPSC1 MD1 IOA1 IOC1 TGIEB TGFB TGRA_6 TGRB_6 TGRC_6 TGRD_6 TCR_7 TMDR_7 TIOR_7 TIER_7 TSR_7 TCNT_7 IOB3 TCFD CCLR1 IOB2 CCLR0 IOB1 TCIEU TCFU CKEG1 IOB0 TCIEV TCFV CKEG0 IOA3 TPSC2 MD2 IOA2 TPSC1 MD1 IOA1 TGIEB TGFB TPSC0 MD0 IOA0 TGIEA TGFA TPU_7 TGRA_7 TGRB_7 Rev. 2.00 Mar. 15, 2006 Page 680 of 754 REJ09B0199-0200 Section 20 List of Registers Register Abbreviation TCR_8 TMDR_8 TIOR_8 TIER_8 TSR_8 TCNT_8 Bit IOB3 TCFD Bit Bit Bit Bit Bit Bit Bit 24/16/8/0 TPSC0 MD0 IOA0 TGIEA TGFA Module TPU_8 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 CCLR1 IOB2 CCLR0 IOB1 TCIEU TCFU CKEG1 IOB0 TCIEV TCFV CKEG0 IOA3 TPSC2 MD2 IOA2 TPSC1 MD1 IOA1 TGIEB TGFB TGRA_8 TGRB_8 TCR_9 TMDR_9 TIORH_9 TIORL_9 TIER_9 TSR_9 TCNT_9 CCLR2 IOB3 IOD3 CCLR1 IOB2 IOD2 CCLR0 BFB IOB1 IOD1 CKEG1 BFA IOB0 IOD0 TCIEV TCFV CKEG0 IOA3 IOC3 TGIED TGFD TPSC2 MD2 IOA2 IOC2 TGIEC TGFC TPSC1 MD1 IOA1 IOC1 TGIEB TGFB TPSC0 MD0 IOA0 IOC0 TGIEA TGFA TPU_9 TGRA_9 TGRB_9 TGRC_9 TGRD_9 TCR_10 TMDR_10 TIOR_10 TIER_10 TSR_10 IOB3 TCFD CCLR1 IOB2 CCLR0 IOB1 TCIEU TCFU CKEG1 IOB0 TCIEV TCFV CKEG0 IOA3 TPSC2 MD2 IOA2 TPSC1 MD1 IOA1 TGIEB TGFB TPSC0 MD0 IOA0 TGIEA TGFA TPU_10 Rev. 2.00 Mar. 15, 2006 Page 681 of 754 REJ09B0199-0200 Section 20 List of Registers Register Abbreviation TCNT_10 Bit Bit Bit Bit Bit Bit Bit Bit 24/16/8/0 Module TPU_10 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 TGRA_10 TGRB_10 TCR_11 TMDR_11 TIOR_11 TIER_11 TSR_11 TCNT_11 TGRA_11 IOB3 TCFD CCLR1 IOB2 CCLR0 IOB1 TCIEU TCFU CKEG1 IOB0 TCIEV TCFV CKEG0 IOA3 TPSC2 MD2 IOA2 TPSC1 MD1 IOA1 TGIEB TGFB TPSC0 MD0 IOA0 TGIEA TGFA TPU_11 TGRB_11 P1DDR P2DDR P3DDR P6DDR PADDR PBDDR PDDDR P1ICR P2ICR P3ICR P4ICR P5ICR P6ICR P17DDR P27DDR P37DDR PA7DDR PD7DDR P17ICR P27ICR P37ICR P47ICR P57ICR P67ICR P16DDR P26DDR P36DDR P66DDR PA6DDR PD6DDR P16ICR P26ICR P36ICR P46ICR P56ICR P66ICR P15DDR P25DDR P35DDR P65DDR PA5DDR PD5DDR P15ICR P25ICR P35ICR P45ICR P55ICR P65ICR P14DDR P24DDR P34DDR P64DDR PA4DDR PD4DDR P14ICR P24ICR P34ICR P44ICR P54ICR P64ICR P13DDR P23DDR P33DDR P63DDR PA3DDR PD3DDR P13ICR P23ICR P33ICR P43ICR P53ICR P63ICR P12DDR P22DDR P32DDR P62DDR PA2DDR PB2DDR PD2DDR P12ICR P22ICR P32ICR P42ICR P52ICR P62ICR P11DDR P21DDR P31DDR P61DDR PA1DDR PB1DDR PD1DDR P11ICR P21ICR P31ICR P41ICR P51ICR P61ICR P10DDR P20DDR P30DDR P60DDR PA0DDR PB0DDR PD0DDR P10ICR P20ICR P30ICR P40ICR P50ICR P60ICR I/O port Rev. 2.00 Mar. 15, 2006 Page 682 of 754 REJ09B0199-0200 Section 20 List of Registers Register Abbreviation PAICR PBICR PDICR PORTH PORTI PORTJ PORTK PHDR PIDR PJDR PKDR PHDDR PIDDR PJDDR PKDDR PHICR PIICR PJICR PKICR PDPCR PHPCR PIPCR PJPCR PKPCR P2ODR PFCR9 PFCRA PFCRB SSIER Bit Bit Bit Bit Bit Bit Bit Bit 24/16/8/0 PA0ICR PB0ICR PD0ICR PH0 PI0 PJ0 PK0 PH0DR PI0DR PJ0DR PK0DR PH0DDR PI0DDR PJ0DDR PK0DDR PH0ICR PI0ICR PJ0ICR PK0ICR PD0PCR PH0PCR PI0PCR PJ0PCR PK0PCR P20ODR Module I/O port 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 PA7ICR PD7ICR PH7 PI7 PJ7 PK7 PH7DR PI7DR PJ7DR PK7DR PH7DDR PI7DDR PJ7DDR PK7DDR PH7ICR PI7ICR PJ7ICR PK7ICR PD7PCR PH7PCR PI7PCR PJ7PCR PK7PCR P27ODR TPUMS5 PA6ICR PD6ICR PH6 PI6 PJ6 PK6 PH6DR PI6DR PJ6DR PK6DR PH6DDR PI6DDR PJ6DDR PK6DDR PH6ICR PI6ICR PJ6ICR PK6ICR PD6PCR PH6PCR PI6PCR PJ6PCR PK6PCR P26ODR TPUMS4 PA5ICR PD5ICR PH5 PI5 PJ5 PK5 PH5DR PI5DR PJ5DR PK5DR PH5DDR PI5DDR PJ5DDR PK5DDR PH5ICR PI5ICR PJ5ICR PK5ICR PD5PCR PH5PCR PI5PCR PJ5PCR PK5PCR P25ODR PA4ICR PD4ICR PH4 PI4 PJ4 PK4 PH4DR PI4DR PJ4DR PK4DR PH4DDR PI4DDR PJ4DDR PK4DDR PH4ICR PI4ICR PJ4ICR PK4ICR PD4PCR PH4PCR PI4PCR PJ4PCR PK4PCR P24ODR PA3ICR PD3ICR PH3 PI3 PJ3 PK3 PH3DR PI3DR PJ3DR PK3DR PH3DDR PI3DDR PJ3DDR PK3DDR PH3ICR PI3ICR PJ3ICR PK3ICR PD3PCR PH3PCR PI3PCR PJ3PCR PK3PCR P23ODR PA2ICR PB2ICR PD2ICR PH2 PI2 PJ2 PK2 PH2DR PI2DR PJ2DR PK2DR PH2DDR PI2DDR PJ2DDR PK2DDR PH2ICR PI2ICR PJ2ICR PK2ICR PD2PCR PH2PCR PI2PCR PJ2PCR PK2PCR P22ODR TPUMS1 TPUMS7 ITS10 SSI10 SSI2 PA1ICR PB1ICR PD1ICR PH1 PI1 PJ1 PK1 PH1DR PI1DR PJ1DR PK1DR PH1DDR PI1DDR PJ1DDR PK1DDR PH1ICR PI1ICR PJ1ICR PK1ICR PD1PCR PH1PCR PI1PCR PJ1PCR PK1PCR P21ODR TPUMS3A TPUMS3B TPUMS2 TPUMS0A TPUMS0B TPUMS6A TPUMS6B ITS9 SSI9 SSI1 ITS8 SSI8 SSI0 INTC TPUMS11 TPUMS10 TPUMS9A TPUMS9B TPUMS8 ITS15 SSI15 SSI7 ITS14 SSI14 SSI6 ITS13 SSI13 SSI5 ITS12 SSI12 SSI4 ITS11 SSI11 SSI3 Rev. 2.00 Mar. 15, 2006 Page 683 of 754 REJ09B0199-0200 Section 20 List of Registers Register Abbreviation DSAR_0 Bit Bit Bit Bit Bit Bit Bit Bit 24/16/8/0 Module DMAC_0 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 DDAR_0 DOFR_0 DTCR_0 DBSR_0 BKSZH31 BKSZH30 BKSZH29 BKSZH28 BKSZH27 BKSZH26 BKSZH25 BKSZH24 BKSZH23 BKSZH22 BKSZH21 BKSZH20 BKSZH19 BKSZH18 BKSZH17 BKSZH16 BKSZ15 BKSZ7 BKSZ14 BKSZ6 DACKE DTSZ0 DTF0 DIRS BKSZ13 BKSZ5 TENDE MDS1 DTA SAT1 BKSZ12 BKSZ4 MDS0 SAT0 SARA4 DARA4 BKSZ11 BKSZ3 DREQS ERRF TSEIE SARA3 DARA3 BKSZ10 BKSZ2 NRD DMAP2 RPTIE SARA2 DARA2 BKSZ9 BKSZ1 ESIF ESIE DMAP1 ARS1 DAT1 SARA1 DARA1 BKSZ8 BKSZ0 DTIF DTIE DMAP0 ARS0 DAT0 SARA0 DARA0 DMDR_0 DTE ACT DTSZ1 DTF1 DACR_0 AMS SARIE DARIE Rev. 2.00 Mar. 15, 2006 Page 684 of 754 REJ09B0199-0200 Section 20 List of Registers Register Abbreviation DSAR_1 Bit Bit Bit Bit Bit Bit Bit Bit 24/16/8/0 Module DMAC_1 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 DDAR_1 DOFR_1 DTCR_1 DBSR_1 BKSZH31 BKSZH30 BKSZH29 BKSZH28 BKSZH27 BKSZH26 BKSZH25 BKSZH24 BKSZH23 BKSZH22 BKSZH21 BKSZH20 BKSZH19 BKSZH18 BKSZH17 BKSZH16 BKSZ15 BKSZ7 BKSZ14 BKSZ6 DACKE DTSZ0 DTF0 DIRS BKSZ13 BKSZ5 TENDE MDS1 DTA SAT1 BKSZ12 BKSZ4 MDS0 SAT0 SARA4 DARA4 BKSZ11 BKSZ3 DREQS TSEIE SARA3 DARA3 BKSZ10 BKSZ2 NRD DMAP2 RPTIE SARA2 DARA2 BKSZ9 BKSZ1 ESIF ESIE DMAP1 ARS1 DAT1 SARA1 DARA1 BKSZ8 BKSZ0 DTIF DTIE DMAP0 ARS0 DAT0 SARA0 DARA0 DMDR_1 DTE ACT DTSZ1 DTF1 DACR_1 AMS SARIE DARIE Rev. 2.00 Mar. 15, 2006 Page 685 of 754 REJ09B0199-0200 Section 20 List of Registers Register Abbreviation DSAR_2 Bit Bit Bit Bit Bit Bit Bit Bit 24/16/8/0 Module DMAC_2 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 DDAR_2 DOFR_2 DTCR_2 DBSR_2 BKSZH31 BKSZH30 BKSZH29 BKSZH28 BKSZH27 BKSZH26 BKSZH25 BKSZH24 BKSZH23 BKSZH22 BKSZH21 BKSZH20 BKSZH19 BKSZH18 BKSZH17 BKSZH16 BKSZ15 BKSZ7 BKSZ14 BKSZ6 DACKE DTSZ0 DTF0 DIRS BKSZ13 BKSZ5 TENDE MDS1 DTA SAT1 BKSZ12 BKSZ4 MDS0 SAT0 SARA4 DARA4 BKSZ11 BKSZ3 DREQS TSEIE SARA3 DARA3 BKSZ10 BKSZ2 NRD DMAP2 RPTIE SARA2 DARA2 BKSZ9 BKSZ1 ESIF ESIE DMAP1 ARS1 DAT1 SARA1 DARA1 BKSZ8 BKSZ0 DTIF DTIE DMAP0 ARS0 DAT0 SARA0 DARA0 DMDR_2 DTE ACT DTSZ1 DTF1 DACR_2 AMS SARIE DARIE Rev. 2.00 Mar. 15, 2006 Page 686 of 754 REJ09B0199-0200 Section 20 List of Registers Register Abbreviation DSAR_3 Bit Bit Bit Bit Bit Bit Bit Bit 24/16/8/0 Module DMAC_3 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 DDAR_3 DOFR_3 DTCR_3 DBSR_3 BKSZH31 BKSZH30 BKSZH29 BKSZH28 BKSZH27 BKSZH26 BKSZH25 BKSZH24 BKSZH23 BKSZH22 BKSZH21 BKSZH20 BKSZH19 BKSZH18 BKSZH17 BKSZH16 BKSZ15 BKSZ7 BKSZ14 BKSZ6 DACKE DTSZ0 DTF0 DIRS BKSZ13 BKSZ5 TENDE MDS1 DTA SAT1 BKSZ12 BKSZ4 MDS0 SAT0 SARA4 DARA4 BKSZ11 BKSZ3 DREQS TSEIE SARA3 DARA3 BKSZ10 BKSZ2 NRD DMAP2 RPTIE SARA2 DARA2 BKSZ9 BKSZ1 ESIF ESIE DMAP1 ARS1 DAT1 SARA1 DARA1 BKSZ8 BKSZ0 DTIF DTIE DMAP0 ARS0 DAT0 SARA0 DARA0 DMAC_0 DMAC_1 DMAC_2 DMAC_3 DMDR_3 DTE ACT DTSZ1 DTF1 DACR_3 AMS SARIE DARIE DMRSR_0 DMRSR_1 DMRSR_2 DMRSR_3 Rev. 2.00 Mar. 15, 2006 Page 687 of 754 REJ09B0199-0200 Section 20 List of Registers Register Abbreviation IPRA Bit Bit Bit Bit Bit Bit Bit Bit 24/16/8/0 IPRA8 IPRA0 IPRB8 IPRB0 IPRC8 IPRC0 IPRD8 IPRE8 IPRF8 IPRF0 IPRG8 IPRG0 IPRI8 IPRI0 IPRL8 IPRL0 IPRM8 IPRM0 IPRN8 IPRN0 IPRO8 IPRQ0 IPRR8 IPRR0 Module INTC 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 IPRA14 IPRA6 IPRB14 IPRB6 IPRC14 IPRC6 IPRD14 IPRD6 IPRF6 IPRG14 IPRG6 IPRI14 IPRI6 IPRK14 IPRL6 IPRM14 IPRM6 IPRN14 IPRN6 IPRO14 IPRO6 IPRR14 IPRR6 IPRA13 IPRA5 IPRB13 IPRB5 IPRC13 IPRC5 IPRD13 IPRD5 IPRF5 IPRG13 IPRG5 IPRI13 IPRI5 IPRK13 IPRL5 IPRM13 IPRM5 IPRN13 IPRN5 IPRO13 IPRO5 IPRR13 IPRR5 IPRA12 IPRA4 IPRB12 IPRB4 IPRC12 IPRC4 IPRD12 IPRD4 IPRF4 IPRG12 IPRG4 IPRI12 IPRI4 IPRK12 IPRL4 IPRM12 IPRM4 IPRN12 IPRN4 IPRO12 IPRO4 IPRR12 IPRR4 IPRA10 IPRA2 IPRB10 IPRB2 IPRC10 IPRC2 IPRD10 IPRE10 IPRF10 IPRF2 IPRG10 IPRG2 IPRI10 IPRI2 IPRL10 IPRL2 IPRM10 IPRM2 IPRN10 IPRN2 IPRO10 IPRQ2 IPRR10 IPRR2 IPRA9 IPRA1 IPRB9 IPRB1 IPRC9 IPRC1 IPRD9 IPRE9 IPRF9 IPRF1 IPRG9 IPRG1 IPRI9 IPRI1 IPRL9 IPRL1 IPRM9 IPRM1 IPRN9 IPRN1 IPRO9 IPRQ1 IPRR9 IPRR1 IPRB IPRC IPRD IPRE IPRF IPRG IPRI IPRK IPRL IPRM IPRN IPRO IPRQ IPRR Rev. 2.00 Mar. 15, 2006 Page 688 of 754 REJ09B0199-0200 Section 20 List of Registers Register Abbreviation ISCRH Bit Bit Bit Bit Bit Bit Bit Bit 24/16/8/0 IRQ12SF IRQ8SF IRQ4SF IRQ0SF BSC Module INTC 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 IRQ15SR IRQ11SR IRQ15SF IRQ11SF IRQ7SF IRQ3SF IRQ14SR IRQ10SR IRQ6SR IRQ2SR IRQ14SF IRQ10SF IRQ6SF IRQ2SF IRQ13SR IRQ9SR IRQ5SR IRQ1SR IRQ13SF IRQ9SF IRQ5SF IRQ1SF IRQ12SR IRQ8SR IRQ4SR IRQ0SR ISCRL IRQ7SR IRQ3SR DTCVBR BCR2 RAMER MDCR PCK2 MACS POSEL1 PCK1 IBCCS PCK0 STS4 RAMS MDS3 STS3 RAM2 MDS2 ICK2 BCK2 STS2 RAM1 MDS1 DTCMD ICK1 BCK1 STS1 PWDBE RAM0 MDS0 RAME ICK0 BCK0 STS0 MSTPA8 MSTPA0 MSTPB8 MSTPB0 MSTPC8 MSTPC0 CKS0 SCI_3 SYSTEM SYSCR FLSHE SCKCR PSTOP1 SBYCR SSBY MSTPCRA ACSE MSTPA7 MSTPA14 MSTPA13 MSTPA12 MSTPA11 MSTPA10 MSTPA9 MSTPA6 MSTPA5 MSTPA4 MSTPA3 MSTPA2 MSTPA1 MSTPCRB MSTPB15 MSTPB14 MSTPB13 MSTPB12 MSTPB11 MSTPB10 MSTPB9 MSTPB7 MSTPB6 MSTPB5 MSTPB4 MSTPB3 MSTPB2 MSTPB1 MSTPCRC MSTPC15 MSTPC14 MSTPC13 MSTPC12 MSTPC11 MSTPC10 MSTPC9 MSTPC7 MSTPC6 MSTPC5 MSTPC4 O/E MSTPC3 STOP (BCP1) MSTPC2 MP (BCP0) MSTPC1 CKS1 SMR_3* C/A (GM) CHR (BLK) PE BRR_3 SCR_3* TDR_3 SSR_3* RDR_3 SCMR_3 SDIR SINV SMIF TDRE RDRF ORER FER (ERS) PER TEND MPB MPBT TIE RIE TE RE MPIE TEIE CKE1 CKE0 Rev. 2.00 Mar. 15, 2006 Page 689 of 754 REJ09B0199-0200 Section 20 List of Registers Register Abbreviation SMR_4* Bit Bit Bit Bit Bit Bit Bit Bit 24/16/8/0 CKS0 Module SCI_4 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 C/A (GM) CHR (BLK) PE O/E STOP (BCP1) MP (BCP0) CKS1 BRR_4 SCR_4* TDR_4 SSR_4* RDR_4 SCMR_4 FCCS FPCS FECS FKEY FMATS FTDAR TCR_4 TMDR_4 TIOR_4 TIER_4 TSR_4 TCNT_4 K7 MS7 TDER IOB3 TTGE TCFD K6 MS6 TDA6 CCLR1 IOB2 K5 MS5 TDA5 CCLR0 IOB1 TCIEU TCFU FLER K4 MS4 TDA4 CKEG1 IOB0 TCIEV TCFV SDIR K3 MS3 TDA3 CKEG0 IOA3 SINV K2 MS2 TDA2 TPSC2 MD2 IOA2 K1 MS1 TDA1 TPSC1 MD1 IOA1 TGIEB TGFB SMIF SCO PPVS EPVB K0 MS0 TDA0 TPSC0 MD0 IOA0 TGIEA TGFA TPU_4 FLASH TDRE RDRF ORER FER (ERS) PER TEND MPB MPBT TIE RIE TE RE MPIE TEIE CKE1 CKE0 TGRA_4 TGRB_4 TCR_5 TMDR_5 TIOR_5 TIER_5 TSR_5 TCNT_5 IOB3 TTGE TCFD CCLR1 IOB2 CCLR0 IOB1 TCIEU TCFU CKEG1 IOB0 TCIEV TCFV CKEG0 IOA3 TPSC2 MD2 IOA2 TPSC1 MD1 IOA1 TGIEB TGFB TPSC0 MD0 IOA0 TGIEA TGFA TPU_5 Rev. 2.00 Mar. 15, 2006 Page 690 of 754 REJ09B0199-0200 Section 20 List of Registers Register Abbreviation TGRA_5 Bit Bit Bit Bit Bit Bit Bit Bit 24/16/8/0 Module TPU_5 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 TGRB_5 DTCERA DTCE15 DTCE7 DTCE14 DTCE6 DTCE14 DTCE6 DTCE14 DTCE6 DTCE14 DTCE6 DTCE14 DTCE6 DTCE14 DTCE6 DTCE14 DTCE6 DTCE14 DTCE6 -- -- DTCP2 IRQ14E IRQ6E IRQ14F IRQ6F P16 P26 P36 P46 P56 P66 DTCE13 DTCE5 DTCE13 DTCE5 DTCE13 DTCE5 DTCE13 DTCE5 DTCE13 DTCE5 DTCE13 DTCE5 DTCE13 DTCE5 DTCE13 DTCE5 -- INTM1 DTCP1 IRQ13E IRQ5E IRQ13F IRQ5F P15 P25 P35 P45 P55 P65 DTCE12 DTCE4 DTCE12 DTCE4 DTCE12 DTCE4 DTCE12 DTCE4 DTCE12 DTCE4 DTCE12 DTCE4 DTCE12 DTCE4 DTCE12 DTCE4 RRS INTM0 DTCP0 IRQ12E IRQ4E IRQ12F IRQ4F P14 P24 P34 P44 P54 P64 DTCE11 DTCE3 DTCE11 DTCE3 DTCE11 DTCE3 DTCE11 DTCE3 DTCE11 DTCE3 DTCE11 DTCE3 DTCE11 DTCE3 DTCE11 DTCE3 RCHNE NMIEG IPSETE IRQ11E IRQ3E IRQ11F IRQ3F P13 P23 P33 P43 P53 P63 DTCE10 DTCE2 DTCE10 DTCE2 DTCE10 DTCE2 DTCE10 DTCE2 DTCE10 DTCE2 DTCE10 DTCE2 DTCE10 DTCE2 DTCE10 DTCE2 -- -- CPUP2 IRQ10E IRQ2E IRQ10F IRQ2F P12 P22 P32 P42 P52 P62 DTCE9 DTCE1 DTCE9 DTCE1 DTCE9 DTCE1 DTCE9 DTCE1 DTCE9 DTCE1 DTCE9 DTCE1 DTCE9 DTCE1 DTCE9 DTCE1 -- -- CPUP1 IRQ9E IRQ1E IRQ9F IRQ1F P11 P21 P31 P41 P51 P61 DTCE8 DTCE0 DTCE8 DTCE0 DTCE8 DTCE0 DTCE8 DTCE0 DTCE8 DTCE0 DTCE8 DTCE0 DTCE8 DTCE0 DTCE8 DTCE0 ERR -- CPUP0 IRQ8E IRQ0E IRQ8F IRQ0F P10 P20 P30 P40 P50 P60 DTC DTCERB DTCE15 DTCE7 DTCERC DTCE15 DTCE7 DTCERD DTCE15 DTCE7 DTCERE DTCE15 DTCE7 DTCERF DTCE15 DTCE7 DTCERG DTCE15 DTCE7 DTCERH DTCE15 DTCE7 DTCCR INTCR CPUPCR IER -- -- CPUPCE IRQ15E IRQ7E INTC ISR IRQ7F PORT1 PORT2 PORT3 PORT4 PORT5 PORT6 P17 P27 P37 P47 P57 P67 I/O port Rev. 2.00 Mar. 15, 2006 Page 691 of 754 REJ09B0199-0200 Section 20 List of Registers Register Abbreviation PORTA PORTB PORTD P1DR P2DR P3DR P6DR PADR PBDR PDDR PCR PMR NDERH NDERL PODRH PODRL NDRH NDRL ADDRA_0 ADDRB_0 ADDRC_0 ADDRD_0 ADDRE_0 ADDRF_0 ADDRG_0 ADDRH_0 Bit Bit Bit Bit Bit Bit Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 PA7 -- PD7 P17DR P27DR P37DR P67DR PA7DR -- PD7DR G3CMS1 G3INV NDER15 NDER7 POD15 POD7 NDR15 NDR7 PA6 -- PD6 P16DR P26DR P36DR P66DR PA6DR -- PD6DR G3CMS0 G2INV NDER14 NDER6 POD14 POD6 NDR14 NDR6 PA5 -- PD5 P15DR P25DR P35DR P65DR PA5DR -- PD5DR G2CMS1 NDER13 NDER5 POD13 POD5 NDR13 NDR5 PA4 -- PD4 P14DR P24DR P34DR P64DR PA4DR -- PD4DR G2CMS0 NDER12 NDER4 POD12 POD4 NDR12 NDR4 PA3 -- PD3 P13DR P23DR P33DR P63DR PA3DR -- PD3DR G3NOV NDER11 NDER3 POD11 POD3 NDR11 NDR3 PA2 PB2 PD2 P12DR P22DR P32DR P62DR PA2DR PB2DR PD2DR G2NOV NDER10 NDER2 POD10 POD2 NDR10 NDR2 PA1 PB1 PD1 P11DR P21DR P31DR P61DR PA1DR PB1DR PD1DR NDER9 NDER1 POD9 POD1 NDR9 NDR1 Bit 24/16/8/0 PB0 PD0 P10DR P20DR P30DR P60DR PA0DR PB0DR PD0DR NDER8 NDER0 POD8 POD0 NDR8 NDR0 A/D_0 PPG Module I/O port Rev. 2.00 Mar. 15, 2006 Page 692 of 754 REJ09B0199-0200 Section 20 List of Registers Register Abbreviation ADCSR_0 ADCR_0 TCSR TCNT RSTCSR TSTR TSYR TCR_0 TMDR_0 TIORH_0 TIORL_0 TIER_0 TSR_0 TCNT_0 WOVF CCLR2 IOB3 IOD3 TTGE RSTE CCLR1 IOB2 IOD2 CST5 SYNC5 CCLR0 BFB IOB1 IOD1 CST4 SYNC4 CKEG1 BFA IOB0 IOD0 TCIEV TCFV CST3 SYNC3 CKEG0 IOA3 IOC3 TGIED TGFD CST2 SYNC2 TPSC2 MD2 IOA2 IOC2 TGIEC TGFC CST1 SYNC1 TPSC1 MD1 IOA1 IOC1 TGIEB TGFB CST0 SYNC0 TPSC0 MD0 IOA0 IOC0 TGIEA TGFA TPU_0 TPU Bit Bit Bit Bit Bit Bit Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 ADF TRGS1 OVF ADIE TRGS0 WT/IT ADST SCANE TME SCANS CH3 CKS1 CH2 CKS0 CKS2 CH1 CKS1 Bit 24/16/8/0 CH0 CKS0 WDT Module A/D_0 TGRA_0 TGRB_0 TGRC_0 TGRD_0 TCR_1 TMDR_1 TIOR_1 TIER_1 TSR_1 TCNT_1 IOB3 TTGE TCFD CCLR1 IOB2 CCLR0 IOB1 TCIEU TCFU CKEG1 IOB0 TCIEV TCFV CKEG0 IOA3 TPSC2 MD2 IOA2 TPSC1 MD1 IOA1 TGIEB TGFB TPSC0 MD0 IOA0 TGIEA TGFA TPU_1 TGRA_1 TGRB_1 Rev. 2.00 Mar. 15, 2006 Page 693 of 754 REJ09B0199-0200 Section 20 List of Registers Register Abbreviation TCR_2 TMDR_2 TIOR_2 TIER_2 TSR_2 TCNT_2 Bit Bit Bit Bit Bit Bit Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 IOB3 TTGE TCFD CCLR1 IOB2 CCLR0 IOB1 TCIEU TCFU CKEG1 IOB0 TCIEV TCFV CKEG0 IOA3 TPSC2 MD2 IOA2 TPSC1 MD1 IOA1 TGIEB TGFB Bit 24/16/8/0 TPSC0 MD0 IOA0 TGIEA TGFA Module TPU_2 TGRA_2 TGRB_2 TCR_3 TMDR_3 TIORH_3 TIORL_3 TIER_3 TSR_3 TCNT_3 CCLR2 IOB3 IOD3 TTGE CCLR1 IOB2 IOD2 CCLR0 BFB IOB1 IOD1 CKEG1 BFA IOB0 IOD0 TCIEV TCFV CKEG0 IOA3 IOC3 TGIED TGFD TPSC2 MD2 IOA2 IOC2 TGIEC TGFC TPSC1 MD1 IOA1 IOC1 TGIEB TGFB TPSC0 MD0 IOA0 IOC0 TGIEA TGFA TPU_3 TGRA_3 TGRB_3 TGRC_3 TGRD_3 Note: * Parts of the bit functions differ in normal mode and the smart card interface mode. Rev. 2.00 Mar. 15, 2006 Page 694 of 754 REJ09B0199-0200 Section 20 List of Registers 20.3 Register States in Each Operating Mode Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Register Abbreviation SSCRH_0 SSCRL_0 SSMR_0 SSER_0 SSSR_0 SSCR2_0 SSTDR0_0 SSTDR1_0 SSTDR2_0 SSTDR3_0 SSRDR0_0 SSRDR1_0 SSRDR2_0 SSRDR3_0 SSCRH_1 SSCRL_1 SSMR_1 SSER_1 SSSR_1 SSCR2_1 SSTDR0_1 SSTDR1_1 SSTDR2_1 SSTDR3_1 SSRDR0_1 SSRDR1_1 SSRDR2_1 SSRDR3_1 SSCRH_2 SSCRL_2 SSMR_2 SSER_2 SSSR_2 Sleep Module Stop Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized All-ModuleClock-Stop Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Software Standby Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Hardware Standby SSU_0 SSU_1 SSU_2 Rev. 2.00 Mar. 15, 2006 Page 695 of 754 REJ09B0199-0200 Section 20 List of Registers Register Abbreviation SSCR2_2 SSTDR0_2 SSTDR1_2 SSTDR2_2 SSTDR3_2 SSRDR0_2 SSRDR1_2 SSRDR2_2 SSRDR3_2 PHRTIDR APPDCR ADDRA_1 ADDRB_1 ADDRC_1 ADDRD_1 ADDRE_1 ADDRF_1 ADDRG_1 ADDRH_1 ADCSR_1 ADCR_1 TSTRB TSYRB TCR_6 TMDR_6 TIORH_6 TIORL_6 TIER_6 TSR_6 TCNT_6 TGRA_6 TGRB_6 TGRC_6 TGRD_6 Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Sleep Module Stop Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized All-ModuleClock-Stop Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Software Standby Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Hardware Standby SSU_2 I/O port A/D A/D_1 TPU TPU_6 Rev. 2.00 Mar. 15, 2006 Page 696 of 754 REJ09B0199-0200 Section 20 List of Registers Register Abbreviation TCR_7 TMDR_7 TIOR_7 TIER_7 TSR_7 TCNT_7 TGRA_7 TGRB_7 TCR_8 TMDR_8 TIOR_8 TIER_8 TSR_8 TCNT_8 TGRA_8 TGRB_8 TCR_9 TMDR_9 TIORH_9 TIORL_9 TIER_9 TSR_9 TCNT_9 TGRA_9 TGRB_9 TGRC_9 TGRD_9 TCR_10 TMDR_10 TIOR_10 TIER_10 TSR_10 TCNT_10 TGRA_10 TGRB_10 Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Sleep Module Stop All-ModuleClock-Stop Software Standby Hardware Standby TPU_7 TPU_8 TPU_9 TPU_10 Rev. 2.00 Mar. 15, 2006 Page 697 of 754 REJ09B0199-0200 Section 20 List of Registers Register Abbreviation TCR_11 TMDR_11 TIOR_11 TIER_11 TSR_11 TCNT_11 TGRA_11 TGRB_11 P1DDR P2DDR P3DDR P6DDR PADDR PBDDR PDDDR P1ICR P2ICR P3ICR P4ICR P5ICR P6ICR PAICR PBICR PDICR PORTH PORTI PORTJ PORTK PHDR PIDR PJDR PKDR PHDDR PIDDR PJDDR Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Sleep Module Stop All-ModuleClock-Stop Software Standby Hardware Standby TPU_11 I/O port Rev. 2.00 Mar. 15, 2006 Page 698 of 754 REJ09B0199-0200 Section 20 List of Registers Register Abbreviation PKDDR PHICR PIICR PJICR PKICR PDPCR PHPCR PIPCR PJPCR PKPCR P2ODR PFCR9 PFCRA PFCRB SSIER DSAR_0 DDAR_0 DOFR_0 DTCR_0 DBSR_0 DMDR_0 DACR_0 DSAR_1 DDAR_1 DOFR_1 DTCR_1 DBSR_1 DMDR_1 DACR_1 DSAR_2 DDAR_2 DOFR_2 DTCR_2 DBSR_2 DMDR_2 DACR_2 Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Sleep Module Stop All-ModuleClock-Stop Software Standby Hardware Standby I/O port INTC DMAC_0 DMAC_1 DMAC_2 Rev. 2.00 Mar. 15, 2006 Page 699 of 754 REJ09B0199-0200 Section 20 List of Registers Register Abbreviation DSAR_3 DDAR_3 DOFR_3 DTCR_3 DBSR_3 DMDR_3 DACR_3 DMRSR_0 DMRSR_1 DMRSR_2 DMRSR_3 IPRA IPRB IPRC IPRD IPRE IPRF IPRG IPRI IPRK IPRL IPRM IPRN IPRO IPRQ IPRR ISCRH ISCRL DTCVBR BCR2 RAMER Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Sleep Module Stop All-ModuleClock-Stop Software Standby Hardware Standby DMAC_3 DMAC_0 DMAC_1 DMAC_2 DMAC_3 INTC BSC Rev. 2.00 Mar. 15, 2006 Page 700 of 754 REJ09B0199-0200 Section 20 List of Registers Register Abbreviation MDCR SYSCR SCKCR SBYCR MSTPCRA MSTPCRB MSTPCRC SMR_3 BRR_3 SCR_3 TDR_3 SSR_3 RDR_3 SCMR_3 SMR_4 BRR_4 SCR_4 TDR_4 SSR_4 RDR_4 SCMR_4 FCCS FPCS FECS FKEY FMATS FTDAR TCR_4 TMDR_4 TIOR_4 TIER_4 TSR_4 TCNT_4 TGRA_4 TGRB_4 Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Sleep Module Stop Initialized Initialized Initialized Initialized Initialized Initialized All-ModuleClock-Stop Initialized Initialized Initialized Initialized Initialized Initialized Software Standby Initialized Initialized Initialized Initialized Initialized Initialized Hardware Standby SYSTEM SCI_3 SCI_4 FLASH TPU_4 Rev. 2.00 Mar. 15, 2006 Page 701 of 754 REJ09B0199-0200 Section 20 List of Registers Register Abbreviation TCR_5 TMDR_5 TIOR_5 TIER_5 TSR_5 TCNT_5 TGRA_5 TGRB_5 DTCERA DTCERB DTCERC DTCERD DTCERE DTCERF DTCERG DTCERH DTCCR INTCR CPUPCR IER ISR PORT1 PORT2 PORT3 PORT4 PORT5 PORT6 PORTA PORTB PORTD P1DR P2DR P3DR P6DR Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Sleep Module Stop All-ModuleClock-Stop Software Standby Hardware Standby TPU_5 DTC INTC I/O port Rev. 2.00 Mar. 15, 2006 Page 702 of 754 REJ09B0199-0200 Section 20 List of Registers Register Abbreviation PADR PBDR PDDR PCR PMR NDERH NDERL PODRH PODRL NDRH NDRL ADDRA_0 ADDRB_0 ADDRC_0 ADDRD_0 ADDRE_0 ADDRF_0 ADDRG_0 ADDRH_0 ADCSR_0 ADCR_0 TCSR TCNT RSTCSR TSTR TSYR TCR_0 TMDR_0 TIORH_0 TIORL_0 TIER_0 TSR_0 TCNT_0 Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Sleep Module Stop All-ModuleClock-Stop Software Standby Hardware Standby I/O port PPG A/D_0 WDT TPU TPU_0 Rev. 2.00 Mar. 15, 2006 Page 703 of 754 REJ09B0199-0200 Section 20 List of Registers Register Abbreviation TGRA_0 TGRB_0 TGRC_0 TGRD_0 TCR_1 TMDR_1 TIOR_1 TIER_1 TSR_1 TCNT_1 TGRA_1 TGRB_1 TCR_2 TMDR_2 TIOR_2 TIER_2 TSR_2 TCNT_2 TGRA_2 TGRB_2 TCR_3 TMDR_3 TIORH_3 TIORL_3 TIER_3 TSR_3 TCNT_3 TGRA_3 TGRB_3 TGRC_3 TGRD_3 Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Sleep Module Stop All-ModuleClock-Stop Software Standby Hardware Standby TPU_0 TPU_1 TPU_2 TPU_3 Rev. 2.00 Mar. 15, 2006 Page 704 of 754 REJ09B0199-0200 Section 21 Electrical Characteristics Section 21 Electrical Characteristics 21.1 Absolute Maximum Ratings Table 21.1 Absolute Maximum Ratings Item Power supply voltage Input voltage (except ports 4 and 5) Input voltage (port 4) Input voltage (port 5) Analog power supply voltage Symbol VCC Vin Vin Vin AVCC0 AVCC1 Analog input voltage (port 4) Analog input voltage (port 5) Operating temperature Storage temperature VAN VAN Topr Tstg Value -0.3 to +7.0 -0.3 to VCC + 0.3 -0.3 to AVCC1 + 0.3 -0.3 to AVCC0 + 0.3 -0.3 to +7.0 -0.3 to +7.0 -0.3 to AVCC1 + 0.3 -0.3 to AVCC0 + 0.3 -20 to +85* -55 to +125 Unit V V V V V V V V C C Caution: Permanent damage to the LSI may result if absolute maximum ratings are exceeded. Note: * The operating temperature when programming/erasing the flash memory ranges from 0C to +85C. Rev. 2.00 Mar. 15, 2006 Page 705 of 754 REJ09B0199-0200 Section 21 Electrical Characteristics 21.2 DC Characteristics Table 21.2 DC Characteristics (1) Conditions: VCC = 4.5 V to 5.5 V, AVCC0 = 4.5 V to 5.5 V, AVCC1 = 4.5 V to 5.5 V, VSS = AVSS = 0 V*1, Ta = -20C to +85C Item Schmitt trigger input voltage IRQ input pin, TPU input pin, ports 2, 3, J, K Symbol VT - Min. VCC x 0.2 - Typ. Max. VCC x 0.7 VCC + 0.3 VCC + 0.3 VCC + 0.3 AVCC1 + 0.3 AVCC0 + 0.3 VCC x 0.1 VCC x 0.2 VCC x 0.2 AVCC1 x 0.2 AVCC0 x 0.2 0.4 1.0 1.0 1.0 Unit V Test Conditions VT + VT - VT Input high MD, RES, NMI voltage (except EXTAL Schmitt trigger Other input pins input pin) Port 4 Port 5 Input low RES, MD, NMI voltage (except EXTAL Schmitt trigger Other pins input pin) Port 4 Port 5 Output high voltage Output low voltage Input leakage current All output pins VOH VIL VIH + VCC x 0.05 VCC - 0.7 VCC x 0.7 VCC x 0.7 AVCC1 x 0.7 AVCC0 x 0.7 -0.3 -0.3 -0.3 -0.3 -0.3 VCC - 0.5 VCC - 1.0 V V V IOH = -200 A IOH = -1 mA All output pins RES, NMI, MD Port 4 Port 5 VOL |Iin| V A IOL = 1.6 mA Vin = 0.5 to VCC - 0.5 V Vin = 0.5 to AVCC1 - 0.5 V Vin = 0.5 to AVCC0 - 0.5 V Rev. 2.00 Mar. 15, 2006 Page 706 of 754 REJ09B0199-0200 Section 21 Electrical Characteristics Table 21.2 DC Characteristics (2) Conditions: VCC = 4.5 V to 5.5 V, AVCC0 = 4.5 V to 5.5 V, AVCC1 = 4.5 V to 5.5 V, VSS = AVSS = 0 V*1, Ta = -20C to +85C Item Ports 1 to 3, 6, A, Tri-state leakage current B, D, H, I, J, K (off state) Input pull-up MOS current Ports D, H, I, J, K Symbol | ITSI | Min. Typ. Max. 1.0 Unit A Test Conditions Vin = 0.5 to VCC - 0.5 V Vin = 0 V Vin = AVCC0, AVCC1 Vin = 0 V f = 1 MHz Ta = 25C f = 48 MHz Ta 50C 50C < Ta -Ip Ip 50 10 300 30 A A Analog port Ports 4, 5 pull-down MOS current Input capacitance Current 2 consumption* All input pins Cin 15 pF Normal operation Sleep mode Standby mode* 3 ICC* 4 95 75 50 42 3.5 1 3.5 1 107 85 300 1 55 5 5 5 5 mA A mA mA All-module-clock5 stop mode* Analog power supply current During A/D conversion Standby for A/D conversion During A/D conversion Standby for A/D conversion RAM standby voltage VRAM AICC1 AICC0 3.0 AVCC0 = 5.0 V A mA A V AVCC1 = 5.0 V Notes: 1. When the A/D converter is not used, the AVCC0, AVCC1, and AVSS pins should not be open. Connect the AVCC0 and AVCC1 pins to VCC, and the AVSS pin to VSS. 2. Current consumption values are for VIH = AVCC0 (port 5), AVCC1 (port 4), VCC (others) and VIL = 0 V with all output pins unloaded and all input pull-up MOSs in the off state. 3. The values are for VRAM VCC < 4.5 V, VIHmin. = VCC - 0.1 V, and VILmax. = 0.1 V. 4. ICC depends on VCC and f as follows: ICCmax = 12 (mA) + 0.35 (mA/(MHz x V)) x VCC x f (normal operation) ICCmax = 12 (mA) + 0.28 (mA/(MHz x V)) x VCC x f (sleep mode) 5. The values are for reference. Rev. 2.00 Mar. 15, 2006 Page 707 of 754 REJ09B0199-0200 Section 21 Electrical Characteristics Table 21.3 Permissible Output Currents Conditions: VCC = 4.5 V to 5.5 V, AVCC0 = 4.5 V to 5.5 V, AVCC1 = 4.5 V to 5.5 V, VSS = AVSS = 0 V*, Ta = -20C to +85C (regular specifications), Ta = -40C to +85C (wide-range specifications) Item Permissible output low current (per pin) Permissible output low current (total) Permissible output high current (per pin) Permissible output high current (total) Caution: Note: * All output pins Total of all output pins All output pins Total of all output pins Symbol IOL IOL -IOH -IOH Min. Typ. Max. 10 100 2.0 30 Unit mA mA mA mA To protect the LSI's reliability, do not exceed the output current values in table 21.3. When the A/D converter is not used, the AVCC0, AVCC1, and AVSS pins should not be open. Connect the AVCC0 and AVCC1 pins to VCC, and the AVSS pin to VSS. 21.3 AC Characteristics 5V RL C = 30 pF (all ports) RL = 2.4 k RH = 12 k Input/output timing measurement level: low at 0.8 V and high at 2.0 V LSI output pin C RH Figure 21.1 Output Load Circuit Rev. 2.00 Mar. 15, 2006 Page 708 of 754 REJ09B0199-0200 Section 21 Electrical Characteristics 21.3.1 Clock Timing Table 21.4 Clock Timing Conditions: VCC = 4.5 V to 5.5 V, AVCC0 = 4.5 V to 5.5 V, AVCC1 = 4.5 V to 5.5 V, VSS = AVSS = 0 V, I = 8 to 48 MHz, P = 8 to 35 MHz, Ta = -20C to +85C Item Clock cycle time Clock high pulse width Clock low pulse width Clock rising time Clock falling time Oscillation settling time after reset (crystal) Oscillation settling time after leaving software standby mode (crystal) External clock output delay settling time External clock input low pulse width External clock input high pulse width External clock rising time External clock falling time Symbol tcyc tCH tCL tCr tCf tOSC1 tOSC2 tDEXT TEXL TEXH TEXr TEXf Min. 20.8 3 3 20 10 2 45 45 Max. 125 5 5 5 5 Unit. ns ns ns ns ns ms ms ms ns ns ns ns Figure 21.4 Figure 21.3 Figure 21.4 Figure 21.5 External clock input frequency = 4 to 9 MHz Test Conditions Figure 21.2 tcyc tCH I tCf tCL tCr Figure 21.2 System Bus Clock Timing Rev. 2.00 Mar. 15, 2006 Page 709 of 754 REJ09B0199-0200 Section 21 Electrical Characteristics Oscillator I NMI NMIEG SSBY NMI exception handling NMI exception handling NMIEG = 1 SSBY = 1 Software standby mode (power-down mode) Oscillation settling time tOSC2 SLEEP instruction Figure 21.3 Oscillation Settling Timing after Software Standby Mode EXTAL tDEXT VCC tOSC1 RES I Figure 21.4 Oscillation Settling Timing tEXH tEXL EXTAL Vcc x 0.5 tEXr tEXf Figure 21.5 External Input Clock Timing Rev. 2.00 Mar. 15, 2006 Page 710 of 754 REJ09B0199-0200 Section 21 Electrical Characteristics 21.3.2 Control Signal Timing Table 21.5 Control Signal Timing Conditions: VCC = 4.5 V to 5.5 V, AVCC0 = 4.5 V to 5.5 V, AVCC1 = 4.5 V to 5.5 V, VSS = AVSS = 0 V, I = 8 to 48 MHz, Ta = -20C to +85C, Item RES setup time RES pulse width NMI setup time NMI hold time NMI pulse width (after leaving software standby mode) IRQ setup time IRQ hold time IRQ pulse width (after leaving software standby mode) Symbol tRESS tRESW tNMIS tNMIH tNMIW tIRQS tIRQH tIRQW Min. 200 20 150 10 200 150 10 200 Max. Unit ns tcyc ns ns ns ns ns ns Figure 21.7 Test Conditions Figure 21.6 I tRESS RES tRESW tRESS Figure 21.6 Reset Input Timing Rev. 2.00 Mar. 15, 2006 Page 711 of 754 REJ09B0199-0200 Section 21 Electrical Characteristics I tNMIS tNMIH NMI tNMIW tIRQW IRQi* (i = 0 to 15) tIRQS tIRQH IRQ* (edge input) tIRQS IRQ* (level input) Note: * SSIER must be set to cancel software standby mode. Figure 21.7 Interrupt Input Timing 21.3.3 Timing of On-Chip Peripheral Modules Table 21.6 Timing of On-Chip Peripheral Modules (1) Conditions: VCC = 4.5 V to 5.5 V, AVCC0 = 4.5 V to 5.5 V, AVCC1 = 4.5 V to 5.5 V, VSS = AVSS = 0 V, P = 8 to 35 MHz, Ta = -20C to +85C Item I/O ports Output data delay time Input data setup time Input data hold time Realtime input port data hold time TPU Timer output delay time Timer input setup time Timer clock input setup time Timer clock pulse width Single-edge setting Both-edge setting Symbol tPWD tPRS tPRH tRTIPH tTOCD tTICS tTCKS tTCKWH tTCKWL Min. 25 25 4 25 25 1.5 2.5 Max. 40 40 Unit ns ns ns tcyc ns ns ns tcyc tcyc Figure 21.11 Figure 21.9 Figure 21.10 Test Conditions Figure 21.8 Rev. 2.00 Mar. 15, 2006 Page 712 of 754 REJ09B0199-0200 Section 21 Electrical Characteristics Item PPG SCI Pulse output delay time Input clock cycle Asynchronous Clocked synchronous Symbol tPOD tScyc Min. 4 6 Max. 40 0.6 20 20 Unit ns tcyc Test Conditions Figure 21.12 Figure 21.13 Input clock pulse width Input clock rise time Input clock fall time tSCKW tSCKr tSCKf 0.4 tScyc ns ns Figure 21.13 Measurement voltages: VCC x 0.3 V to VCC x 0.7 V Output clock Asynchronous cycle Clocked synchronous Output clock pulse width Output clock rise time Output clock fall time tScyc 30 4 0.6 20 20 tcyc Figure 21.13 tSCKW tSCKr tSCKf 0.4 tScyc ns ns Figure 21.13 Measurement voltages: VCC x 0.3 V to VCC x 0.7 V Transmit data delay time Receive data setup time (clocked synchronous) Receive data hold time (clocked synchronous) A/D Trigger input setup time converter tTXD tRXS tRXH tTRGS 40 40 30 40 ns ns ns ns Figure 21.14 Figure 21.15 Rev. 2.00 Mar. 15, 2006 Page 713 of 754 REJ09B0199-0200 Section 21 Electrical Characteristics Table 21.6 Timing of On-Chip Peripheral Modules (2) Conditions: VCC = 4.5 V to 5.5 V, AVCC0 = 4.5 V to 5.5 V, AVCC1 = 4.5 V to 5.5 V, VSS = AVSS = 0 V, P = 8 to 24 MHz, Ta = -20C to +85C Item SSU Clock cycle time Master Slave Clock high pulse width Master Slave Clock low pulse width Master Slave Clock rising time Clock falling time Data input setup time Master Slave Data input hold time SCS setup time SCS hold time Master Slave Master Slave Master Slave Data output delay time Master Slave Data output hold time Master Slave Consecutive transmit delay time Master Slave Symbol tSUcyc tHI tLO tRISE tFALL tSU tH tLEAD tLAG tOD tOH tTD Min. 4 4 80 80 80 80 25 30 10 10 2.5 2.5 2.5 2.5 30 30 2.5 2.5 Max. 256 256 20 20 40 40 1 1 Unit tcyc ns ns ns ns ns ns tcyc tcyc ns ns tcyc Test Conditions Figure 21.16 Figure 21.17 Figure 21.18 Figure 21.19 Slave access time Slave out release time tSA tREL tcyc tcyc Figure 21.18 Figure 21.19 Rev. 2.00 Mar. 15, 2006 Page 714 of 754 REJ09B0199-0200 Section 21 Electrical Characteristics T1 P tPRS tPRH Ports 1 to 6, A, B, D, H, I, J, K (read) T2 tPWD Ports 1 to 3, 6, A, B, D, H, I, J, K (write) Figure 21.8 I/O Port Input/Output Timing P IRQ14 tRTIPH Port H input Figure 21.9 Data Input Timing for Realtime Input Port P tTOCD Output compare output* tTICS Input capture input* Note: * TIOCA0 to TIOCA5, TIOCB0 to TIOCB5, TIOCC0, TIOCC3, TIOCD0, TIOCD3, TIOCA6 to TIOCA11, TIOCB6 to TIOCB11, TIOCC6, TIOCC9, TIOCD6, and TIOCD9 Figure 21.10 TPU Input/Output Timing Rev. 2.00 Mar. 15, 2006 Page 715 of 754 REJ09B0199-0200 Section 21 Electrical Characteristics P tTCKS TCLKA to TCLKD TCLKE to TCLKH tTCKWL tTCKWH tTCKS Figure 21.11 TPU Clock Input Timing P tPOD PO15 to PO8 Figure 21.12 PPG Output Timing tSCKW SCK3, SCK4 tScyc tSCKr tSCKf Figure 21.13 SCK Clock Input/Output Timing SCK3, SCK4 tTXD TxD3, TxD4 (transmit data) tRXS tRXH RxD3, RxD4 (receive data) Figure 21.14 SCI Input/Output Timing: Clocked Synchronous Mode P tTRGS ADTRG0, ADTRG1 Figure 21.15 A/D Converter External Trigger Input Timing Rev. 2.00 Mar. 15, 2006 Page 716 of 754 REJ09B0199-0200 Section 21 Electrical Characteristics SCS (output) tLEAD SSCK (output) CPOS = 1 tLO tHI SSCK (output) CPOS = 0 tLO SSO (output) tOH SSI (input) tOD tSUcyc tHI tFALL tRISE tLAG tTD tSU tH Figure 21.16 SSU Timing (Master, CPHS = 1) SCS (output) tLEAD SSCK (output) CPOS = 1 tLO tHI SSCK (output) CPOS = 0 tLO SSO (output) tOH SSI (input) tOD tSUcyc tHI tFALL tRISE tLAG tTD tSU tH Figure 21.17 SSU Timing (Master, CPHS = 0) Rev. 2.00 Mar. 15, 2006 Page 717 of 754 REJ09B0199-0200 Section 21 Electrical Characteristics SCS (input) tLEAD SSCK (input) CPOS = 1 tLO tHI SSCK (input) CPOS = 0 tLO SSO (input) tREL tSUcyc tHI tFALL tRISE tLAG tTD tSU SSI (output) tSA tH tOH tOD Figure 21.18 SSU Timing (Slave, CPHS = 1) SCS (input) tLEAD SSCK (input) CPOS = 1 tLO tHI SSCK (input) CPOS = 0 tLO SSO (input) tREL tH tSUcyc tHI tFALL tRISE tLAG tTD tSU SSI (output) tSA tOH tOD Figure 21.19 SSU Timing (Slave, CPHS = 0) Rev. 2.00 Mar. 15, 2006 Page 718 of 754 REJ09B0199-0200 Section 21 Electrical Characteristics 21.3.4 A/D Conversion Characteristics Table 21.7 A/D Conversion Characteristics Conditions: VCC = 4.5 V to 5.5 V, AVCC0 = 4.5 V to 5.5 V, AVCC1 = 4.5 V to 5.5 V, VSS = AVSS = 0 V, P = 8 to 35 MHz, Ta = -20C to +85C Item Conversion time: 5 s or more Resolution Conversion time Analog input capacitance Permissible signal source impedance Nonlinearity error Offset error Full-scale error Quantization error Absolute accuracy Conversion time: 3.4 s to 5.0 s Resolution Conversion time Analog input capacitance Permissible signal source impedance Nonlinearity error Offset error Full-scale error Quantization error Absolute accuracy Min. 10 5.0 10 3.4 Typ. 10 0.5 10 0.5 Max. 10 200 20 5 3.5 3.5 3.5 4.0 10 5 20 1 3.5 3.5 3.5 4.0 Unit Bit s pF k LSB LSB LSB LSB LSB Bit s pF k LSB LSB LSB LSB LSB Rev. 2.00 Mar. 15, 2006 Page 719 of 754 REJ09B0199-0200 Section 21 Electrical Characteristics 21.3.5 Flash Memory Characteristics Table 21.8 Flash Memory Characteristics Conditions: VCC = 4.5 V to 5.5 V, AVCC0 = 4.5 V to 5.5 V, AVCC1 = 4.5 V to 5.5 V, VSS = AVSS = 0 V, I = 8 to 48 MHz, P = 8 to 35 MHz, Ta = 0C to +85C Item Programming time* * * Erase time* * * 1 2 4 1 2 4 Symbol tP tE Min. Typ. 3 80 500 1000 5 Max. 30 800 5000 10000 15 Unit ms/128 bytes ms/4-kbyte block ms/32-kbyte block ms/64-kbyte block s/256 kbytes Test Condition Programming time (total) *1*2*4 Erase time (total) *1*2*4 Programming/erase time (total) *1*2 Number of programming Data retention time* 4 tP Ta = 25C, memory filled with 0. Ta = 25C Ta = 25C tE tPE NWEC tDRP 100*3 10 5 10 15 30 s/256 kbytes s/256 kbytes Times Year Notes: 1. Programming time and erase time depend on data in the flash memory. 2. Programming time and erase time do not include time for data transfer. 3. All the characteristics after programming are guaranteed within this value (guaranteed value is from 1 to Min. value). 4. Characteristics when programming is performed within the Min. value Rev. 2.00 Mar. 15, 2006 Page 720 of 754 REJ09B0199-0200 Appendix Appendix A. Port States in Each Pin State Port States in Each Pin State MCU Operating Mode All All All All All All All All All All All All All Reset Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Software Standby Mode Keep Keep Keep Hi-Z Hi-Z Keep Keep Keep Keep Keep Keep Keep Keep Table A.1 Port Name Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port A Port B Port D Port H Port I Port J Port K Rev. 2.00 Mar. 15, 2006 Page 721 of 754 REJ09B0199-0200 Appendix B. Product Lineup Marking R5F61582 Package (Package Code) PLQP0120LA-A (FP-120B) R5F61582 Product Classification Product Model H8SX/1582 Rev. 2.00 Mar. 15, 2006 Page 722 of 754 REJ09B0199-0200 C. JEITA Package Code P-LQFP120-14x14-0.40 RENESAS Code PLQP0120LA-A Previous Code 120P6R-A / FP-120B / FP-120BV MASS[Typ.] 0.7g HD *1 D 61 90 Package Dimensions 91 60 NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. bp b1 E HE *2 c1 c Reference Symbol Dimension in Millimeters Terminal cross section 120 ZE 31 30 1 ZD F Index mark A A2 A1 For the package dimensions, data in the Renesas IC Package General Catalog has priority. Figure C.1 Package Dimensions (PLQP0120LA-A) c D E A2 HD HE A A1 bp b1 c c1 L L1 y *3 bp e x Detail F Rev. 2.00 Mar. 15, 2006 Page 723 of 754 e x y ZD ZE L L1 Min Nom Max 13.9 14.0 14.1 13.9 14.0 14.1 1.4 15.8 16.0 16.2 15.8 16.0 16.2 1.7 0.05 0.1 0.15 0.13 0.18 0.23 0.16 0.09 0.145 0.20 0.125 0 8 0.4 0.07 0.08 1.2 1.2 0.35 0.5 0.65 1.0 Appendix REJ09B0199-0200 Appendix Rev. 2.00 Mar. 15, 2006 Page 724 of 754 REJ09B0199-0200 Main Revisions and Additions in this Edition Item Section 1 Overview 1.1 Features Page Revision (See Manual for Details) 1 Amended * General I/O port 82 input/output ports Amended * Small package Code PLQP0120LA-A (FP-120B) Package LQFP1414-120 13.1 Pin Assignments Figure 1.2 Pin Assignments of H8SX/1582 1.3 Pin Assignments 1.3.3 Pin Functions Table 1.2 Pin Functions 3 Amended PLQP0120LA-A (FP-120B) (top vew) 14 Amended Classification Abbreviation I/O port PA6 PA5 PA4 PA3 PA2 PA1 PA0 Description 7-bit input/output pins. Section 3 MCU Operating Modes 3.2.2 System Control Register (SYSCR) 65 Deleted SYSCR controls MAC saturation operation, selects bus with mode for instruction fetch, and enables/disables the on-chip RAM and the flash memory control registers. 3.4.1 Address Map (Advanced Mode) 68 Amended On-chip ROM (256 kbytes) H'040000 Reserved H'FF9000 On-chip RAM (12 kbytes) Rev. 2.00 Mar. 15, 2006 Page 725 of 754 REJ09B0199-0200 Item Section 4 Exception Handling 4.9 Usage Note Page Revision (See Manual for Details) 81 Amended TRAPA instruction executed Deleted 5.3.3 Interrupt Priority Registers A to G, I, K to O, Q, and R (IPRA to IPRG, IPRI, IPRK to IPRO, IPRQ, and IPRR) Amended 5.3.3 Interrupt Priority Registers A 89 to G, I, K to O, and R (IPRA to IPRG, IPRI, IPRK to IPRO, and IPRR) 5.5 Interrupt Exception Handling Vector Table Table 5.2 Interrupt Sources, Vector Address Offsets, and Interrupt Priority 107, 108 5.6.5 DTC and DMAC Activation by Interrupt (1) Selection of Interrupt Sources 116 Added ...When transfer by an on-chip module interrupt is enabled (DTF1 = 1, DTF0 = 0, and DTE = 1 in DMDR) and the DTA bit in DMDR is set to 1, ... ...an interrupt request is made to the CPU by clearing the DTCE bit to 0 after the DTC and DMAC data transfer. When the same interrupt source is set as both the DTC and DMAC activation source and CPU interrupt source, the DTC and DMAC must be given priority over the CPU. ...Therefore, the CPUP setting or the IPR setting corresponding to the interrupt source must be set to lower than or equal to the DTCP and DMAP settings. If the CPU is given priority, the DTC and DMAC may not be activated and the data transfer may be performed. Rev. 2.00 Mar. 15, 2006 Page 726 of 754 REJ09B0199-0200 Item (3) Operation Order Page Revision (See Manual for Details) 117 Added Table 5.6 lists the selection of DMAC activation sources and the selection of interrupt sources and interrupt source clear control by means of the setting of the DTA bit in DMDR of the DMAC... Amended Interrupt Source Selection/ DMAC Setting DTA 0 DTC Setting DTCE 0 1 DISEL * 0 1 1 * * DMAC O O O Clear Control DTC X O X CPU X X (4) Usage Note 117 Added The interrupt sources of the SCI, A/D converter, and SSU are cleared according to the setting... To initiate multiple channels for the DTC and DMAC with the same interrupt, the same priority (DTCP = DMAP) should be assigned. 5.8.6 Interrupt Flags of Peripheral 123 Modules Amended To clear an interrupt request flag of a peripheral module by the CPU, the flag must be read from after being cleared within the interrupt handling routine even if the peripheral module clock is not generated by dividing the system clock. This makes the request signal synchronized with the system clock. 6.6.1 Write Data Buffer Function for Peripheral Module This LSI has a write data buffer function for the peripheral module. ..., if a peripheral module write continues for two cycles or longer, and there is an internal access next, only the peripheral module write is executed in the first two cycles. 6.6.1 Write Data Buffer Function for Peripheral Module 130 Rev. 2.00 Mar. 15, 2006 Page 727 of 754 REJ09B0199-0200 Item Page Revision (See Manual for Details) Amended Data Transfer Acknowledge This bit is valid while the DMA transfer is performed by the on-chip module interrupt. This bit decides whether the source flag selected by DMRSR is cleared or not. 0: The source flag is not cleared while the DMA transfer is performed by the on-chip module interrupt. Since the source flag is not cleared by the DMA transfer, it should be cleared by the CPU. 1: The source flag is cleared while the DMA transfer is performed by the on-chip module interrupt. Since the source flag is cleared by the DMA transfer, there is no need to request an interrupt to the CPU. Section 7 DMA Controller (DMAC) 151 7.2.6 DMA Mode Control Register (DMDR) * Bit 5 7.4.2 Transfer Modes (1) Normal Transfer Mode 165 Deleted The TEND signal is output only in the last DMA transfer. The DACK signal is output every time a transfer request is received and a transfer starts. (2) Repeat Transfer Mode 166 Amended The TEND and DACK signals are is output only in the last DMA 7.4.3 Activation Sources (2) Activation by On-Chip Module Interrupt 169 Added The interrupt request selected as an activation source can simultaneously generate interrupt requests to the CPU. For details, see section 5, Interrupt Controller. When the DMAC is activated with DTA = 1, the interrupt request flag is automatically cleared by a DMA transfer. When the DMAC is activated with DTA = 0, the interrupt request flag is not cleared by the DMAC. Thus it should be cleared by the CPU. 7.4.6 Address Update Function using Offset 7.4.6 Address Update Function using Offset 175 Amended External memory External memory External memory 0 1, 2, or 4 + offset Address not updated Data access size added to or subtracted from address (addresses are continuous) (b) Increment or decrement by 1, 2, or 4 Offset is added to address (addresses are not continuous) (c) Offset addition (a) Address fixed 7.4.9 DMA Basic Bus Cycle 185 Amended HHWR, HLWR, LHWR Rev. 2.00 Mar. 15, 2006 Page 728 of 754 REJ09B0199-0200 Item Page Revision (See Manual for Details) Deleted Origin of Activation Source TPU_5 Activation Source TGI5A TGI5B TMR_0 CMIA0 CMIB0 TMR_1 CMIA1 CMIB1 TMR_2 CMIA2 CMIB2 TMR_3 CMIA3 CMIB3 DMAC TPU_11 DMTEND0 TGI11A or reserved for system use TGI11B or reserved for system use SCI_5 RXI5 TXI5 193 194 H'704 H'708 DTCEF7 DTCEF6 189 H'6F4 DTCEF9 Vector Number 110 111 116 117 119 120 122 123 125 126 128 188 DTC Vector Address Offset H'5B8 H'5BC H'5D0 H'5D4 H'5DC H'5E0 H'5E8 H'5EC H'5F4 H'5F8 H'600 H'6F0 DTCE*1 DTCEC15 DTCEC14 DTCEC13 DTCEC12 DTCEC11 DTCEC10 DTCEC9 DTCEC8 DTCEC7 DTCEC6 DTCEC5 DTCEF10 Section 8 Data Transfer Controller 221, (DTC) 222 Table 8.1 Interrupt Sources, DTC Vector Addresses, and Corresponding DTCEs Section 9 I/O Ports 9.1 Register Descriptions 249 Amended Number of Port Port 6 Port A Pins 8 8 9.1.5 Pull-Up MOS Control Register (PnPCR) (n = D, H, J, and K) Table 9.3 Input Pull-Up MOS State 253 Amended Port Port D Pin State On-chip peripheral module output Port input Port H Port output Port input Port J On-chip peripheral module output Port input Port K On-chip peripheral module output Port input Reset OFF OFF OFF OFF OFF OFF OFF OFF Software Standby Mode OFF ON/OFF OFF ON/OFF OFF ON/OFF OFF ON/OFF Rev. 2.00 Mar. 15, 2006 Page 729 of 754 REJ09B0199-0200 Item Page Revision (See Manual for Details) Added (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) Amended ...Upon counter clearing by a cycle register compare match, ... 405 Added (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) Section 10 16-Bit Timer Pulse Unit 331 (TPU) to 334 10.3.5 Timer Status Register (TSR) * Bit 5 to 0 351 10.4.5 PWM Modes 2. PWM mode 2 Section 12 Watchdog Timer (WDT) 12.2 Register Descriptions 12.2.2 Timer Control/Status Register (TCSR) * Bit 7 409 12.4 Interrupt Source Table 12.1 WDT Interrupt Source Amended Interrupt Name WOVI Source TCNT overflow Interrupt Flag OVF DTC Activation Impossible DMAC Activation Impossible Section 13 Serial Communication 425 Interface (SCI) to 427 12.3.7 Serial Status Register (SSR) Bit Functions in Normal Serial Communication Interface Mode * Bit 7 to 3 428 to 430 441 Bit Functions in Smart Card Interface Mode * Bit 7 to 3 Added (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) Added (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) Amended M = | (0.5 - 1 ) - (L - 0.5) F - | D - 0.5 | 2N N 13.4.2 Receive Data Sampling Timing and Reception Margin in Asynchronous Mode 13.9.6 Restrictions on Using DMAC (1 + F ) | x 100[%] 477 Amended ...and wait for at least five P clock cycles before... Rev. 2.00 Mar. 15, 2006 Page 730 of 754 REJ09B0199-0200 Item Section 14 Synchronous Serial Communication Unit (SSU) * BIt 6, 3 to 0 Page Revision (See Manual for Details) Amended (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) Added Be sure not to access invalid SSTDRs. 497 Added 492 to 14.3.5 SS Status Register (SSSR) 494 14.3.7 SS Transmit Data Registers 0 to 3 (SSTDR0 to SSTDR3) Table 14.2 Correspondence Between DATS Bit Setting and SSTDR 496 14.3.8 SS Receive Data Registers 198 0 to 3 (SSRDR0 to SSRDR3) Table 14.3 Correspondence Between DATS Bit Setting and SSRDR 14.4.5 SSU Mode Table 14.5 Communication Modes and Pin States of SSCK Pin Table 14.6 Communication Modes and Pin States of SCS Pin Figure 14.4 Example of Initial Settings in SSU Mode 504 499 Added Be sure not to access invalid SSRDRs Added 503 Amended [Legend] : Not used as SSU pin (can be used as I/O port) Amended Start setting initial values [4] Specify MLS, CPOS, CPHS, CKS2, CKS1, and CKS0 bits in SSMR Specify SDOS, SSCKOS, SCSOS, TENDSTS, SCSATS and SSODTS bits in SSCR2 [5] Specify TE, RE, TEIE, TIE, RIE, and CEIE bits in SSER simultaneously End Figure 14.6 Flowchart Example of 507 Data Transmission (SSU Mode) Deleted Start [1] Initial setting TE = 1 (transmission enabled) [2] Read TDRE in SSSR Rev. 2.00 Mar. 15, 2006 Page 731 of 754 REJ09B0199-0200 Item Page Revision (See Manual for Details) Deleted Start [1] Initial setting RE = 1 (receprion started) Figure 14.8 Flowchart Example of 510 Data Reception (SSU Mode) [2] Dummy-read SRDR Figure 14.9 Flowchart Example of 511 Simultaneous Transmission/Reception (SSU Mode) Amended Start [1] Initial setting Transmission/reception started (TE = 1, RE = 1) [2] Read TDRE in SSSR Consecutive data transmission/reception? No Read TEND in SSSR No TEND = 1? Yes Clear TEND in SSSR to 0 Error processing No Has the 1 bit transfer period elapsed? Yes Clear TE and RE in SSER to 0 End transmission/reception 14.4.6 SCS Pin Control and Conflict Error Figure 14.10 Conflict Error Detection Timing (Before Transfer) Figure 14.11 Conflict Error Detection Timing (After Transfer End) 512 Amended ...the SCS pin functions as an input (Hi-Z) to detect a conflict error. 512 Amended Conflict error detection period Rev. 2.00 Mar. 15, 2006 Page 732 of 754 REJ09B0199-0200 Item 14.4.7 Clock Synchronous Communication Mode Figure 14.12 Example of Initial Settings in Clock Synchronous Communication Mode Page Revision (See Manual for Details) 513 Amended Start setting initial values [4] Specify CPOS, CKS2, CKS1, and CKS0 bits in SSMR Specify SDOS, SSCKOS, SCSOS, TENDSTS, SCSATS, and SSODTS bits in SSCR2 [5] Specify TE, RE, TEIE, TIE, RIE, and CEIE bits in SSER simultaneously End Figure 14.14 Flowchart Example of Transmission Operation 515 Deleted Start [1] Initial setting TE = 1 (transmission enabled) [2] Read TDRE in SSSR Figure 14.16 Flowchart Example of Data Reception 517 Deleted Start [1] Initial setting RE = 1 (receprion started) Read SSSR Rev. 2.00 Mar. 15, 2006 Page 733 of 754 REJ09B0199-0200 Item Figure 14.17 Flowchart Example of Simultaneous Transmission/Reception Page Revision (See Manual for Details) 518 Amended Start [1] Initial setting Transmission/reception started (TE = 1, RE = 1) [2] Read TDRE in SSSR Consecutive data transmission/reception? No Read TEND in SSSR No TEND = 1? Yes Clear TEND in SSSR to 0 Error processing No Has the 1 bit transfer period elapsed? Yes Clear TE and RE in SSER to 0 End transmission/reception 14.5 Interrupt Requests 519 Deleted When an interrupt condition shown in table 14.7 is satisfied, an interrupt is requested. Clear the interrupt source by CPU, DTC, or DMAC data transfer. Table 14.5 Interrupt Sources 519 Amended Channel 0 Abbreviation SSERI0 Interrupt Source Overrun error Conflict error SSRXI0 SSTXI0 Receive data register full Transmit data register empty Transmit end 1 SSERI1 Overrun error Conflict error SSRXI1 SSTXI1 Receive data register full Transmit data register empty Transmit end 2 SSERI2 Overrun error Conflict error SSRXI2 SSTXI2 Receive data register full Transmit data register empty Transmit end DTC Activation Rev. 2.00 Mar. 15, 2006 Page 734 of 754 REJ09B0199-0200 Item Section 15 A/D Converter 15.1 Features Page Revision (See Manual for Details) 521 Amended Conversion time: 3.4 s per channel (at 35-MHz operation) Amended Figure 15.1 Block Diagram of A/D 522 Converter (Unit 0/AD_0) AVCC0 10-bit D/A AVSS Figure 15.2 Block Diagram of A/D 523 Converter (Unit 1/AD_1) Amended AVCC1 10-bit D/A AVSS Multiplexer Control circuit AN14 AN15 ADTRG1 ADI1 interrupt signal Conversion start trigger from the TPU 15.3.2 A/D Control/Status Register (ADCSR) * Bit 7 527 Added (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) 15.3.2 A/D Control/Status Register (ADCSR) * Bit 5 527 Amended In scan mode, A/D conversion continues sequentially on the specified channels until this bit is cleared to 0 by software or a reset. 15.8.6 Notes on Noise Countermeasures 543 Amended AN0 to AN15 Rev. 2.00 Mar. 15, 2006 Page 735 of 754 REJ09B0199-0200 Item Section 16 RAM Page Revision (See Manual for Details) 545 Amended Product Classification Flash memory version H8SX/1582 RAM Size 12 kbytes RAM Addresses H'FF9000 to H'FFBFFF Section 17 Flash Memory (0.18m F-ZTAT Version) 547 Amended Programming/erasing time Programming time: 3 ms (typ) for 128-byte simultaneous programming, 23.4 s per byte Erasing time: 1000 ms (typ) per 1 block (64 kbytes) Number of programming The number of programming can be up to 100 times at the minimum. (1 to 100 times are guaranteed.) 17.2 Mode Transition Diagram Figure 17.2 Mode Transition of Flash Memory 549 Added Notes: In this LSI, the user program mode is defined as the period from the timing when a program concerning programming and erasure is started in user mode to the timing when the program is completed. 1. Programming and erasure is started. 2. Programing and erasure is completed. 17.7.1 Programming/Erasing Interface Registers (4) Flash Key Code Register (FKEY) 17.7.2 Programming/Erasing Interface Parameters Table 17.4 Parameters and Target Modes 560 Amended H'5A: Programming/erasing of the flash memory is enabled. (When FKEY is a value other than H'5A, the software protection state is entered.) 563 Amended Parameter DPFR FPFR FPEFEQ FMPAR FMPDR FEBS Download O Rev. 2.00 Mar. 15, 2006 Page 736 of 754 REJ09B0199-0200 Item 17.7.2 Programming/Erasing Interface Parameters (b) Programming * Bit 4 17.7.2 Programming/Erasing Interface Parameters (c) Erasure * Bit 4 (3) Flash Program/Erase Frequency Parameter (FPEFEQ: General Register ER0 of CPU) (6) Flash Erase Block Select Parameter (FEBS: General Register ER0 of CPU) Page Revision (See Manual for Details) 568 Amended Checks the FKEY value (H'5A) before erasure starts, and returns the result. 570 Amended Checks the FKEY value (H'5A) before erasure starts, and returns the result. 570 FPEFEQ sets the operating frequency of the CPU. The CPU operating frequency available in this LSI ranges from 8 MHz to 48 MHz. Amended FEBS specifies the erase block number. Settable values for the erase block numbers range from 0 to 11 (H'00000000 to H'0000000B). A value of 0 corresponds to block EB0 and a value of 11 corresponds to block EB11. An error occurs when a value outside the range (from 0 to 11) is set. 581 Amended DPFR (Return value: 1 byte) System use area (15 bytes) Area to be downloaded (size: 4 kbytes) Unusable area during programming/erasing 574 17.8.2 User Program Mode (1) On-Chip RAM Address Map when Programming/Erasing is Executed Figure 17.10 RAM Map when Programming/Erasing is Executed FTDAR setting Programming/erasing program entry Initialization program entry Initialization + programming program or Initialization + erasing program RAM emulation area or area that can be used by user Area that can be used by user FTDAR setting + 16 bytes FTDAR setting + 32 bytes FTDAR setting + 4 kbytes H'FFBFFF Rev. 2.00 Mar. 15, 2006 Page 737 of 754 REJ09B0199-0200 Item (2) Programming Procedure in User Program Mode Figure 17.11 Programming Procedure in User Program Mode Page Revision (See Manual for Details) 582 Amended 1 Disable interrupts and bus master operation other than CPU Set FKEY to H'5A 9. 10. Set parameters to ER1 and ER0 (FMPAR and FMPDR) Programming 11. Programming JSR FTDAR setting + 16 FPFR = 0? 12. 13. No Clear FKEY and programming error processing 14. Yes No Required data programming is completed? Yes Clear FKEY to 0 15. End programming procedure program (2) Programming Procedure in User Program Mode 583 Amended The area that can be executed in the steps of the procedure program (on-chip RAM and user MAT, and external space) is shown in section 17.8.4, On-Chip Program and Storable Area for Program Data. Rev. 2.00 Mar. 15, 2006 Page 738 of 754 REJ09B0199-0200 Item (2) Programming Procedure in User Program Mode Page Revision (See Manual for Details) 584, 585, 586 Amended 7. Initialization is executed. The initialization program is downloaded together with the programming program to the on-chip RAM. The entry point of the initialization program is at the address which is 32 bytes after #DLTOP (start address of the download destination specified by FTDAR). Call the subroutine to execute initialization by using the following steps. The general registers other than ER0 and ER1 are held in the initialization program. 12. Programming is executed. The entry point of the programming program is a the address which is 16 bytes after #DLTOP (start address of the download destination specified by FTDAR). Call the subroutine to execute programming by using the following steps. The general registers other than ER0 and ER1 are held in the programming program. (3) Erasing Procedure in User Program Mode Figure 17.12 Erasing Procedure in User Program Mode 587 Amended 1 Disable interrupts and bus master operation other than CPU Set FKEY to H'5A Set FEBS parameter Erasing JSR FTDAR setting + 16 FPFR = 0? 2. 3. 4. Erasing No Clear FKEY and erasing error processing Yes No Required block erasing is completed? 5. Yes Clear FKEY to 0 6. End erasing procedure program Rev. 2.00 Mar. 15, 2006 Page 739 of 754 REJ09B0199-0200 Item (3) Erasing Procedure in User Program Mode Page Revision (See Manual for Details) 588 Amended The area that can be executed in the steps of the procedure program (on-chip RAM and user MAT, and external space) is shown in section 17.8.4, On-Chip Program and Storable Area for Program Data. 588 Amended 3. Erasure is executed. As in programming, the entry point of the erasing program is at the address which is 16 bytes after #DLTOP (start address of the download destination specified by FTDAR). Call the subroutine to execute erasure by using the following steps. The general registers other than ER0 and ER1 are held in the erasing program. (4) Procedure of Erasing, 590 Programming, and RAM Emulation in User Program Mode Amended * Be sure to initialize both the programming program and erasing program. When the FPEFEQ parameter is initialized, also initialize both the erasing program and programming program. Initialization must be executed for both entry addresses: 32 bytes after #DLTOP (start address of download destination for erasing program), and 32 bytes after #DLTOP (start address of download destination for programming program). Rev. 2.00 Mar. 15, 2006 Page 740 of 754 REJ09B0199-0200 Item 17.8.3 User Boot Mode Figure 17.14 Procedure for Programming User MAT in User Boot Mode Page Revision (See Manual for Details) 591 Amended Start programming procedure program Select on-chip program to be downloaded and specify download destination by FTDAR Set FKEY to H'A5 Set SCO to 1 after initializing VBR and execute download Set FKEY to H'5A 1 Set FMATS to value other than H'AA to select user MAT MAT switchover Download Clear FKEY to 0 Set parameter to ER0 and ER1 (FMPAR and FMPDR) Programming JSR FTDAR setting + 16 FPFR = 0 ? User-boot-MAT selection state No Download error processing Yes Set the FPEFEQ parameter Programming DPFR = 0 ? User-MAT selection state No Yes Clear FKEY and programming error processing Initialization Initialization JSR FTDAR setting + 32 FPFR = 0 ? No Required data programming is completed? Yes No Clear FKEY to 0 Yes Initialization error processing Set FMATS to H'AA to select user boot MAT MAT switchover Disable interrupts and bus master operation other than CPU User-boot-MAT End programming procedure program selection state Note: The MAT must be switched by FMATS to perform the programming error processing in the user boot MAT. 1 Figure 17.15 Procedure for Erasing User MAT in User Boot Mode 593 Amended Start erasing procedure program Select on-chip program to be downloaded and specify download destination by FTDAR 1 Set FMATS to value other than H'AA to select user MAT MAT switchover Set FKEY to H'A5 Set SCO to 1 after initializing VBR and execute download Set FKEY to H'5A Download Clear FKEY to 0 Set FEBS parameter Programming JSR FTDAR setting + 16 User-boot-MAT selection state Yes Erasing No Download error processing User-MAT selection state DPFR = 0 ? FPFR = 0 ? Yes No Required block erasing is completed? Yes Set the FPEFEQ parameter No Clear FKEY and erasing error processing Initialization Initialization JSR FTDAR setting + 32 FPFR = 0 ? No Clear FKEY to 0 Yes Initialization error processing Set FMATS to H'AA to select user boot MAT MAT switchover Disable interrupts and bus master operation other than CPU User-boot-MAT End erasing procedure program Note: The MAT must be switched by FMATS to perform the erasing error processing in the user boot MAT. 1 selection state Rev. 2.00 Mar. 15, 2006 Page 741 of 754 REJ09B0199-0200 Item 17.11 Switching between User MAT and User Boot MAT Figure 17.20 Switching between User MAT and User Boot MAT Page Revision (See Manual for Details) 606 Added Procedure for switching to the user boot MAT 2. 2. Write H'AA to FMATS*. Write other than H'AA to FMATS*. Procedure for switching to the user MAT Note: * Set the FLSHE bit in the system control register (SYSCR) to 1 when making access to FMATS. 17.13 Standard Serial Communication Interface Specifications for Boot Mode (4) Receive Data Check (8) Programming/Erasing State 620 Deleted 3. Operating frequency error 624 Amended Command H'4C H'4D H'4C Command Name User boot MAT blank check User MAT blank check User boot MAT blank check Description Checks the blank data of the user boot MAT Checks the blank data of the user MAT Checks whether the contents of the user boot MAT are blank H'4D User MAT blank check Checks whether the contents of the user MAT are blank H'4F Boot program status inquiry Inquires into the boot program's status 17.14 Usage Notes 636, 637 Added 10. To program the flash memory, the program data and program must be allocated to addresses which are higher than those of the external interrupt vector table and H'FF must be written to all the system reserved areas in the exception handling vector table. 11. The programming program that includes the initialization routine and the erasing program that includes the initialization routine are each 4 kbytes or less. Accordingly, when the CPU clock frequency is 48 MHz, the download for each program takes approximately 35 ms at the maximum. 15. The contents of some general registers are not saved in a programming/ programming end/erasing program. When needed, save general registers in the procedure program. Rev. 2.00 Mar. 15, 2006 Page 742 of 754 REJ09B0199-0200 Item Page Revision (See Manual for Details) Amended SCKCR controls B clock output and frequencies of the system, peripheral module, and external clocks, and selects the B clock to be output. Bit 15 Bit Name PSTOP1 Description B Clock Output Enable Controls B output on PA7. * Normal operation 0: B output 1: Fixed high * * Software standby mode Hardware standby mode X: Fixed high X: Hi-Z Section 18 Clock Pulse Generator 641 18.1 Register Description 18.1.1 System Clock Control Register (SCKCR) 18.5 Usage Notes 18.5.1 Notes on Clock Pulse Generator 645 Deleted 5. When I > P is specified by SCKCR, signals from the peripheral modules must be synchronized with the system clock. When CPU instructions are used to clear the interrupt source flag of a peripheral module, the flag must be read after being cleared to 0. Rev. 2.00 Mar. 15, 2006 Page 743 of 754 REJ09B0199-0200 Item Section 19 Power-Down Modes 19.2 Register Descriptions Page Revision (See Manual for Details) 651 to 653 Amended Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W 15 SSBY 0 R/W 7 0 R/W 14 1 R/W 6 0 R/W 13 0 R/W 5 0 R/W 12 STS4 0 R/W 4 0 R/W 11 STS3 1 R/W 3 0 R/W 10 STS2 1 R/W 2 0 R/W 9 STS1 1 R/W 1 0 R/W 8 STS0 1 R/W 0 0 R/W Bit 15 14 13 12 11 10 9 8 Bit Name SSBY STS4 STS3 STS2 STS1 STS0 Initial Value 0 1 0 0 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W Added Initial Bit 7 to 0 Bit Name Value All 0 R/W R/W Description ReservedThese bits are always read as 0. The write value should always be 0. 19.7.4 Software Standby Mode Application Example Section 20 List of Registers 20.1 Register Addresses (Address Order) 661 669 Amended I Added Number of Register Name Abbr. Bits Address* Module Data Width Access Cycles (Read/Write) Port A data direction register Port B data direction register Port D data direction register PADDR PBDDR PDDDR 8 8 8 H'FFB89 H'FFB8A H'FFB8C I/O port I/O port I/O port 8 8 8 2P/2P 2P/2P 2P/2P Rev. 2.00 Mar. 15, 2006 Page 744 of 754 REJ09B0199-0200 Item Section 20 List of Registers Page Revision (See Manual for Details) 670 Amended Number of Register Name Abbr. Bits Address* Module Data Width Access Cycles (Read/Write) Port A input buffer PAICR control register Port B input buffer PBICR control register Port D input buffer PDICR control register 8 H'FFB99 I/O port 8 2P/2P 8 H'FFB9A I/O port 8 2P/2P 8 H'FFB9C I/O port 8 2P/2P Port H data direction register Port I data direction register Port J data direction register PHDDR 8 H'FFBA8 I/O port 8 2P/2P PIDDR 8 H'FFBA9 I/O port 8 2P/2P PJDDR 8 H'FFBAA I/O port 8 2P/2P Port H input buffer PHICR control register Port I input buffer control register Port J input buffer control register PIICR 8 H'FFBAC I/O port 8 2P/2P 8 H'FFBAD I/O port 8 2P/2P PJICR 8 H'FFBAE I/O port 8 2P/2P Port H pull-up MOS control register Port I pull-up MOS control register Port J pull-up MOS control register PHPCR 8 H'FFBB8 I/O port 8 2P/2P PIPCR 8 H'FFBB9 I/O port 8 2P/2P PJPCR 8 H'FFBBA I/O port 8 2P/2P 672 Amended Register Name Standby control register Abbr. SBYCR Number of Bits 16 Rev. 2.00 Mar. 15, 2006 Page 745 of 754 REJ09B0199-0200 Item 20.2 Register Bits Page Revision (See Manual for Details) 683 Added Register Abbreviation Bit 31/ 23/15/7 Bit 30/ 22/14/6 Bit 29/ 21/13/5 Bit 28/ 20/12/4 Bit 27/ 19/11/3 Bit 26/ 18/10/2 Bit 25/ 17/9/1 Bit 24/ 16/8/0 Module PORTH PORTI PORTJ PH7 PI7 PJ7 PH6 PI6 PJ6 PH5 PI5 PJ5 PH4 PI4 PJ4 PH3 PI3 PJ3 PH2 PI2 PJ2 PH1 PI1 PJ1 PH0 PI0 PJ0 I/O Ports 689 Amended Register Abbreviation SYSCR Bit 31/ 23/15/7 FLSHE SCKCR Bit 30/ 22/14/6 Bit 29/ 21/13/5 MACS POSEL1 PCK1 Bit 28/ 20/12/4 PCK0 STS4 Bit 27/ 19/11/3 STS3 Bit 26/ 18/10/2 ICK2 BCK2 STS2 Bit 25/ 17/9/1 DTCMD ICK1 BCK1 STS1 Bit 24/ 16/8/0 RAME ICK0 BCK0 STS0 Module SYSTEM PSTOP1 PCK2 SBYCR SSBY Section 21 Electrical Characteristics 21.1 Absolute Maximum Ratings Table 21.1 Absolute Maximum Ratings 705 Amended Item Operating temperature Symbol Topr Value Regular specifications: -20 to +75* Wide-range specifications: -40 to +85* Note: * The operating temperature when programming/erasing the flash memory ranges from 0C to +85C for regular specification products and from 0C to +85C for wide-range specification products. Unit C 21.2 DC Characteristics Table 21.2 DC Characteristics (2) 707 Amended Notes: 4. ICC depends on VCC and f as follows: ICCmax = 12 (mA) + 0.35 (mA/(MHz x V)) x VCC x f (normal operation) ICCmax = 12 (mA) + 0.28 (mA/(MHz x V)) x VCC x f (sleep mode) Rev. 2.00 Mar. 15, 2006 Page 746 of 754 REJ09B0199-0200 Item 21.2 DC Characteristics Table 21.2 DC Characteristics (1) Table 21.2 DC Characteristics (2) Table 21.3 Permissible Output Currents Table 21.4 Clock Timing Table 21.5 Control Signal Timing Table 21.6 Timing of On-Chip Peripheral Modules (1) Table 21.6 Timing of On-Chip Peripheral Modules (2) Table 21.7 A/D Conversion Characteristics Table 21.8 Flash Memory Characteristics Page Revision (See Manual for Details) 706 to 709, 711, 712, 714, 719, 720 Amended Conditions: VCC = 4.5 V to 5.5 V, AVCC0 = 4.5 V to 5.5 V, AVCC1 = 4.5 V to 5.5 V, VSS = AVSS = 0 V*1, Ta = -20C to +85C (regular specifications), Ta = -40C to +85C (wide-range specifications) Table 21.2 DC Characteristics (2) 707 Amended Item Current 2 consumption* Normal operation Sleep mode Standby mode*3 Typ. 95 75 50 All-module-clock5 stop mode* 42 Max. 107 85 300 1 55 A mA mA Ta 50C 50C < Ta Unit mA Test Conditions f = 48 MHz Notes: 2. Current consumption values are for VIH = AVCC0 (port 5), AVCC1 (port 4), VCC (others) and VIL = 0 V with all output pins unloaded and all input pull-up MOSs in the off state. Figure 21.7 Interrupt Input Timing 712 Amended I tNMIS tNMIH NMI tNMIW tIRQW IRQi* (i = 0 to 15) tIRQS tIRQH IRQ* (edge input) tIRQS IRQ* (level input) Note: * SSIER must be set to cancel software standby mode. Rev. 2.00 Mar. 15, 2006 Page 747 of 754 REJ09B0199-0200 Item Table 21.6 Timing of On-Chip Peripheral Modules (2) Page Revision (See Manual for Details) 714 Amended Item SSU Clock cycle time Master Slave Clock high pulse width Master Slave Test Conditions Figure 21.16 Figure 21.17 Figure 21.18 Figure 21.19 Slave access time Slave out release time Figure 21.18 Figure 21.19 21.3.5 Flash Memory Characteristics Table 21.8 Flash Memory Characteristics 720 Amended Item Programming time* * * Erase time* * * 124 124 Symbol tP tE Min. Typ. 3 80 500 1000 5 5 10 3 Max. 30 800 5000 Unit ms/128 bytes ms/4-kbyte block ms/32-kbyte block 10000 ms/64-kbyte block 15 15 30 s/256 kbytes s/256 kbytes s/256 kbytes Times Year Programming time (total) * * * Erase time (total) * * * 124 124 tP tE 12 100* 10 Programming/erase time (total) * * Number of programming Data retention time* 4 tPE NWEC tDRP Notes: 4. Characteristics when programming is performed within the Min. value Appendix B. Product Lineup Figure C.1 Package Dimensions (PRQP0100KB-A) 722 723 Amended PLQP0120LA-A (FP-120B) Changed Rev. 2.00 Mar. 15, 2006 Page 748 of 754 REJ09B0199-0200 Index Numerics 0-output/1-output .................................... 341 16-bit timer pulse unit (TPU) ................. 291 C Chain transfer.......................................... 232 Clock....................................................... 442 Clock pulse generator ............................. 639 Clock synchronous communication mode ....................................................... 513 Clocked synchronous mode .................... 455 Communications protocol ....................... 609 CPU priority control function over DTC and DMAC............................. 118 Crystal resonator ..................................... 643 Cycle stealing mode................................ 171 A A/D conversion accuracy........................ 538 A/D converter ......................................... 521 Absolute accuracy................................... 538 Absolute maximum ratings..................... 705 AC characteristics................................... 708 Address error ............................................ 74 Address error exception handling ............. 76 Address map ............................................. 68 Address modes........................................ 161 All-module-clock-stop mode .......... 650, 658 Analog port pull-down function ............. 540 Asynchronous mode ............................... 439 AT-cut parallel-resonance type............... 643 Available output signal and settings in each port ............................................. 280 D Data direction register............................. 251 Data register............................................ 251 Data transfer controller (DTC)................ 207 DC characteristics ................................... 706 Direct convention.................................... 464 DMA controller (DMAC) ....................... 135 Double-buffered structure ....................... 439 Download pass/fail result parameter....... 565 DTC vector address................................. 220 DTC vector address offset....... 220, 221, 222 DTC vector table..................................... 218 Dual address mode.................................. 161 B B clock output control .......................... 662 Bit rate .................................................... 432 Block diagram............................................. 2 Block structure........................................ 552 Block transfer mode................................ 231 Boot mode ...................................... 549, 576 Burst access mode .................................. 172 Bus access modes ................................... 171 Bus arbitration ........................................ 131 Bus configuration ................................... 127 Bus controller (BSC) .............................. 125 Bus-released state ..................................... 61 E Electrical characteristics ......................... 705 Error protection....................................... 601 Error signal ............................................. 464 Exception handling ................................... 69 Exception handling by general illegal instruction ................................................. 79 Exception handling vector table................ 70 Rev. 2.00 Mar. 15, 2006 Page 749 of 754 REJ09B0199-0200 Exception-handling state .......................... 61 Extended repeat area............................... 159 Extended repeat area function ................ 172 External bus clock (B) .................. 128, 639 External clock......................................... 644 External interrupts .................................. 100 External trigger input.............................. 537 F Flash erase block select parameter ......... 574 Flash memory ......................................... 547 Flash multipurpose address area parameter ................................................ 572 Flash multipurpose data destination parameter ................................................ 573 Flash pass and fail parameter.................. 566 Flash program/erase frequency parameter ................................................ 570 Free-running count operation ................. 339 Frequency divider ................................... 645 Full address mode................................... 218 Full-scale error........................................ 538 Internal interrupts.................................... 101 Internal peripheral bus ............................ 127 Internal system bus 1 .............................. 127 Interrupt .................................................... 77 Interrupt control mode 0 ......................... 109 Interrupt control mode 2 ......................... 111 Interrupt controller.................................... 83 Interrupt exception handling ..................... 77 Interrupt exception handling sequence ... 113 Interrupt exception handling vector table.............................................. 102 Interrupt response times.......................... 114 Interrupt sources ..................................... 100 Interrupt sources and vector address offsets...................................................... 102 Interval timer mode................................. 409 Inverse convention.................................. 465 IRQn interrupts ....................................... 100 M Mark state ....................................... 439, 476 MCU operating modes.............................. 63 Memory MAT configuration .................. 551 Mode 1 ...................................................... 67 Mode 2 ...................................................... 67 Mode 3 ...................................................... 67 Mode pin................................................... 63 Module stop mode .................................. 657 Multi-clock function ....................... 128, 657 Multiprocessor bit ................................... 449 Multiprocessor communication function ................................................... 449 G General illegal instruction ........................ 79 H Hardware protection ............................... 600 I I/O ports.................................................. 243 ID code ................................................... 449 Illegal instruction...................................... 78 Input buffer control register.................... 252 Internal bus ............................................. 129 Rev. 2.00 Mar. 15, 2006 Page 750 of 754 REJ09B0199-0200 N NMI interrupt.......................................... 100 Nonlinearity error ................................... 538 Normal transfer mode ............................. 228 O Offset addition ........................................ 175 Offset error ............................................. 538 On-board programming .......................... 576 On-board programming mode ................ 547 On-chip baud rate generator ................... 442 Open-drain control register..................... 254 Oscillator ................................................ 643 Output buffer control .............................. 255 Output trigger ......................................... 394 Overflow................................................. 408 Q Quantization error ................................... 538 R RAM ....................................................... 545 Register addresses (address order) .......... 666 Register bits ............................................ 678 Register configuration in each port ......... 249 Register states in each operating mode ... 695 Registers ADCR ......................... 529, 675, 693, 703 ADCSR ....................... 527, 675, 693, 703 ADDR ......................... 526, 675, 692, 703 APPDCR..................... 530, 667, 679, 696 BCR2 .......................... 126, 672, 689, 700 BRR ............................ 432, 673, 690, 701 CCR ...................................................... 28 CPUPCR ....................... 87, 674, 691, 702 CRA .................................................... 213 CRB .................................................... 214 DACR ......................... 153, 671, 684, 699 DAR.................................................... 213 DBSR .......................... 143, 671, 684, 699 DDAR ......................... 140, 671, 684, 699 DDR............................ 251, 669, 682, 698 DMDR ........................ 144, 671, 684, 699 DMRSR ...................... 160, 672, 687, 700 DOFR.......................... 141, 671, 684, 699 DPFR .................................................. 565 DR............................... 251, 675, 692, 702 DSAR.......................... 139, 671, 684, 699 DTCCR ............................................... 216 DTCER ............................................... 214 DTCR.......................... 142, 671, 684, 699 DTCVBR ............................................ 217 EXR ...................................................... 30 FCCS........................... 557, 673, 690, 701 FEBS................................................... 574 FECS........................... 559, 673, 690, 701 Rev. 2.00 Mar. 15, 2006 Page 751 of 754 REJ09B0199-0200 P Package....................................................... 1 Package dimensions................................ 723 Parity bit ................................................. 439 Peripheral module clock (P) ......... 128, 639 Pin assignments .......................................... 3 Pin configuration in each operating mode .. 4 Pin functions ............................................... 8 PLL circuit...................................... 639, 645 Port function controller........................... 284 Port H realtime input data register.......... 254 Port register............................................. 252 Port states in each pin state ..................... 721 Power-down modes ................................ 649 Processing states ....................................... 61 Product lineup......................................... 722 Program execution state............................ 61 Program stop state .................................... 61 Programmable pulse generator (PPG) .... 381 Programmer mode .................................. 607 Programming/erasing interface............... 553 Programming/erasing interface parameters............................................... 563 Programming/erasing interface register.. 556 Protection................................................ 600 Pull-up MOS control register.................. 253 FKEY...........................560, 673, 690, 701 FMATS........................561, 673, 690, 701 FMPAR .............................................. 572 FMPDR .............................................. 573 FPCS............................559, 673, 690, 701 FPEFEQ.............................................. 570 FPFR................................................... 566 FTDAR........................562, 673, 690, 701 General registers ................................... 27 ICR ..............................252, 669, 682, 698 IER.................................91, 674, 691, 702 INTCR ...........................86, 674, 691, 702 IPR.................................89, 672, 688, 700 ISCRH ...........................93, 672, 689, 700 ISCRL............................93, 672, 689, 700 ISR.................................98, 674, 691, 702 MAC..................................................... 31 MDCR ...........................64, 672, 689, 701 MRA................................................... 210 MRB ................................................... 211 MSTPCRA ..................653, 673, 689, 701 MSTPCRB...................653, 673, 689, 701 MSTPCRC...................656, 673, 689, 701 NDERH .......................383, 675, 692, 703 NDERL........................383, 675, 692, 703 NDRH..........................386, 675, 692, 703 NDRL ..........................386, 675, 692, 703 ODR.............................254, 670, 683, 699 PC ......................................................... 28 PCR .................................................... 670 PCR .....253, 389, 675, 683, 692, 699, 703 PFCR9 .........................284, 670, 683, 699 PFCRA ........................286, 670, 683, 699 PFCRB.........................287, 670, 683, 699 PHRTIDR ....................254, 667, 679, 696 PMR.............................390, 675, 692, 703 PODRH .......................384, 675, 692, 703 PODRL ........................384, 675, 692, 703 PORT...........................252, 674, 691, 702 RAMER.......................575, 672, 689, 700 Rev. 2.00 Mar. 15, 2006 Page 752 of 754 REJ09B0199-0200 RDR ............................ 416, 673, 689, 701 RSR..................................................... 416 RSTCSR ..................... 406, 676, 693, 703 SAR..................................................... 212 SBR....................................................... 30 SBYCR ....................... 651, 672, 689, 701 SCKCR ....................... 640, 672, 689, 701 SCMR ......................... 431, 673, 689, 701 SCR............................. 420, 673, 689, 701 SMR.................... 417, 673, 689, 690, 701 SSCR2......................... 495, 666, 678, 695 SSCRH........................ 486, 666, 678, 695 SSCRL ........................ 488, 666, 678, 695 SSER........................... 490, 666, 678, 695 SSIER ........................... 99, 670, 683, 699 SSMR.......................... 489, 666, 678, 695 SSR ............................. 424, 673, 689, 701 SSRDR........................ 498, 666, 678, 695 SSSR ........................... 491, 666, 678, 695 SSTDR........................ 496, 666, 678, 695 SSTRSR.............................................. 499 SYSCR.......................... 65, 672, 689, 701 TCNT.................. 335, 404, 676, 693, 703 TCR............................. 305, 676, 693, 703 TCSR .......................... 404, 676, 693, 703 TDR ............................ 417, 673, 690, 701 TGR ............................ 335, 676, 693, 704 TIER ........................... 329, 676, 693, 703 TIOR ........................... 311, 676, 693, 703 TMDR......................... 310, 676, 693, 703 TSR ..................... 331, 417, 676, 693, 703 TSTR........................... 336, 676, 693, 703 TSYR .......................... 337, 676, 693, 703 VBR ...................................................... 30 Repeat transfer mode .............................. 229 Reset ......................................................... 72 Reset exception handling .......................... 72 Reset state ................................................. 61 Resolution ............................................... 538 S Sample-and-hold circuit.......................... 535 Scan mode .............................................. 533 Serial communication interface (SCI) .... 413 Short address mode................................. 218 Single address mode ............................... 163 Single mode ............................................ 531 Sleep mode ..................................... 650, 658 Slot illegal instruction............................... 79 Smart card interface................................ 463 Software protection................................. 601 Software standby mode................... 650, 659 SSU mode ............................................... 504 Stack status after exception handling........ 80 Standard serial communication interface specifications for boot mode................... 607 Start bit ................................................... 439 State transitions......................................... 62 Stop bit.................................................... 439 Synchronous clearing.............................. 344 Synchronous presetting........................... 344 Synchronous serial communication unit (SSU)............................................... 481 System clock (I)............................ 128, 639 Trace exception handling .......................... 74 Transfer clock ......................................... 500 Transfer modes........................................ 165 Transmit/receive data.............................. 439 Trap instruction exception handling.......... 78 U User boot MAT ............................... 547, 606 User boot mode ....................................... 590 User MAT ....................................... 547, 606 User program mode................................. 580 V Vector table address.................................. 70 Vector table address offset........................ 70 W Watchdog timer (WDT) .......................... 403 Watchdog timer mode............................. 408 Write data buffer function....................... 130 Write data buffer function for peripheral module ................................... 130 T Toggle output.......................................... 341 Rev. 2.00 Mar. 15, 2006 Page 753 of 754 REJ09B0199-0200 Rev. 2.00 Mar. 15, 2006 Page 754 of 754 REJ09B0199-0200 Renesas 32-Bit CISC Microcomputer Hardware Manual H8SX/1582 Publication Date: Rev.1.00, Sep. 16, 2004 Rev.2.00, Mar. 15, 2006 Published by: Sales Strategic Planning Div. Renesas Technology Corp. Edited by: Customer Support Department Global Strategic Communication Div. Renesas Solutions Corp. 2006. Renesas Technology Corp., All rights reserved. Printed in Japan. Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan RENESAS SALES OFFICES Refer to "http://www.renesas.com/en/network" for the latest and detailed information. Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501 Renesas Technology Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K. Tel: <44> (1628) 585-100, Fax: <44> (1628) 585-900 Renesas Technology (Shanghai) Co., Ltd. Unit 204, 205, AZIACenter, No.1233 Lujiazui Ring Rd, Pudong District, Shanghai, China 200120 Tel: <86> (21) 5877-1818, Fax: <86> (21) 6887-7898 Renesas Technology Hong Kong Ltd. 7th Floor, North Tower, World Finance Centre, Harbour City, 1 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel: <852> 2265-6688, Fax: <852> 2730-6071 Renesas Technology Taiwan Co., Ltd. 10th Floor, No.99, Fushing North Road, Taipei, Taiwan Tel: <886> (2) 2715-2888, Fax: <886> (2) 2713-2999 Renesas Technology Singapore Pte. Ltd. 1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632 Tel: <65> 6213-0200, Fax: <65> 6278-8001 Renesas Technology Korea Co., Ltd. Kukje Center Bldg. 18th Fl., 191, 2-ka, Hangang-ro, Yongsan-ku, Seoul 140-702, Korea Tel: <82> (2) 796-3115, Fax: <82> (2) 796-2145 http://www.renesas.com Renesas Technology Malaysia Sdn. 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